о?AD8021

FEATURESLow Noise2.1 nV/√Hz Input Voltage Noise2.1 pA/√Hz Input Current NoiseCustom CompensationConstant Bandwidth from G = –1 to G = –10High Speed200 MHz (G = –1)190 MHz (G = –10)Low Power34 mW or 6.7 mA Typ for 5 V SupplyOutput Disable Feature, 1.3 mALow Distortion–93 dB Second Harmonic, fC = 1 MHz–108 dB Third Harmonic, fC = 1 MHzDC Precision1 mV Max Input Offset Voltage0.5 ␮V/؇C Input Offset Voltage DriftWide Supply Range, 5 V to 24 VLow PriceSmall PackagingAvailable in SOIC-8 and MSOP-8APPLICATIONSADC Preamp and DriverInstrumentation PreampActive FiltersPortable InstrumentationLine ReceiversPrecision InstrumentsUltrasound Signal ProcessingHigh Gain CircuitsPRODUCT DESCRIPTIONThe AD8021 is a very high performance, high speed voltagefeedback amplifier that can be used in 16-bit resolution systems.It is designed to have low voltage and current noise (2.1nV/√Hztyp and 2.1 pA/√Hz typ) while operating at the lowest quiescentsupply current (7 mA @ ±5 V) among today’s high speed, lownoise op amps. The AD8021 operates over a wide range ofsupply voltages from ±2.5 V to ±12 V, as well as from single5 V supplies, making it ideal for high speed, low power instru-ments. An output disable pin allows further reduction of thequiescent supply current to 1.3 mA.REV.D

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Low Noise, High Speed Amplifierfor 16-Bit SystemsAD8021CONNECTION DIAGRAMSOIC-8 (R-8)MSOP-8 (RM-8)LOGICREFERENCE1AD80218DISABLE–IN27+VS+IN36VOUT–VS45CCOMPThe AD8021 allows the user to choose the gain bandwidthproduct that best suits the application. With a single capacitor,the user can compensate the AD8021 for the desired gain withlittle trade-off in bandwidth. The AD8021 is a very well behavedamplifier that settles to 0.01% in 23 ns for a 1 V step. It has a fastoverload recovery of 50 ns.The AD8021 is stable over temperature with low input offsetvoltage drift and input bias current drift, 0.5 µV/°C and 10 nA/°C,respectively. The AD8021 is also capable of driving a 75Ω linewith ±3 V video signals.The AD8021 is not only technically superior, but also pricedconsiderably less than comparable amps drawing much higherquiescent current. The AD8021 is a high speed, general-purposeamplifier, ideal for a wide variety of gain configurations, and canbe used throughout a signal processing chain and in control loops.The AD8021 is available in both standard 8-lead SOIC and MSOPpackages in the industrial temperature range of –40°C to +85°C.24VOUT = 50mV p-p2118G = –10, RF = 1k⍀, RG = 100⍀,BRIN = 100⍀, CC = 0pFd –15 NIAG = –5, RF = 1k⍀, RG = 200⍀,G12 RPIN = 66.5⍀, CC = 1.5pFOO9L-DE6SG = –2, RF = 499⍀, RG = 249⍀,OL3RIN = 63.4⍀, CC = 4pFC0G = –1, RF = 499⍀, RG = 499⍀,–3RIN = 56.2⍀, CC = 7pF–60.1M1M10M100M1GFREQUENCY – HzFigure 1.Small Signal Frequency ResponseOne Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781/329-4700 www.analog.comFax: 781/326-8703© 2003 Analog Devices, Inc. All rights reserved.

AD8021–SPECIFICATIONSVS = ؎5 VParameterDYNAMIC PERFORMANCE–3 dB Small Signal Bandwidth(@ TA = 25؇C, VS = 5 V, RL = 1 k⍀, Gain = +2, unless otherwise noted.)

ConditionsG = +1, CC = 10 pF, VO = 0.05 V p-pG = +2, CC = 7 pF, VO = 0.05 V p-pG = +5, CC = 2 pF, VO = 0.05 V p-pG = +10, CC = 0 pF, VO = 0.05 V p-pG = +1, CC = 10 pFG = +2, CC = 7 pFG = +5, CC = 2 pFG = +10, CC = 0 pFVO = 1 V Step, RL = 500 ΩAD8021AR/AD8021ARMMinTypMax3551601501109512025038049020518515012015030042023UnitMHzMHzMHzMHzV/µsV/µsV/µsV/µsnsSlew Rate, 1 V StepSettling Time to 0.01%Overload Recovery (50%)DISTORTION/NOISE PERFORMANCEf = 1 MHzHD2HD3f = 5 MHzHD2HD3Input Voltage NoiseInput Current NoiseDifferential Gain Error±2.5 V Input Step, G = +250nsVO = 2 V p-pVO = 2 V p-pVO = 2 V p-pVO = 2 V p-pf = 50 kHzf = 50 kHzNTSC, RL = 150 Ω–93–108–70–802.12.10.03dBcdBcdBcdBcnV/√HzpA/√Hz%2.6Differential Phase ErrorDC PERFORMANCEInput Offset VoltageInput Offset Voltage DriftInput Bias CurrentInput Bias Current DriftInput Offset CurrentNTSC, RL = 150 Ω0.040.40.57.5100.11.010.50.5DegreesmVµV/°CµAnA/°C±µATMIN to TMAX+Input or –InputOpen-Loop GainINPUT CHARACTERISTICSInput ResistanceCommon-Mode Input CapacitanceInput Common-Mode Voltage Range8286101–4.1 to +4.6dBMΩpFVCommon-Mode Rejection RatioOUTPUT CHARACTERISTICSOutput Voltage SwingLinear Output CurrentShort-Circuit CurrentVCM = ±4 V–86–3.5 to +3.2–98–3.8 to +3.46075dBVmAmACapacitive Load Drive for 30% OvershootDISABLE CHARACTERISTICSOff IsolationTurn-On TimeTurn-Off TimeVO = 50 mV p-p/1 V p-pf = 10 MHzVO = 0 V to 2 V, 50% Logic to 50% OutputVO = 0 V to 2 V, 50% Logic to 50% Output15/120–404550pFdBnsnsDISABLE Voltage—Off/OnEnabled Leakage CurrentDisabled Leakage CurrentPOWER SUPPLYOperating RangeQuiescent Current+Power Supply Rejection Ratio–Power Supply Rejection RatioSpecifications subject to change without notice.VDISABLE – VLOGIC REFERENCELogic Ref = 0.4 VDISABLE = 4.0 VLogic Ref = 0.4 VDISABLE = 0.4 V1.75/1.907023033±2.25±57.01.3–95±12.07.71.6VµAµAµAµAVmAmAdBOutput EnabledOutput DisabledVCC = +4 V to +6 V, VEE = –5 VVCC = +5 V, VEE = –6 V to –4 V–86–86–95dB–2–REV. D

AD8021

VS = ؎12 V(@ T = 25؇C, R = 1 k⍀, Gain = +2, unless otherwise noted.)

A

L

ParameterDYNAMIC PERFORMANCE–3 dB Small Signal BandwidthConditionsG = +1, CC = 10 pF, VO = 0.05 V p-pG = +2, CC = 7 pF, VO = 0.05 V p-pG = +5, CC = 2 pF, VO = 0.05 V p-pG = +10, CC = 0 pF, VO = 0.05 V p-pG = +1, CC = 10 pFG = +2, CC = 7 pFG = +5, CC = 2 pFG = +10, CC = 0 pFVO = 1 V Step, RL = 500 Ω±6 V Input Step, G = +2 AD8021AR/AD8021ARMMinTypMax52017517012510514026005602202001651301703404602190UnitMHzMHzMHzMHzV/µsV/µsV/µsV/µsnsnsSlew Rate, 1 V StepSettling Time to 0.01%Overload Recovery (50%)DISTORTION/NOISE PERFORMANCEf = 1 MHzHD2HD3f = 5 MHzHD2HD3Input Voltage NoiseInput Current NoiseDifferential Gain ErrorDifferential Phase ErrorDC PERFORMANCEInput Offset VoltageInput Offset Voltage DriftInput Bias CurrentInput Bias Current DriftInput Offset CurrentOpen-Loop GainINPUT CHARACTERISTICSInput ResistanceCommon-Mode Input CapacitanceInput Common-Mode Voltage RangeCommon-Mode Rejection RatioVO = 2 V p-pVO = 2 V p-pVO = 2 V p-pVO = 2 V p-pf = 50 kHzf = 50 kHzNTSC, RL = 150 ΩNTSC, RL = 150 Ω–95–116–71–832.12.10.030.040.40.28100.188101–11.1 to +11.6–96–10.6 to +10.27011515/120–4045501.80/1.957023033±2.25±57.81.7–96–100dBcdBcdBcdBcnV/√HzpA/√Hz%DegreesmVµV/°CµAnA/°C±µAdBMΩpFVdBVmAmApFdBnsnsVµAµAµAµA±12.0V8.6mA2.0mAdBdB2.61.011.30.5TMIN to TMAX+Input or –Input84VCM = ±10 V–86–10.2 to +9.8OUTPUT CHARACTERISTICSOutput Voltage SwingLinear Output CurrentShort-Circuit CurrentCapacitive Load Drive for 30% OvershootVO = 50 mV p-p/1 V p-pDISABLE CHARACTERISTICSOff IsolationTurn-On TimeTurn-Off TimeDISABLE Voltage—Off/OnEnabled Leakage CurrentDisabled Leakage CurrentPOWER SUPPLYOperating RangeQuiescent Current+Power Supply Rejection Ratio–Power Supply Rejection RatioSpecifications subject to change without notice.f = 10 MHzVO = 0 V to 2 V, 50% Logic to 50% OutputVO = 0 V to 2 V, 50% Logic to 50% OutputVDISABLE – VLOGIC REFERENCELogic Ref = 0.4 VDISABLE = 4.0 VLogic Ref = 0.4 VDISABLE= 0.4 VOutput EnabledOutput DisabledVCC = +11 V to +13 V, VEE = –12 VVCC = +12 V, VEE = –13 V to –11 V–86–86REV. D–3–

AD8021

VS = 5 V(@ T = 25؇C, R = 1 k⍀, Gain = +2, unless otherwise noted.)

A

L

ParameterDYNAMIC PERFORMANCE–3 dB Small Signal BandwidthConditionsG = +1, CC = 10 pF, VO = 0.05 V p-pG = +2, CC = 7 pF, VO = 0.05 V p-pG = +5, CC = 2 pF, VO = 0.05 V p-pG = +10, CC = 0 pF, VO = 0.05 V p-pG = +1, CC = 10 pFG = +2, CC = 7 pFG = +5, CC = 2 pFG = +10, CC = 0 pFVO = 1 V Step, RL = 500 Ω0 V to 2.5 V Input Step, G = +2 AD8021AR/AD8021ARMMinTypMax27015513595801102102903051901651301101402803902840UnitMHzMHzMHzMHzV/µsV/µsV/µsV/µsnsnsSlew Rate, 1 V StepSettling Time to 0.01%Overload Recovery (50%)DISTORTION/NOISE PERFORMANCEf = 1 MHzHD2HD3f = 5 MHzHD2HD3Input Voltage NoiseInput Current NoiseDC PERFORMANCEInput Offset VoltageInput Offset Voltage DriftInput Bias CurrentInput Bias Current DriftInput Offset CurrentOpen-Loop GainINPUT CHARACTERISTICSInput ResistanceCommon-Mode Input CapacitanceInput Common-Mode Voltage RangeCommon-Mode Rejection RatioOUTPUT CHARACTERISTICSOutput Voltage SwingLinear Output CurrentShort-Circuit CurrentCapacitive Load Drive for 30% OvershootDISABLE CHARACTERISTICSOff IsolationTurn-On TimeTurn-Off TimeDISABLE Voltage—Off/OnEnabled Leakage CurrentDisabled Leakage CurrentPOWER SUPPLYOperating RangeQuiescent Current+Power Supply Rejection Ratio–Power Supply Rejection RatioSpecifications subject to change without notice.VO = 2 V p-pVO = 2 V p-pVO = 2 V p-pVO = 2 V p-pf = 50 kHzf = 50 kHz–84–91–68–812.12.10.40.87.5100.1761010.9 to 4.6–981.10 to 3.60305010/120–4045501.55/1.707023033±2.25±56.71.2–82–84dBcdBcdBcdBcnV/√HzpA/√HzmVµV/°CµAnA/°C±µAdBMΩpFVdBVmAmApFdBnsnsVµAµAµAµA±12.0V7.5mA1.5mAdBdB2.61.010.30.5TMIN to TMAX+Input or –Input721.5 V to 3.5 V–841.25 to 3.38VO = 50 mV p-p/1 V p-pf = 10 MHzVO = 0 V to 1 V, 50% Logic to 50% OutputVO = 0 V to 1 V, 50% Logic to 50% OutputVDISABLE – VLOGIC REFERENCELogic Ref = 0.4 VDISABLE = 4.0 VLogic Ref = 0.4 VDISABLE = 0.4 VOutput EnabledOutput DisabledVCC = 4.5 V to 5.5 V, VEE = 0 VVCC = +5 V, VEE = –0.5 V to +0.5 V–74–76–4–REV. 0

AD8021

ABSOLUTE MAXIMUM RATINGS1MAXIMUM POWER DISSIPATION (mW)2.0Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26.4 VPower Dissipation . . . . . . . . Observed Power Derating CurvesInput Voltage (Common-Mode) . . . . . . . . . . . . . . . ±VS ± 1 VDifferential Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . ±0.8 VDifferential Input Current . . . . . . . . . . . . . . . . . . . . . ±10 mAOutput Short-Circuit Duration . . . . . . . . . . . . . . . . . . . . . .Observed Power Derating CurvesStorage Temperature . . . . . . . . . . . . . . . . . . –65∞C to +125∞COperating Temperature Range . . . . . . . . . . . –40∞C to +85∞CLead Temperature Range (Soldering, 10 sec) . . . . . . . . 300∞CNOTES1Stresses above those listed under Absolute Maximum Ratings may cause perma-nent damage to the device. This is a stress rating only and functional operation ofthe device at these or any other conditions above those indicated in the operationalsection of this specification is not implied. Exposure to absolute maximum ratingconditions for extended periods may affect device reliability.2The AD8021 inputs are protected by diodes. Current-limiting resistors are notused in order to preserve the low noise. If a differential input exceeds ±0.8 V, theinput current should be limited to ±10 mA.1.58-LEAD SOIC1.08-LEAD MSOP0.50.01–55–45–35–25–15–5515253555657585AMBIENT TEMPERATURE (؇C)Figure 2.Maximum Power Dissipation vs. Temperature**Specification is for device in free air:8-Lead SOIC: ␪JA = 125∞C/W8-Lead MSOP: ␪JA = 145∞C/WMAXIMUM POWER DISSIPATIONThe maximum power that can be safely dissipated by the AD8021is limited by the associated rise in junction temperature. The maxi-mum safe junction temperature for plastic encapsulated devicesis determined by the glass transition temperature of the plastic,approximately 150∞C. Temporarily exceeding this limit may causea shift in parametric performance due to a change in the stressesexerted on the die by the package. Exceeding a junction tempera-ture of 175∞C for an extended period can result in device failure.While the AD8021 is internally short-circuit protected, this maynot be sufficient to guarantee that the maximum junction tem-perature (150∞C) is not exceeded under all conditions. To ensureproper operation, it is necessary to observe the maximum powerderating curves.PIN CONFIGURATIONLOGICREFERENCE–IN+IN–VS1234PIN FUNCTION DESCRIPTIONSPin No.Mnemonic12345678FunctionLOGIC REFERENCEReference for Pin 8* VoltageLevel. Connect to logic lowsupply.–INInverting Input+INNoninverting InputNegative Supply Voltage–VSCompensation Capacitor. TieCCOMPto –VS. (See the Applicationssection for value.)OutputVOUTPositive Supply Voltage+VSDISABLEDisable, Active Low*AD80218765DISABLE+VSVOUTCCOMP*When Pin 8 (DISABLE) is about 2 V or more higher than Pin 1 (LOGICREFERENCE), the part is enabled. When Pin 8 is brought down to within about1.5 V ofPin 1, the part is disabled. (See the Specification tables for exact disable andenable voltage levels.) If the disable feature is not going to be used, Pin 8 can be tiedto +VS or a logic high source, and Pin 1 can be tied to ground or logic low. Alterna-tively, if Pin 1 and Pin 8 are not connected, the part will be in an enabled state.ORDERING GUIDEModelAD8021ARAD8021AR-REELAD8021AR-REEL7AD8021ARMAD8021ARM-REELAD8021ARM-REEL7AD8021ARZ*AD8021ARZ-REEL*AD8021ARZ-REEL7**Z = Lead FreeTemperature Range–40∞C to +85∞C–40∞C to +85∞C–40∞C to +85∞C–40∞C to +85∞C–40∞C to +85∞C–40∞C to +85∞C–40∞C to +85∞C–40∞C to +85∞C–40∞C to +85∞CPackage Description8-Lead SOIC8-Lead SOIC8-Lead SOIC8-Lead MSOP8-Lead MSOP8-Lead MSOP8-Lead SOIC8-Lead SOIC8-Lead SOICPackage OutlineR-8R-8R-8RM-8RM-8RM-8R-8R-8R-8BrandingHNAHNAHNACAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readilyaccumulate on the human body and test equipment and can discharge without detection. Although theAD8021 features proprietary ESD protection circuitry, permanent damage may occur on devicessubjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommendedto avoid performance degradation or loss of functionality.REV. D–5–

AD8021–Typical Performance Characteristics

(TA = 25ЊC, VS = ؎5 V, RL = 1 k⍀, G = +2, RF = RG = 499 ⍀, RS = 49.9 ⍀, RO = 976 ⍀, RD = 53.6 ⍀, CC = 7 pF, CL = 0, CF = 0, VOUT = 2 V p-p,Freq = 1 MHz, unless otherwise noted.)

2421G = 10, RF = 1k⍀, RG = 110⍀, CC = 0pF18Bd –15G = 5, RF = 1k⍀, RG = 249⍀, CC = 2pF NIAG12 POO9LG = 2, R-DE6F = RG = 499⍀, CC = 7pFSOL3CG = 1, R⍀, C0F = 75C = 10pF–3–60.1M

1M

10M

100M

1G

FREQUENCY – Hz

TPC 1.Small Signal Frequency Response vs.Frequency and Gain, VOUT = 50 mV p-p,Noninverting. See Test Circuit 1.242118G = –10, RF = 1k⍀, RG = 100⍀,RIN = 100⍀, CC = 0pF15G = –5, RF = 1k⍀, RB12G = 200⍀,dR IN = 66.5⍀, CC = 1.5pF– N9IAG6G = –2, RF = 499⍀, RG = 249⍀,3RIN = 63.4⍀, CC = 4pF0G = –1, RF = 499⍀, RG = 499⍀,–3RIN = 56.2⍀, CC = 7pF–60.1M1M10M100M1GFREQUENCY – HzTPC 2.Small Signal Frequency Responsevs. Frequency and Gain, VOUT = 50 mV p-p,Inverting. See Test Circuit 1.9G = 2C8C = 5pF77pF6B5d –9pF N4IAG3217pF9pF0–10.1M1M10M100M1GFREQUENCY – HzTPC 3.Small Signal Frequency Response vs.Frequency and Compensation Capacitor,VOUT = 50 mV p-p. See Test Circuit 1.9G = 28VS = ؎2.5V؎5V76B5d – N4IAG3؎12V2VS = ؎2.5V10–11M10M100M1GFREQUENCY – HzTPC 4.Small Signal Frequency Response vs.Frequency and Supply, VOUT = 50 mV p-p,Noninverting. See Test Circuit 1.3G = –12VS = ؎2.5V1؎5V0B–1VS = ؎12Vd – N–2IAG–3–4–5VS = ؎2.5V–6–71M10M100M1GFREQUENCY – HzTPC 5.Small Signal Frequency Response vs.Frequency and Supply, VOUT = 50 mV p-p,Inverting. See Test Circuit 3.9G = 287VOUT = 0.1V AND 50mV p-p6B5d – N4IAVGOUT = 4V p-p1V p-p3210–11M10M100M1GFREQUENCY – Hz TPC 6.Frequency Response vs. Frequency and VOUT, Noninverting. See Test Circuit 1.–6–REV. D

10 G = 2987B6d – N5IAG41k⍀3R2L = 100⍀100.1M1M10M100M1GFREQUENCY – HzTPC 7.Large Signal Frequency Response vs.Frequency and Load, Noninverting. See TestCircuit 2.9G = 2+85؇C8+25؇C76B5–40؇CVdOUT = –+85؇C50mV p-p N4IAGV3OUT =2V p-p21+25؇C0–40؇C–11M10M100M1GFREQUENCY – Hz TPC 8.Frequency Response vs. Frequency, Temperature and VOUT, Noninverting. See Test Circuit 1.18G = 250pF1530pF1220pF910pFB6d – N3IAG00pF–3–6–9–121M10M100M1GFREQUENCY – HzTPC 9.Small Signal Frequency Response vs.Frequency and Capacitive Load, Noninverting,VOUT = 50 mV p-p. See Test Circuit 2 and Figure 16.REV. DAD8021

10G = 2RF = 1k⍀9RF = RGRF = 499⍀87RF = 250⍀B6d – N5IAG4R3F = 150⍀2RF = 75⍀1R0F = 1k⍀ AND CF = 2.2pF0.1M1M10M100M1GFREQUENCY – HzTPC 10.Small Signal Frequency Response vs.Frequency and RF, Noninverting, VOUT = 50 mV p-p.See Test Circuit 1.15G = 21296B3d R–S = 49.9⍀ N0IAG–3–6RS = 100⍀–9–12RS = 249⍀–150.1M1M10M100M1GFREQUENCY – HzTPC 11.Small Signal Frequency Response vs.Frequency and RS, Noninverting, VOUT = 50 mV p-p.See Test Circuit 1.1009080Bd70 180– sNeIeA60135rGge PD O5090– OELS-N4045AEHPPO30020–4510–900–13510k100k1M10M100M1GFREQUENCY – HzTPC 12.Open-Loop Gain and Phase vs.Frequency, RG =100 Ω, RF = 1 kΩ, RO = 976 Ω,RD = 53.6 Ω, CC = 0pF. See Test Circuit 3.–7–

AD8021

6.4G = 26.2VS = ؎2.5VB6.0d – NIA؎5VG5.8؎12V5.65.41M10M100MFREQUENCY – HzTPC 13.0.1 dB Flatness vs. Frequency andSupply, VOUT = 1 V p-p, RL = 150 Ω, Noninverting.See Test Circuit 2.–20–30–40–50SECONDcBd–60 – NO–70ITRL = 100⍀R–80TOSRL = 1k⍀I–90D–100–110–120THIRD–1300.1M1M10M20MFREQUENCY – HzTPC 14.Second and Third Harmonic Distortionvs. Frequency and RL–30–40–50c–60Bd ––70THIRD NOIT–80VS = ؎2.5VSECONDRTO–90SID–100SECONDV = ؎5V–110S–120SECONDV12VTHIRDS = ؎–130100k1M10M20MFREQUENCY – HzTPC 15.Second and Third Harmonic Distortionvs. Frequency and VS–20–30–40ff–5012⌬f = 0.2MHzPm–60OUTBd976⍀ – –70TU53.6⍀50⍀OP–80–90–100–110–1209.59.710.010.310.5FREQUENCY – MHzTPC 16.Intermodulation Distortion vs. Frequency50m45Bd – TP40ECRET35VS = ؎5VNI REVS = ؎2.5VDRO30-DRIHT252005101520FREQUENCY – MHzTPC 17.Third-Order Intercept vs. Frequency andSupply Voltage–50–60–70cBSECONDd – N–80RL = 100⍀OITR–90THIRDTOSECONDSID–100RL = 1k⍀–110THIRD–120123456VOUT – V p-pTPC 18.Second and Third Harmonic Distortionvs. VOUT and RLREV. D

–8–

–50–60SECOND–70cBdfC = 5MHz – N–80OTHIRDITR–90TOSECONDSID–100fC = 1MHz–110THIRD–120123456VOUT – V p-pTPC 19.Second and Third Harmonic Distortionvs. VOUT and Fundamental Frequency (fC), G = +2–40–50fC = 5MHz–60cSECONDBd – N–70OITTHIRDR–80TOSISECONDD–90fC = 1MHz–100THIRD–110123456VOUT – V p-pTPC 20.Second and Third Harmonic Distortionvs. VOUT and Fundamental Frequency (fC), G = +10–70fC = 1MHzRL = 1k⍀–80cBd ––90 NOSECONDITRTO–100SI DTHIRD–110–12002004006008001000FEEDBACK RESISTANCE – ⍀TPC 21.Second and Third Harmonic Distortionvs. Feedback Resistor (RF)REV. DAD8021

3.5–3.13.4–3.2 VPOSITIVE OUTPUT V–– E3.3–3.3EAGLTAGLTO VO VT3.2–3.4TUUPPTTUUO3.1–3.5O EEVVIITIS3.0–3.6ATOGPEN2.9NEGATIVE OUTPUT–3.72.80400800120016002000–3.8LOAD – ⍀TPC 22.DC Output Voltage vs. Load. See TestCircuit 1.120VA100S = ؎12 m– TNE80RVS = ؎5.0RUC T60IUCVS = ؎2.5RICT-40 ROHS200–50–30–101030507090110TEMPERATURE – ؇CTPC 23.Short-Circuit Current to Ground vs.Temperature50G = 240R30L = 1k⍀, 150⍀20V10 m– TUOV–10–20–30–40–5004080120160200TIME – nsTPC 24.Small Signal Transient Response vs. RL,VO = 50 mV p-p. See Test Circuit 2, Noninverting.–9–

AD8021

VO = 4V p-p2.0G = 2RL = 1k⍀1.0 V– TUOVRL = 150⍀–1.0–2.004080120160200TIME – nsTPC 25.Large Signal Transient Response vs. RL.See Test Circuit 2, Noninverting.5 VO = 4V p-p4G = –13V2IN1SLTVO–1VOUT –2–3–4–5050100150200250TIME – ns TPC 26.Large Signal Transient Response. See Test Circuit 3, Inverting.CL = 50pFVO = 4V p-p2.0G = 21.0CL = 10pF, 0pF V– TUOV –1.0–2.004080120160200TIME – nsTPC 27.Large Signal Transient Response vs. CL.See Test Circuit 1.V2.0O = 2V p-pG = 21.0 V– TUOVVS = ؎2.5V –1.0VS = ؎5V–2.004080120160200TIME – nsTPC 28.Large Signal Transient Response vs. VS.See Test Circuit 1.VIN = ؎3VG = +2VVOUT, RL = 1k⍀VIN = 1V/DIVOUT = 2V/DIVRL = 150⍀VIN0100200300400500TIME – nsTPC 29.Overdrive Recovery vs. RL. See Test Circuit 2.G = 2NGILT+0.01%TES TUPT–0.01%UO25nsVERT = 0.2mV/DIVHOR = 5ns/DIVTPC 30.0.01% Settling Time, 2 V StepREV. D

–10–

100806040V␮PULSEWIDTH = 120ns –20 GNI0LTTE–20SPULSEWIDTH = 300␮s–40–605V–800V–100t1048121620242832TIME – ␮sTPC 31.Long-Term Settling, 0 V to 5 V, VS = ±12 V, G = +135040G = ؉13020Vm10 – TUOV–10 –20–30–40–5004080120160200TIME – ns TPC 32.Small Signal Transient Response, VO = 50 mV p-p.G = +1. See Test Circuit 1.100zH /Vn – ESIO10N EG LTAVO2.1nV/ Hz1101001k10k100k1M10MFREQUENCY – HzTPC 33.Input Voltage Noise vs. FrequencyREV. D–11–

AD8021

100

zH /Ap – ESION TN10

ERRUC TUPNI110

1001k

10k100k

1M10M

FREQUENCY – Hz

TPC 34.Input Current Noise vs. Frequency0.480.44Vm –0.40 TESFF0.36 OEAGLT0.32VO0.280.24–50–250255075100TEMPERATURE – ؇CTPC 35.VOS vs. Temperature8.48.0A␮ – TN7.6ERRUC7.2 SAIB TU6.8PNI6.46.0–50–250255075100TEMPERATURE – ؇CTPC 36.Input Bias Current vs. Temperature AD8021

–20–30–40–50Bd–60 – RR–70MC–80–90–100–110–120

10k

100k

1M

10M

100M

FREQUENCY – Hz

TPC 37.CMRR vs. Frequency. See Test Circuit 4.30010030 ⍀– 10ECN3DAEP1MI TU0.3PTU0.1O0.030.010.00310k100k1M10M100M1GFREQUENCY – HzTPC 38.Output Impedance vs. Frequency, ChipEnabled. See Test Circuit 5.4VDISABLE2VVOUTPUT2VtEN = 45ns1VtDIS = 50ns0100200300400500TIME – nsTPC 39.Enable (tEN)/Disable (tDIS) Time vs. VOUT.See Test Circuit 6.0–10–20Bd – –30NOI–40ATLOS–50I DEL–60BAS–70ID–80–90–1000.1M1M10M100M1GFREQUENCY – HzTPC 40.Input to Output Isolation, Chip Disabled.See Test Circuit 7.300k100k30k ⍀– 10kECN3kDAEP1kMI TU300PTU100O3010310k100k1M10M100M1GFREQUENCY – HzTPC 41.Output Impedance vs. Frequency, ChipDisabled. See Test Circuit 8.0–10–20–PSRR–30B–40d –V R–50S = ؎2.5V+PSRRRSP–60VS = ؎12V–70–80VS = ؎5V–90–10010k100k1M10M100M500MFREQUENCY – HzTPC 42.PSRR vs. Frequency and Supply Voltage.See Test Circuits 9 and 10.REV. D

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AD8021

8.58.0SUPPLY CURRENT – mA7.57.06.56.05.5–50–2502550TEMPERATURE – ؇C75100TPC 43.Quiescent Supply Current vs. TemperatureTest Circuits50⍀+VSRO5RIN49.9⍀CC–VSRGRFRD50⍀ CABLE50⍀ CABLE50⍀HP8753DNETWORKANALYZER50⍀AD8021499⍀499⍀CC–VS55.6⍀499⍀7pF499⍀+VS5RS49.9⍀

CFTest Circuit 1.Noninverting GainFETPROBETest Circuit 4.CMRRAD8021+VS100⍀HP8753DNETWORKANALYZER5CC7pF–VSRG499⍀RF499⍀50⍀50⍀ CABLE50⍀RIN49.9⍀RS+VS5CCRFCFCLRL–VSRGTest Circuit 2.Noninverting Gain with FET ProbeTest Circuit 5.Output Impedance, Chip EnabledAD8021+VSRO49.9⍀CC50⍀ CABLE50⍀RIN49.9⍀RG–VSRF5RD50⍀ CABLE49.9⍀1.0V49.9⍀1+VS976⍀553.6⍀LOGIC REF8DISABLE4V49.9⍀–VS499⍀499⍀CC7pFTest Circuit 3.Inverting GainTest Circuit 6.Enable/DisableREV. D–13–

AD8021

HP8753DNETWORKANALYZER50⍀50⍀50⍀ CABLE+VS49.9⍀AD8021FET49.9⍀1LOGIC REFPROBE8DISABLE51k⍀–VCSC7pF499⍀499⍀Test Circuit 7.Input to Output Isolation, Chip DisabledAD8021HP8753D18+VSNETWORKANALYZER100⍀550⍀CC7pF–VSTest Circuit 8.Output Impedance, Chip Disabled–14–

BIASBNCHP8753DNETWORKANALYZER50⍀+V50⍀S50⍀ CABLE+V49.9⍀, 5WS976⍀249⍀553.6⍀–VCCS7pF499⍀499⍀Test Circuit 9.Positive PSRRBIASBNCHP8753DNETWORKANALYZER50⍀–V50⍀S

50⍀ CABLE

+VS976⍀249⍀553.6⍀–VCSC7pF49.9⍀5W499⍀499⍀Test Circuit 10.Negative PSRRREV. D

AD8021

APPLICATIONSCOMPENSATION CAPACITANCE – pFThe typical voltage feedback op amp is frequency stabilized witha fixed internal capacitor, CINTERNAL, using dominant pole compen-sation. To a first-order approximation, voltage feedback opampshave a fixed gain bandwidth product. For example, if its –3dBbandwidth for G = +1 is 200 MHz, at a gain of G = +10 itsbandwidth will be only about 20 MHz. The AD8021 is a voltagefeedback op amp with a minimal CINTERNAL of about 1.5pF. Byadding an external compensation capacitor, CC, the user cancircumvent the fixed gain bandwidth limitation of other voltagefeedback op amps.Unlike the typical op amp with fixed compensation, the AD8021allows the user to1.Maximize the amplifier bandwidth for closed-loop gainsbetween 1 and 10, avoiding the usual loss of bandwidthand slew rate.bandwidth is degraded to about 20 MHz and the phase marginincreases to 90° (Arrow B). However, by reducing CC to zero,the bandwidth and phase margin return to about 200 MHz and60° (Arrow C), respectively. In addition, the slew rate is dra-matically increased, as it roughly varies with the inverse of CC.10987632101234567NOISE GAIN – V/V10112. Optimize the trade-off between bandwidth and phasemargin for a particular application.3. Match bandwidth in gain blocks with different noise gains,such as when designing differential amplifiers (as shown inFigure 10).110100908680706050403020100–101k10k100k(B)(A)1M10M100MFREQUENCY – Hz1G10G(C)CC = 10pF18013590CC = 0pF(B)(A)(C)45Figure 4.Suggested Compensation Capacitancevs. Gain for Maintaining 1 dB PeakingOPEN-LOOP GAIN – dBPHASE – Degrees0Table I and Figure 4 provide recommended values of compensa-tion capacitance at various gains and the corresponding slew rate,bandwidth, and noise. Note that the value of the compensationcapacitor depends on the circuit noise gain, not the voltage gain.As shown in Figure 5, the noise gain, GN, of an op amp gain blockis equal to its noninverting voltage gain, regardless of whetheritis actually used for inverting or noninverting gain. Thus,NoninvertingGN=RF/RG+1 InvertingGN=RF/RG+1RG200⍀65RF800⍀3+–VSRG200⍀CCOMPINVERTING2–RF800⍀1RS3+Figure 3.Simplified Diagram of Open-Loop Gainand Phase ResponseAD80212––VSCCOMPG = GN = 5AD802156Figure 3 is the AD8021 gain and phase plot that has been sim-plified for instructional purposes. If the desired closed-loop gainis G = +1 and CC = 10 pF is chosen, Arrow A of the figureshows that the bandwidth is about 200 MHz and the phasemargin is about 60°. If the gain is changed to G = +10 and CCis fixed at 10 pF, then (as expected for a typical op amp) theG = –4GN = 5NONINVERTINGFigure 5.The Noise Gain of Both Is 5Table I.Recommended Component Values. See Test Circuit 2. CF = CL = 0, RL = 1 k⍀, RIN = 49.9 ⍀Noise Gain(NoninvertingGain)1251020RS(⍀)79.949.949.949.9RF(⍀)7991 k1 k1 kRG(⍀)NA49924911052.3CCOMP(pF)107200SlewRate(V/␮s)120150300420200–3 dBSS BW(MHz)49020518515042Output Noise(AD8021 Only)(nV/√Hz)2.14.310.721.242.2Output Noise(AD8021 with Resistors)(nV/√Hz)2.88.215.527.952.7100REV. D

49.91 k10034–15–

6211.12.1AD8021

With the AD8021, a variety of trade-offs can be made to fine-tuneits dynamic performance. Sometimes more bandwidth or slewrate is needed at a particular gain. Reducing the compensationcapacitance, as illustrated in TPC 3, will increase the bandwidthand peaking due to a decrease in phase margin. On the other hand,if more stability is needed, increasing the compensation cap willdecrease the bandwidth while increasing the phase margin.As with all high speed amplifiers, parasitic capacitance and induc-tance around the amplifier can affect its dynamic response.Often, the input capacitance (due to the op amp itself, as wellas the PC board) could have a significant effect. The feedbackresistance, together with the input capacitance, may contribute toa loss of phase margin, thereby affecting the high frequency response,as shown in TPC 10. Furthermore, a capacitor (CF) in parallelwith the feedback resistor can compensate for this phase loss.Additionally, any resistance in series with the source will createa pole with the input capacitance (as well as dampen high fre-quency resonance due to package and board inductance andcapacitance), the effect of which is shown in TPC 11.It must also be noted that increasing resistor values will increasethe overall noise of the amplifier, and that reducing the feedbackresistor value will increase the load on the output stage, thusincreasing distortion (TPC 18).Using the Disable Featurethis high impedance with a current gain of 5,000, so that theAD8021 can maintain a high open-loop gain even when drivingheavy loads.Two internal diode clamps across the inputs (Pins 2 and 3) protectthe input transistors from large voltages that could otherwise causeemitter-base breakdown, which would result in degradation ofoffset voltage and input bias current.+VS+INOUTPUTCINTERNAL1.5pF–IN–VSCCOMPCCFigure 6.Simplified SchematicPCB LAYOUT CONSIDERATIONSWhen Pin 8 (DISABLE) is approximately 2 V or more higher thanPin 1 (LOGIC REFERENCE), the part is enabled. When Pin8is brought down to within about 1.5 V of Pin 1, the part is dis-abled. See the Specification tables for exact disable and enablevoltage levels. If the disable feature is not going to be used, Pin8can be tied to VS or a logic high source, and Pin 1 can be tied toground or logic low. Alternatively, if Pin 1 and Pin 8 are notconnected, the part will be in an enabled state.THEORY OF OPERATIONThe AD8021 is fabricated on the second generation of AnalogDevices’ proprietary High Voltage eXtra-Fast ComplementaryBipolar (XFCB) process, which enables the construction of PNPand NPN transistors with similar fTs in the 3 GHz region. Thetransistors are dielectrically isolated from the substrate (and eachother), eliminating the parasitic and latch-up problems causedby junction isolation. It also reduces nonlinear capacitance(asource of distortion) and allows a higher transistor fT for agiven quiescent current. The supply current is trimmed, whichresults in less part-to-part variation of bandwidth, slew rate,distortion, and settling time.As shown in Figure 6, the AD8021 input stage consists of an NPNdifferential pair in which each transistor operates at 0.8mA collec-tor current. This allows the input devices a high transconductance;thus, the AD8021 has a low input noise of 2.1 nV/√Hz @ 50 kHz.The input stage drives a folded cascode that consists of a pair ofPNP transistors. The folded cascode and current mirror providea differential to single-ended conversion of signal current. Thiscurrent then drives the high impedance node (Pin 5), where theCC external capacitor is connected. The output stage preservesAs with all high speed op amps, achieving optimum performancefrom the AD8021 requires careful attention to PC board layout.Particular care must be exercised to minimize lead lengthsbetween the ground leads of the bypass capacitors and betweenthe compensation capacitor and the negative supply. Otherwise,lead inductance can influence the frequency response and evencause high frequency oscillations. Use of a multilayer printedcircuit board, with an internal ground plane, will reduce groundnoise and enable a compact component arrangement.Due to the relatively high impedance of Pin 5 and low values ofthe compensation capacitor, a guard ring is recommended. Theguard ring is simply a PC trace that encircles Pin 5 and isconnected to the output, Pin 6, which is at the same potential asPin5. This serves two functions. It shields Pin 5 from any localcircuit noise generated by surrounding circuitry. It also mini-mizes stray capacitance, which would tend to otherwise reducethe bandwidth. An example of a guard ring layout may be seenin Figure7.Also shown in Figure 7, the compensation capacitor is locatedimmediately adjacent to the edge of the AD8021 package, spanningPin 4 and Pin 5. This capacitor must be a high quality surface-mount COG or NPO ceramic. The use of leaded capacitors is notrecommended. The high frequency bypass capacitor(s) shouldbe located immediately adjacent to the supplies, Pins4 and7.To achieve the shortest possible lead length at the invertinginput, the feedback resistor RF is located beneath the board andjust spans the distance from the output, Pin 6, to inverting inputPin 2. The return node of resistor RG should be situated asclosely as possible to the return node of the negative supplybypass capacitor connected to Pin 4.–16–

REV. D

AD8021

(TOP VIEW)LOGIC REFERENCE12348+VS765VOUTGROUNDPLANE–VSMETALBYPASSCAPACITORCOMPENSATIONCAPACITORGROUNDPLANE50⍀CCOMPDISABLEBYPASSCAPACITOR Table II.Summary of ADC Driver Performance, fC = 65 kHz, VOUT = 10 V p-p–IN+INParameterSecond Harmonic DistortionThird Harmonic DistortionTHDSFDR+12V50⍀3+50⍀Measurement–101.3–109.5–100.0100.3UnitdBdBdBdB5V65CCRF750⍀570kSPSADCOPTIONAL CFINLOINHIAD80212–Figure 7.Recommended Location of CriticalComponents and Guard RingDRIVING 16-BIT ADCS–12VRG82.5⍀Low noise and adjustable compensation make the AD8021especially suitable as a buffer/driver for high resolution analog-to-digital converters.As seen in TPC 15, the harmonic distortion is better than 90dB atfrequencies between 100 kHz and 1 MHz. This is a real advantagefor complex waveforms that contain high frequency information,as the phase and gain integrity of the sampled waveform can bepreserved throughout the conversion process. The increase inloop gain results in improved output regulation and lower noisewhen the converter input changes state during a sample. Thisadvantage is particularly apparent when using 16-bit high resolu-tion ADCs with high sampling rates.Figure 8 shows a typical ADC driver configuration. The AD8021is in an inverting gain of –7.5, fC is 65 kHz, and its output voltageis 10 V p-p. The results are listed in Table II.+12V3590⍀2RG200⍀50⍀65kHz5V+Figure 9.Noninverting ADC Driver, Gain = 10, fC = 100kHzTable III.Summary of ADC Driver Performance,fC = 100 kHz, VOUT = 20 V p-pParameterSecond Harmonic DistortionThird Harmonic DistortionTHDSFDRMeasurement–92.6–86.4–84.45.4UnitdBdBdBdBFigure 9 shows another ADC driver connection. The circuit wastested with a noninverting gain of 10.1 and an output voltage ofapproximately 20 V p-p for optimum resolution and noise per-formance. No filtering was used. An FFT was performed usingAnalog Devices’ evaluation software for the AD7665 16-bitconverter. The results are listed in Table III.DIFFERENTIAL DRIVERAD8021–CC65INHI–12VRF1.5k⍀56pFINLO570kSPS16 BITS10pFAD7665The AD8021 is uniquely suited as a low noise differential driverfor many ADCs, balanced lines, and other applications requiringdifferential drive. If pairs of internally compensated op amps areconfigured as inverter and follower, the noise gain of the inverterwill be higher than that of the follower section, resulting in animbalance in the frequency response (see Figure 11).A better solution takes advantage of the external compensationfeature of the AD8021. By reducing the CCOMP value of the inverter,its bandwidth may be increased to match that of the follower,avoiding compromises in gain bandwidth and phase delay. Theinverting and noninverting bandwidths can be closely matchedusing the compensation feature, thus minimizing distortion.Figure 8.Inverting ADC Driver, Gain = –7.5, fC = 65 kHzREV. D–17–

16 BITSAD7665AD8021

Figure 10 illustrates an inverter-follower driver circuit operatingat a gain of 2, using individually compensated AD8021s. Thevalues of feedback and load resistors were selected to provide atotal load of less than 1 kΩ, and the equivalent resistances seenat each op amp’s inputs were matched to minimize offset volt-age and drift. Figure 12 is a plot of the resulting ac responses ofUSING THE AD8021 IN ACTIVE FILTERSThe low noise and high gain bandwidth of the AD8021 make it anexcellent choice in active filter circuits. Most active filter litera-ture provides resistor and capacitor values for various filters butneglects the effect of the op amp’s finite bandwidth on filterperformance; ideal filter response with infinite loop gain is implied.driver halves.V249⍀IN3+G = +2AD80219.9⍀2–5–VS7pF499⍀499⍀VOUT11k⍀232⍀3+G = –2AD80216V5OUT22–1k⍀–VS5pF332⍀6⍀Figure 10.Differential Amplifier12963B0G = –2d –G = +2 N–3IAG–6–9–12–15–18100k1M10M100M1GFREQUENCY – HzFigure 11.AC Response of Two IdenticallyCompensated High Speed Op Amps Configuredfor Gains of +2 and –212 963G = ؎2B0d – N–3IAG–6–9–12–15–18100k1M10M100M1GFREQUENCY – HzFigure12.AC Response of Two DissimilarlyCompensated AD8021 OpAmps (Figure11) Configuredfor Gains of +2 and –2. Note the Close Gain Match.Unfortunately, real filters do not behave in this manner. Instead,they exhibit finite limits of attenuation, depending on the gainbandwidth of the active device. Good low-pass filter performancerequires an op amp with high gain bandwidth for attenuation athigh frequencies, and low noise and high dc gain for low frequency,pass-band performance.Figure 13 shows the schematic of a 2-pole, low-pass active filter,and Table IV lists typical component values for filters having aBessel-type response with gains of 2 and 5. Figure 14 is a network analyzer plot of this filter’s performance.C1+VSAD8021VR1R2IN36C225VOUTCC–VSRGRFFigure 13.Schematic of a Second-Order Low-PassActive FilterTable IV. Typical Component Values for Second-OrderLow-Pass Filter of Figure 13GainR1 (⍀)R2(⍀)RF (⍀)RS (⍀)C1C2CC271.5219949910 nF10 nF7 pF4.236590.936510 nF10 nF2 pF50403020G = 5B10d – N0IAGG = 2–10–20–30–40–501k10k100k1M10MFREQUENCY – HzFigure 14.Frequency Response of the Filter Circuitof Figure 13 for Two Different GainsREV. D

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Driving Capacitive LoadsWhen the AD8021 drives a capacitive load, the high frequencyresponse may show excessive peaking before it rolls off. Twotechniques can be used to improve stability at high frequency andreduce peaking. The first technique is to increase the compensa-tion capacitor, CC, which reduces the peaking while maintaininggain flatness at low frequencies. The second technique is to add aresistor, RSNUB, in series between the output pin of the AD8021and the capacitive load, CL. Figure 15 shows the response of theAD8021 when both CC and RSNUB are used to reduce peaking.For a given CL, Figure 16 can be used to determine the value ofRSNUB that maintains 2 dB of peaking in the frequency response.Note, however, that using RSNUB attenuates the low frequencyoutput by a factor of RLOAD/(RSNUB + RLOAD).18+VSFET16PROBE5RSNUBCC = 7pF;1449.9⍀RSNUB = 049.9⍀633pFRL12–VS1k⍀CC = 8pF;CCRSNUB = 0B10d – N8499⍀499⍀IAG2C0RC = 8pF;SNUB = 17.4⍀0.11.0101001000FREQUENCY – MHzFigure 15.Peaking vs. RSNUB and CC for CL = 33 pFREV. D–19–

AD8021

20181614 ⍀12– BU10NRS820051015202530304550CAPACITIVE LOAD – pFFigure 16.Relationship of RSNUB vs. CL for 2 dBPeaking at a Gain of +2AD8021

OUTLINE DIMENSIONS8-Lead Standard Small Outline Package [SOIC](R-8)Dimensions shown in millimeters and (inches)5.00 (0.1968)4.80 (0.10)4.00 (0.1574)856.20 (0.2440)3.80 (0.1497)145.80 (0.2284)1.27 (0.0500)0.50 (0.0196)BSC1.75 (0.0688)0.25 (0.0099)؋ 45؇0.25 (0.0098)1.35 (0.0532)0.10 (0.0040)0.51 (0.0201)8؇COPLANARITY0.10SEATING0.31 (0.0122)0.25 (0.0098)0؇1.27 (0.0500)PLANE0.17 (0.0067)0.40 (0.0157)COMPLIANT TO JEDEC STANDARDS MS-012AACONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FORREFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN8-Lead Mini Small Outline Package [MSOP](RM-8)Dimensions shown in millimeters3.00BSC853.004.90BSCBSC14PIN 10.65 BSC0.151.10 MAX0.000.800.380.238؇0.220.080؇0.600.40COPLANARITYSEATING0.10PLANECOMPLIANT TO JEDEC STANDARDS MO-187AARevision HistoryLocationPage10/03—Data Sheet changed from REV. C to REV. D.Edits to SPECIFICATIONS heading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57/03—Data Sheet changed from REV. B to REV. C.Deleted all references to evaluation board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .UniversalReplaced Figure 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202/03—Data Sheet changed from REV. A to REV. B.Edits to Evaluation Board Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20Edits to Figure 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206/02—Data Sheet changed from REV. 0 to REV. A.Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2–20–

REV. D

)D(30/01–0–88810C