专利名称：Gate self aligned low noise JFET发明人：Xiaoju Wu,Fan-Chi Frank Hou,Pinghai Hao申请号：US11715748申请日：20070308公开号：US07745274B2公开日：20100629
专利附图：
摘要：The disclosure herein pertains to fashioning a low noise junction field effecttransistor (JFET) where transistor gate materials are utilized in forming and electricallyisolating active areas of a the JFET. More particularly, active regions are self aligned withpatterned gate electrode material and sidewall spacers which facilitate desirably locating
the active regions in a semiconductor substrate. This mitigates the need for additionalmaterials in the substrate to isolate the active regions from one another, where suchadditional materials can introduce noise into the JFET. This also allows a layer of gatedielectric material to remain over the surface of the substrate, where the layer of gatedielectric material provides a substantially uniform interface at the surface of thesubstrate that facilitates uninhibited current flow between the active regions, and thuspromotes desired device operation.
申请人：Xiaoju Wu,Fan-Chi Frank Hou,Pinghai Hao
地址：Irving TX US,McKinney TX US,Plano TX US
国籍：US,US,US
代理人：Warren L. Franz,Wade J. Brady, III,Frederick J. Telecky, Jr.
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