Generating hardware accelerators and processor off

专利名称：Generating hardware accelerators and

processor offloads

发明人：Navendu Sinha,William Charles Jordan,Bryon

Irwin Moyer,Stephen John JosephFricke,Roberto Attias,Akash RenukadasDeshpande,Vineet Gupta,Shobhit Sonakiya

申请号：US11607452申请日：20061201公开号：US08127113B1公开日：20120228

专利附图：

摘要：System and method for generating hardware accelerators and processoroffloads. System for hardware acceleration. System and method for implementing anasynchronous offload. Method of automatically creating a hardware accelerator.Computerized method for automatically creating a test harness for a hardware

accelerator from a software program. System and method for interconnecting hardwareaccelerators and processors. System and method for interconnecting a processor and ahardware accelerator. Computer implemented method of generating a hardware circuitlogic block design for a hardware accelerator automatically from software. Computerprogram and computer program product stored on tangible media implementing themethods and procedures of the invention.

申请人：Navendu Sinha,William Charles Jordan,Bryon Irwin Moyer,Stephen JohnJoseph Fricke,Roberto Attias,Akash Renukadas Deshpande,Vineet Gupta,Shobhit Sonakiya

地址：Milpitas CA US,Tres Pinos CA US,Sunnyvale CA US,Felton CA US,Alameda CAUS,San Jose CA US,San Jose CA US,Fremont CA US

国籍：US,US,US,US,US,US,US,US

代理机构：Fenwick & West LLP

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