SC16C2550_en-03

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SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOsandinfrared(IrDA) encoder/decoder

Rev. 03 — 19 June 2003

Product data

1.Description

TheSC16C2550 is a 2 channel Universal Asynchronous Receiver and Transmitter(UART) used for serial data communications. Its principal function is to convert

parallel data into serial data and vice versa. The UART can handle serial data ratesup to 5Mbits/s.

The SC16C2550 is pin compatible with the ST16C2550. It will power-up to be

functionally equivalent to the 16C2450. The SC16C2550 provides enhanced UARTfunctionswith16-byteFIFOs,modemcontrolinterface,DMAmodedatatransfer.TheDMA mode data transfer is controlled by the FIFO trigger levels and the TXRDY andRXRDYsignals.On-boardstatusregistersprovidetheuserwitherrorindicationsandoperationalstatus.Systeminterruptsandmodemcontrolfeaturesmaybetailoredbysoftware to meet speciﬁc user requirements. An internal loop-back capability allowson-boarddiagnostics.Independentprogrammablebaudrategeneratorsareprovidedto select transmit and receive baud rates.

TheSC16C2550 operates at 5V, 3.3V and 2.5V and the Industrial temperaturerange, and is available in plastic PLCC44, LQFP48 and DIP40 packages.

2.Features

sssssssssssssss

2 channel UART

5V, 3.3V and 2.5V operationIndustrial temperature range

Pin and functionally compatible to 16C2450 and software compatible withINS8250, SC16C550

Up to 5Mbits/s data rate at 5V and 3.3V, and 3Mbits/s at 2.5V

16byte transmit FIFO to reduce the bandwidth requirement of the external CPU16byte receive FIFO with error ﬂags to reduce the bandwidth requirement of theexternal CPU

Independent transmit and receive UART control

Four selectable Receive FIFO interrupt trigger levelsAutomatic software/hardware ﬂow controlProgrammable Xon/Xoff characters

Software selectable Baud Rate GeneratorSleep mode

Standard asynchronous error and framing bits (Start, Stop, and Parity OverrunBreak)

Transmit, Receive, Line Status, and Data Set interrupts independently controlled

Philips Semiconductors

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs andIrDA

encoder/decoder

sFully programmable character formatting:

x5-, 6-, 7-, or 8-bit characters

xEven-, Odd-, or No-Parity formatsx1-, 11⁄2-, or 2-stop bit

xBaud generation (DC to 1.5Mbit/s)sFalse start-bit detection

sComplete status reporting capabilities

s3-State output TTL drive capabilities for bi-directional data bus and control bussLine Break generation and detectionsInternal diagnostic capabilities:

xLoop-back controls for communications link fault isolationsPrioritized interrupt system controls

sModem control functions (CTS,RTS,DSR,DTR,RI,DCD).3.Ordering information

Table 1:

Ordering information

PackageNameSC16C2550IN40SC16C2550IA44SC16C2550IB48

DIP40PLCC44LQFP48

Descriptionplastic dual in-line package; 40 leads (600mil)plastic leaded chip carrier; 44 leads

plastic low proﬁle quad ﬂat package; 48 leads; body 7×7×1.4mm

VersionSOT129-1SOT187-2SOT313-2

Product dataRev. 03 — 19 June 20032 of 46

Philips Semiconductors

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs andIrDA

encoder/decoder

4.Block diagram

SC16C2550TRANSMITFIFOREGISTERD0–D7IORIOWRESETDATA BUSANDCONTROL LOGICTRANSMITSHIFTREGISTERTXA, TXBINTERCONNECT BUS LINESANDCONTROL SIGNALSRECEIVEFIFOREGISTERRECEIVESHIFTREGISTERRXA, RXBA0–A2CSACSBREGISTERSELECTLOGICDTRA, DTRBRTSA, RTSBOP2A, OP2BMODEMCONTROLLOGICINTA, INTBTXRDYA, TXRDYBRXRDYA, RXRDYBINTERRUPTCONTROLLOGICCLOCK ANDBAUD RATEGENERATORCTSA, CTSBRIA, RIBCDA, CDBDSRA, DSRB002aaa119XTAL1XTAL2Fig 1.SC16C2550 block diagram.939775011621© Koninklijke Philips Electronics N.V. 2003. All rights reserved.

Product dataRev. 03 — 19 June 20033 of 46

Philips Semiconductors

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs andIrDA

encoder/decoder

5.Pinning information

5.1Pinning

D01D12D23D34D45D56D67D7840VCC39RIA38CDA37DSRA36CTSA35RESET34DTRB33DTRARXA10TXA11TXB12OP2B13CSA14CSB15XTAL116XTAL217IOW18CDB19GND20SC16C2550IN40RXB932RTSA31OP2A30INTA29INTB28A027A126A225CTSB24RTSB23RIB22DSRB21IOR002aaa105Fig 2.DIP40 pin conﬁguration.939775011621© Koninklijke Philips Electronics N.V. 2003. All rights reserved.

Product dataRev. 03 — 19 June 20034 of 46

Philips Semiconductors

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs andIrDA

encoder/decoder

1TXRDYA41DSRAD5D6D7740CTSA42CDA44VCC43RIA6D45D34D23D12D039RESET38DTRB37DTRA36RTSA35OP2ARXB10RXA11TXRDYB12TXA13TXB14OP2B15CSA16CSB17SC16C2550IA4434RXRDYA33INTA32INTB31A030A129A2XTAL118XTAL219IOW20CDB21GND22RXRDYB23IOR24DSRB25RIB26RTSB27CTSB28002aaa103Fig 3.PLCC44 pin conﬁguration.939775011621© Koninklijke Philips Electronics N.V. 2003. All rights reserved.

Product dataRev. 03 — 19 June 20035 of 46

Philips Semiconductors

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs andIrDA

encoder/decoder

43TXRDYA39DSRA38CTSA40CDAD5D6D7RXBRXATXRDYBTXATXBOP2B12345637N.C.42VCC41RIA48D447D346D245D144D036RESET35DTRB34DTRA33RTSA32OP2A31RXRDYASC16C2550IB48730INTA29INTB28A027A126A225N.C.CSA10CSB11N.C.12XTAL113XTAL214IOW15CDB16GND17RXRDYB18IOR19DSRB20RIB21RTSB22CTSB23N.C.24002aaa104Fig 4.LQFP48 pin conﬁguration.5.2Pin description

Table 2:SymbolA0A1A2282726313029Pin description

PinDIP40PLCC44LQFP4828272610, 11IIIIAddress 0 select bit. Internal register address selection.Address 1 select bit. Internal register address selection.Address 2 select bit. Internal register address selection.ChipSelectA,B(Active-LOW).Thisfunctionisassociatedwithindividualchannels, A through B. These pins enable data transfers between the userCPU and the SC16C2550 for the channel(s) addressed. Individual UARTsections(A,B)areaddressedbyprovidingalogic0ontherespectiveCSA,CSB pin.Data bus (bi-directional). These pins are the 8-bit, 3-State data bus fortransferring information to or from the controlling CPU. D0 is the leastsigniﬁcant bit and the ﬁrst data bit in a transmit or receive serial datastream.Signal and power ground.TypeDescriptionCSA,CSB14, 1516, 17D0-D71-82-944-48,1-3I/OGND202217I939775011621© Koninklijke Philips Electronics N.V. 2003. All rights reserved.

Product dataRev. 03 — 19 June 20036 of 46

Philips Semiconductors

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs andIrDA

encoder/decoder

Table 2:SymbolINTA,INTBPin description…continuedPinDIP40PLCC44LQFP4830, 2933, 3230, 29OInterruptA,B(3-State).Thisfunctionisassociatedwithindividualchannelinterrupts, INTA, INTB. INTA, INTB are enabled when MCR bit3 is set to alogic1, interrupts are enabled in the interrupt enable register (IER), and isactive when an interrupt condition exists. Interrupt conditions include:receiver errors, available receiver buffer data, transmit buffer empty, orwhen a modem status ﬂag is detected.Readstrobe(Active-LOWstrobe).Alogic0transitiononthispinwillloadthe contents of an internal register deﬁned by address bits A0-A2 onto theSC16C2550 data bus (D0-D7) for access by external CPU.Write strobe (Active-LOW strobe). A logic0 transition on this pin willtransfer the contents of the data bus (D0-D7) from the external CPU to aninternal register that is deﬁned by address bits A0-A2.Output 2 (user-deﬁned). This function is associated with individualchannels, A through B. The state at these pin(s) are deﬁned by the userandthroughMCRregisterbit3.INTA,INTBaresettotheactivemodeandOP2 to logic 0 when MCR[3] is set to a logic1. INTA, INTB are set to the3-State mode andOP2 to a logic 1 when MCR[3] is set to a logic0. Seebit3, Modem Control Register (MCR[3]). Since these bits control both theINTA, INTB operation andOP2 outputs, only one function should be usedat one time, INT orOP2.Reset (Active-HIGH). A logic 1 on this pin will reset the internal registersandalltheoutputs.TheUARTtransmitteroutputandthereceiverinputwillbe disabled during reset time. (SeeSection 7.11 “SC16C2550 externalreset condition” for initialization details.)Receive Ready A, B (Active-LOW). This function is associated withPLCC44 and LQFP48 packages only. This function provides theRXFIFO/RHR status for individual receive channels (A-B).RXRDYn isprimarilyintendedformonitoringDMAmode1transfersforthereceivedataFIFOs. A logic0 indicates there is a receive data to read/upload, i.e.,receive ready status with one or more RX characters available in theFIFO/RHR. This pin is a logic1 when the FIFO/RHR is empty or when theprogrammed trigger level has not been reached. This signal can also beused for single mode transfers (DMA mode 0).Transmit Ready A, B (Active-LOW). This function is associated withPLCC44 and LQFP48 packages only. These outputs provide theTXFIFO/THR status for individual transmit channels (A-B).TXRDYn isprimarily intended for monitoring DMA mode1 transfers for the transmitdataFIFOs.Anindividualchannel’sTXRDYA,TXRDYBbufferreadystatusis indicated by logic0, i.e., at lease one location is empty and available inthe FIFO or THR. This pin goes to a logic1 (DMA mode1) when there arenomoreemptylocationsintheFIFOorTHR.Thissignalcanalsobeusedfor single mode transfers (DMA mode0).Power supply input.Crystal or external clock input. Functions as a crystal input or as anexternal clock input. A crystal can be connected between this pin andXTAL2 to form an internal oscillator circuit. This conﬁguration requires anexternal 1MΩ resistor between the XTAL1 and XTAL2 pins. Alternatively,anexternalclockcanbeconnectedtothispintoprovidecustomdatarates.(SeeSection 6.8 “Programmable baud rate generator”.) SeeFigure5.© Koninklijke Philips Electronics N.V. 2003. All rights reserved.

TypeDescriptionIOR212419IIOW182015IOP2A,OP2B31, 1335, 1532, 9ORESET353936IRXRDYA,RXRDYB-34, 2331, 18OTXRDYA,TXRDYB-1, 1243, 6OVCCXTAL14014184213II939775011621

Product dataRev. 03 — 19 June 20037 of 46

Philips Semiconductors

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs andIrDA

encoder/decoder

Table 2:SymbolXTAL2Pin description…continuedPinDIP40PLCC44LQFP48171914OOutput of the crystal oscillator or buffered clock. (See also XTAL1.)Crystal oscillator output or buffered clock output. Should be left open if anexternal clock is connected to XTAL1. For extended frequency operation,this pin should be tied to VCC via a 2kΩ resistor.Carrier Detect (Active-LOW). These inputs are associated with individualUART channels A through B. A logic0 on this pin indicates that a carrierhas been detected by the modem for that channel.Clear to Send (Active-LOW). These inputs are associated with individualUART channels, A through B. A logic0 on theCTS pin indicates themodem or data set is ready to accept transmit data from the SC16C2550.Status can be tested by reading MSR[4]. This pin has no effect on theUART’s transmit or receive operation.Data Set Ready (Active-LOW). These inputs are associated withindividual UART channels, A through B. A logic0 on this pin indicates themodem or data set is powered-on and is ready for data exchange with theUART. This pin has no effect on the UART’s transmit or receive operation.Data Terminal REady (Active-LOW). These outputs are associated withindividual UART channels, A through B. A logic0 on this pin indicates thatthe SC16C2550 is powered-on and ready. This pin can be controlled viathe modem control register. Writing a logic1 to MCR[0] will set theDTRoutputtologic0,enablingthemodem.Thispinwillbealogic1afterwritinga logic0 to MCR[0], or after a reset. This pin has no effect on the UART’stransmit or receive operation.RingIndicator(Active-LOW).TheseinputsareassociatedwithindividualUARTchannels,AthroughB.Alogic0onthispinindicatesthemodemhasreceivedaringingsignalfromthetelephoneline.Alogic1transitiononthisinput pin will generate an interrupt.Request to Send (Active-LOW). These outputs are associated withindividual UART channels, A through B. A logic0 on theRTS pin indicatesthe transmitter has data ready and waiting to send. Writing a logic1 in themodem control register MCR[1] will set this pin to a logic0, indicating datais available. After a reset this pin will be set to a logic 1. This pin has noeffect on the UART’s transmit or receive operation.Receive data A, B. These inputs are associated with individual serialchannel data to the SC16C2550 receive input circuits, A-B. The RX signalwill be a logic1 during reset, idle (no data), or when the transmitter isdisabled.Duringthelocalloop-backmode,theRXinputpinisdisabledandTX data is connected to the UART RX input, internally.Transmit data A, B. These outputs are associated with individual serialtransmitchanneldatafromtheSC16C2550.TheTXsignalwillbealogic1during reset, idle (no data), or when the transmitter is disabled. During thelocal loop-back mode, the TX output pin is disabled and TX data isinternally connected to the UART RX input.TypeDescriptionCDA,CDBCTSA,CTSB38, 1942, 2140, 16I36, 20, 2838, 23IDSRA,DSRB37, 2241, 2539, 20IDTRA,DTRB33, 3437, 3834, 35ORIA,RIB39, 2343, 21, 21IRTSA,RTSB32, 2436, 2733, 22ORXA,RXB10, 911, 105, 4ITXA, TXB11, 1213, 147, 8O939775011621© Koninklijke Philips Electronics N.V. 2003. All rights reserved.

Product dataRev. 03 — 19 June 20038 of 46

Philips Semiconductors

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs andIrDA

encoder/decoder

6.Functional description

TheSC16C2550 provides serial asynchronous receive data synchronization,

parallel-to-serial and serial-to-parallel data conversions for both the transmitter andreceiver sections. These functions are necessary for converting the serial data

streamintoparalleldatathatisrequiredwithdigitaldatasystems.Synchronizationforthe serial data stream is accomplished by adding start and stop bits to the transmitdatatoformadatacharacter(characterorientatedprotocol).Dataintegrityisinsuredbyattachingaparitybittothedatacharacter.Theparitybitischeckedbythereceiverforanytransmissionbiterrors.Theelectroniccircuitrytoprovideallthesefunctionsisfairlycomplex,especiallywhenmanufacturedonasingleintegratedsiliconchip.TheSC16C2550 represents such an integration with greatly enhanced features. TheSC16C2550 is fabricated with an advanced CMOS process.

TheSC16C2550 is an upward solution that provides a dual UART capability with16bytesoftransmitandreceiveFIFOmemory,insteadofnoneinthe16C2450.TheSC16C2550 is designed to work with high speed modems and shared networkenvironments that require fast data processing time. Increased performance isrealized in theSC16C2550 by the transmit and receive FIFOs. This allows the

externalprocessortohandlemorenetworkingtaskswithinagiventime.Forexample,the ST16C2450 without a receive FIFO, will require unloading of the RHR in

93microseconds(thisexampleusesacharacterlengthof11bits,includingstart/stopbits at 115.2kbits/s). This means the external CPU will have to service the receiveFIFO less than every 100 microseconds. However, with the 16 byte FIFO in theSC16C2550, the data buffer will not require unloading/loading for 1.53ms. Thisincreases the service interval, giving the external CPU additional time for otherapplications and reducing the overall UART interrupt servicing time. In addition, thefourselectablereceiveFIFOtriggerinterruptlevelsisuniquelyprovidedformaximumdata throughput performance especially when operating in a multi-channel

environment. The FIFO memory greatly reduces the bandwidth requirement of theexternal controlling CPU, increases performance, and reduces power consumption.TheSC16C2550 is capable of operation up to 5Mbits/s with a 80MHz clock. With acrystal or external clock input of 7.3728MHz, the user can select data rates up to460.8kbits/s.

The rich feature set of theSC16C2550 is available through internal registers.

SelectablereceiveFIFOtriggerlevels,selectableTXandRXbaudrates,andmodeminterfacecontrolsareallstandardfeatures.Followingapower-onresetoranexternalreset, theSC16C2550 is software compatible with the previous generation,ST16C2450.

6.1UART A-B functions

TheUARTprovidestheuserwiththecapabilitytobi-directionallytransferinformationbetweenanexternalCPU,theSC16C2550package,andanexternalserialdevice.Alogic0 on chip select pinsCSA and/orCSB allows the user to conﬁgure, send data,and/or receive data via UART channels A-B. Individual channel select functions areshown inTable3.

Product dataRev. 03 — 19 June 20039 of 46

Philips Semiconductors

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs andIrDA

encoder/decoder

Serial port selection

FunctionnoneUART channel AUART channel BTable 3:

Chip SelectCSA-CSB=1CSA=0CSB=06.2Internal registers

TheSC16C2550 provides two sets of internal registers (A and B) consisting of

12registers each for monitoring and controlling the functions of each channel of theUART. These registers are shown inTable4. The UART registers function as dataholdingregisters(THR/RHR),interruptstatusandcontrolregisters(IER/ISR),aFIFOcontrol register (FCR), line status and control registers (LCR/LSR), modem statusand control registers (MCR/MSR), programmable data rate (clock) control registers(DLL/DLM), and a user accessible scratchpad register (SPR).

Table 4:A2000011110001111

[1][2][3]

Internal registers decodingA1001100110010011

A0010101010100101

Line Status RegisterModem Status RegisterScratchpad RegisterLSB of Divisor LatchMSB of Divisor LatchEnhanced Feature RegisterXon1 wordXon2 wordXoff1 wordXoff2 word

Interrupt Status RegisterREAD modeReceive Holding Register

WRITE modeTransmit Holding RegisterInterrupt Enable RegisterFIFO Control RegisterLine Control RegisterModem Control Registern/an/a

Scratchpad RegisterLSB of Divisor LatchMSB of Divisor LatchEnhanced Feature RegisterXon1 wordXon2 wordXoff1 wordXoff2 word

General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LSR, SPR)[1]Baud rate register set (DLL/DLM)[2]

Enhanced register set (EFR, Xon/off 1-2)[3]

These registers are accessible only when LCR[7] is a logic0.These registers are accessible only when LCR[7] is a logic1.

Enhanced Feature Register, Xon1, 2 and Xoff1, 2 are accessible only when the LCR is set to‘BF(HEX)’.

Product dataRev. 03 — 19 June 200310 of 46

Philips Semiconductors

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs andIrDA

encoder/decoder

6.3FIFO operation

The 16byte transmit and receive data FIFOs are enabled by the FIFO Control

Register (FCR) bit0. The user can set the receive trigger level via FCR bits 6-7, butnot the transmit trigger level. The receiver FIFO section includes a time-out functionto ensure data is delivered to the external CPU. An interrupt is generated wheneverthe Receive Holding Register (RHR) has not been read following the loading of acharacter or the receive trigger level has not been reached.

Table 5:

Flow control mechanism

INT pin activation14814

NegateRTS orsend Xoff481214

AssertRTS orsend Xon14810

Selected trigger level(characters)14814

6.4Hardware ﬂow control

Whenautomatichardwareﬂowcontrolisenabled,theSC16C2550monitorstheCTSpin for a remote buffer overﬂow indication and controls theRTS pin for local bufferoverﬂows. Automatic hardware ﬂow control is selected by setting EFR[6] (RTS) andEFR[7] (CTS) to a logic1. IfCTS transitions from a logic0 to a logic1 indicating aﬂow control request, ISR[5] will be set to a logic1 (if enabled via IER[6,7]), and theSC16C2550willsuspendTXtransmissionsassoonasthestopbitofthecharacterinprocess is shifted out. Transmission is resumed after theCTS input returns to alogic0, indicating more data may be sent.

WiththeAutoRTSfunctionenabled,aninterruptisgeneratedwhenthereceiveFIFOreaches the programmed trigger level. TheRTS pin will not be forced to a logic1(RTSoff),untilthereceiveFIFOreachesthenexttriggerlevel.However,theRTSpinwillreturntoalogic0afterthedatabuffer(FIFO)isunloadedtothenexttriggerlevelbelow the programmed trigger. However, under the above described conditions, theSC16C2550 will continue to accept data until the receive FIFO is full.

6.5Software ﬂow control

When software ﬂow control is enabled, theSC16C2550 compares one or twosequential receive data characters with the programmed Xon/Xoff or Xoff1,2character value(s). If received character(s) match the programmed values, theSC16C2550 will halt transmission (TX) as soon as the current character(s) has

completedtransmission.Whenamatchoccurs,thereceiveready(ifenabledviaXoffIER[5])ﬂagswillbesetandtheinterruptoutputpin(ifreceiveinterruptisenabled)willbe activated. Following a suspension due to a match of the Xoff characters’ values,theSC16C2550 will monitor the receive data stream for a match to the Xon1,2character value(s). If a match is found, theSC16C2550 will resume operation andclear the ﬂags (ISR[4]).

ResetinitiallysetsthecontentsoftheXon/Xoff8-bitﬂowcontrolregisterstoalogic0.Following reset, the user can write any Xon/Xoff value desired for software ﬂowcontrol. Different conditions can be set to detect Xon/Xoff characters and

suspend/resumetransmissions.Whendouble8-bitXon/Xoffcharactersareselected,

939775011621

Product dataRev. 03 — 19 June 200311 of 46

Philips Semiconductors

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs andIrDA

encoder/decoder

theSC16C2550comparestwoconsecutivereceivecharacterswithtwosoftwareﬂowcontrol 8-bit values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissionsaccordingly. Under the above described ﬂow control mechanisms, ﬂow controlcharacters are not placed (stacked) in the user accessible RX data buffer or FIFO.Intheeventthatthereceivebufferisoverﬁllingandﬂowcontrolneedstobeexecuted,theSC16C2550 automatically sends an Xoff message (when enabled) via the serialTX output to the remote modem. TheSC16C2550 sends the Xoff1,2 characters assoon as received data passes the programmed trigger level. To clear this condition,theSC16C2550 will transmit the programmed Xon1,2 characters as soon as receivedata drops below the programmed trigger level.

6.6Special feature software ﬂow control

A special feature is provided to detect an 8-bit character when EFR[5] is set. When8-bit character is detected, it will be placed on the user-accessible data stack alongwith normal incoming RX data. This condition is selected in conjunction with

EFR[0-3].Notethatsoftwareﬂowcontrolshouldbeturnedoffwhenusingthisspecialmode by setting EFR[0-3] to a logic0.

TheSC16C2550 compares each incoming receive character with Xoff2 data. If amatch exists, the received data will be transferred to the FIFO, and ISR[4] will be setto indicate detection of a special character. Although the Internal Register Table(Table7) shows each X-Register with eight bits of character information, the actualnumber of bits is dependent on the programmed word length. Line Control Registerbits LCR[0-1] deﬁne the number of character bits, i.e., either 5bits, 6bits, 7bits or8bits. The word length selected by LCR[0-1] also determine the number of bits thatwillbeusedforthespecialcharactercomparison.Bit0intheX-registerscorrespondswith the LSB bit for the receive character.

6.7Hardware/software and time-out interrupts

The interrupts are enabled by IER[0-3]. Care must be taken when handling theseinterrupts. Following a reset, if Interrupt Enable Register (IER) bit1=1, the

SC16C2550 will issue a Transmit Holding Register interrupt. This interrupt must beserviced prior to continuing operations. The LSR register provides the current

singular highest priority interrupt only. It could be noted that CTS and RTS interruptshave lowest interrupt priority. A condition can exist where a higher priority interruptmay mask the lower priority CTS/RTS interrupt(s). Only after servicing the higherpendinginterruptwillthelowerpriorityCTS/RTSinterrupt(s)bereﬂectedinthestatusregister. Servicing the interrupt without investigating further interrupt conditions canresult in data errors.

When two interrupt conditions have the same priority, it is important to service theseinterrupts correctly. Receive Data Ready and Receive Time Out have the same

interrupt priority (when enabled by IER[3]). The receiver issues an interrupt after thenumber of characters have reached the programmed trigger level. In this case, theSC16C2550 FIFO may hold more characters than the programmed trigger level.Following the removal of a data byte, the user should re-check LSR[0] for additionalcharacters. A Receive Time Out will not occur if the receive FIFO is empty. Thetime-out counter is reset at the center of each stop bit received or each time the

Product dataRev. 03 — 19 June 200312 of 46

Philips Semiconductors

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs andIrDA

encoder/decoder

receive holding register (RHR) is read. The actual time-out value is 4 character time,including data information length, start bit, parity bit, and the size of stop bit, i.e., 1×,1.5×, or 2× bit times.

6.8Programmable baud rate generator

TheSC16C2550supportshighspeedmodemtechnologiesthathaveincreasedinputdata rates by employing data compression schemes. For example, a 33.6kbit/smodem that employs data compression may require a 115.2kbit/s input data rate.A128.0kbit/s ISDN modem that supports data compression may need an inputdatarate of 460.8kbit/s. TheSC16C2550 can support a standard data rate of921.6kbit/s.

A single baud rate generator is provided for the transmitter and receiver, allowingindependent TX/RX channel control. The programmable Baud Rate Generator iscapableofoperatingwithafrequencyofupto80MHz.Toobtainmaximumdatarate,it is necessary to use full rail swing on the clock input. TheSC16C2550 can beconﬁgured for internal or external clock operation. For internal clock oscillatoroperation, an industry standard microprocessor crystal is connected externallybetween the XTAL1 and XTAL2 pins. Alternatively, an external clock can be

connected to the XTAL1 pin to clock the internal baud rate generator for standard orcustom rates (seeTable6).

The generator divides the input 16× clock by any divisor from 1 to 216−1. TheSC16C2550 divides the basic external clock by 16. The basic 16× clock providestable rates to support standard and custom applications using the same systemdesign. The rate table is conﬁgured via the DLL and DLM internal register functions.Customized Baud Rates can be achieved by selecting the proper divisor values forthe MSB and LSB sections of baud rate generator.

Programming the Baud Rate Generator Registers DLM (MSB) and DLL (LSB)provides a user capability for selecting the desired ﬁnal baud rate. The example inTable6 shows the selectable baud rate table available when using a 1.8432MHzexternal clock input.

X11.8432 MHzC147 pFC2100 pFFig 5.Crystal oscillator connection.939775011621

Product dataRev. 03 — 19 June 200313 of 46

Philips Semiconductors

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs andIrDA

encoder/decoder

Baud rate generator programming table using a 1.8432MHz clock

OutputOutputDLM16×clock divisor16×clockdivisorprogramvalue(decimal)(HEX)(HEX)23041536104776838419298322416126321

900600417300180C060302018100C06030201

09060403010000000000000000000000

DLLprogramvalue(HEX)0000170080C060302018100C06030201

Table 6:Outputbaudrate507511015030060012002400360048007200960019.2k38.4k57.6k115.2k

6.9DMA operation

TheSC16C2550 FIFO trigger level provides additional ﬂexibility to the user for blockmode operation. LSR[5,6] provide an indication when the transmitter is empty or hasanemptylocation(s).TheusercanoptionallyoperatethetransmitandreceiveFIFOsin the DMA mode (FCR[3]). When the transmit and receive FIFOs are enabled andtheDMAmodeisde-activated(DMAMode0),theSC16C2550activatestheinterruptoutput pin for each data transmit or receive operation. When DMA mode is activated(DMA Mode1), the user takes the advantage of block mode operation by loading orunloading the FIFO in a block sequence determined by the receive trigger level andthetransmitFIFO.Inthismode,theSC16C2550setstheTXRDY(orRXRDY)outputpinwhencharactersinthetransmitFIFOisbelow16,orthecharactersinthereceiveFIFOs are above the receive trigger level.

6.10Loop-back mode

Theinternalloop-backcapabilityallowson-boarddiagnostics.Intheloop-backmode,the normal modem interface pins are disconnected and reconﬁgured for loop-backinternally (seeFigure6). MCR[0-3] register bits are used for controlling loop-backdiagnostictesting.Intheloop-backmode,thetransmitteroutput(TX)andthereceiverinput (RX) are disconnected from their associated interface pins, and instead areconnected together internally. TheCTS,DSR,CD, andRI are disconnected fromtheirnormalmodemcontrolinputspins,andinsteadareconnectedinternallytoRTS,DTR, MCR[3] (OP2) and MCR[2] (OP1). Loop-back test data is entered into thetransmit holding register via the user data bus interface, D0-D7. The transmit UARTserializes the data and passes the serial data to the receive UART via the internalloop-back connection. The receive UART converts the serial data back into parallel

939775011621

Product dataRev. 03 — 19 June 200314 of 46

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SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs andIrDA

encoder/decoder

datathatisthenmadeavailableattheuserdatainterfaceD0-D7.Theuseroptionallycompares the received data to the initial transmitted data for verifying error-freeoperation of the UART TX/RX circuits.

Inthismode,thereceiverandtransmitterinterruptsarefullyoperational.TheModemControl Interrupts are also operational.

SC16C2550TRANSMITFIFOREGISTERD0–D7IORIOWRESETDATA BUSANDCONTROL LOGICTRANSMITSHIFTREGISTERTXA, TXBMCR[4] = 1INTERCONNECT BUS LINESANDCONTROL SIGNALSRECEIVEFIFOREGISTERRECEIVESHIFTREGISTERRXA, RXBRTSA, RTSBA0–A2CSA, CSBREGISTERSELECTLOGICCTSA, CTSBDTRA, DTRBMODEMCONTROLLOGICDSRA, DSRB(OP1A, OP1B)INTA, INTBTXRDYA, TXRDYBRXRDYA, RXRDYBINTERRUPTCONTROLLOGICCLOCK ANDBAUD RATEGENERATORRIA, RIB(OP2A, OP2B)CDA, CDB002aaa120XTAL1XTAL2Fig 6.Internal loop-back mode diagram.939775011621© Koninklijke Philips Electronics N.V. 2003. All rights reserved.

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SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs andIrDA

encoder/decoder

7.Register descriptions

Table7 details the assigned bit functions for theSC16C2550 internal registers. Theassigned bit functions are more fully deﬁned inSection7.1 throughSection7.11.

Table 7:SC16C2550 internal registers

Shaded bits are only accessible when EFR[4] is set.A2000A1000A0001RegisterDefault[1]Bit 7RHRTHRIERXXXX00bit 7bit 7CTSinterruptBit 6bit 6bit 6RTSinterruptBit 5bit 5bit 5XoffinterruptBit 4bit 4bit 4SleepmodeBit 3bit 3bit 3Bit 2bit 2bit 2Bit 1bit 1bit 1transmitholdingregisterinterruptRCVRFIFOresetINTprioritybit0Bit 0bit 0bit 0receiveholdingregisterFIFOsenableINTstatuswordlengthbit0DTRreceivedataready∆CTSbit 0bit 0bit 8Cont-0Tx, RxControlGeneral Register Set[2]modemreceivestatuslineinterruptstatusinterruptDMAmodeselectINTprioritybit2parityenableXMITFIFOresetINTprioritybit1010FCR00RCVRtrigger(MSB)FIFOsenableddivisorlatchenable0FIFOdataerrorCDbit 7bit 7bit 15AutoCTSRCVRtrigger(LSB)FIFOsenabledreserved0INTprioritybit 4reserved0INTprioritybit 3010ISR01011LCR00set breakset parityevenparityIRenable0stop bitswordlengthbit1RTSoverrunerror∆DSRbit 1bit 1bit 9Cont-1Tx, RxControl110001MCRLSR0060loop backOP2/INT(OP1)enablebreakinterruptCTSbit 4bit 4bit 12framingerror∆CDbit 3bit 3bit 11parityerror∆RIbit 2bit 2bit 10Cont-2Tx, RxControlTHRandTHRTSRemptyemptyRIbit 6bit 6bit 14AutoRTSDSRbit 5bit 5bit 13Specialchar.select110001100101010MSRSPRDLLDLMEFRX0FFXXXX00Special Register Set[3]Enhanced Register Set[4]EnableCont-3IER[4-7],Tx, RxISR[4,5],ControlFCR[4,5],MCR[5-7]bit 4bit 12bit 4bit 12bit 3bit 11bit 3bit 111111[1][2][3][4]

00110101Xon-1Xon-2Xoff-1Xoff-200000000bit 7bit 15bit 7bit 15bit 6bit 14bit 6bit 14bit 5bit 13bit 5bit 13bit 2bit 10bit 2bit 10bit 1bit 9bit 1bit 9bit 0bit 8bit 0bit 8The value shown in represents the register’s initialized HEX value; X=n/a.Accessible only when LCR[7] is logic0.

Baud rate registers accessible only when LCR[7] is logic1.

Enhanced Feature Register, Xon-1,2 and Xoff-1,2 are accessible only when LCR is set to ‘BFHex’.

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Dual UART with 16 bytes of transmit and receive FIFOs andIrDA

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7.1Transmit (THR) and Receive (RHR) Holding Registers

The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) andTransmit Shift Register (TSR). The status of the THR is provided in the Line StatusRegister (LSR). Writing to the THR transfers the contents of the data bus (D7-D0) tothe TSR and UART via the THR, providing that the THR is empty. The THR emptyﬂag in the LSR register will be set to a logic1 when the transmitter is empty or whendataistransferredtotheTSR.NotethatawriteoperationcanbeperformedwhentheTHR empty ﬂag is set (logic0=at least one byte in FIFO/THR, logic1=FIFO/THRempty).

Theserialreceivesectionalsocontainsan8-bitReceiveHoldingRegister(RHR)andaReceiveSerialShiftRegister(RSR).ReceivedataisremovedfromtheSC16C2550and receive FIFO by reading the RHR register. The receive section provides a

mechanism to prevent false starts. On the falling edge of a start or false start bit, aninternal receiver counter starts counting clocks at the 16× clock rate. After 7-1⁄2

clocks,thestartbittimeshouldbeshiftedtothecenterofthestartbit.Atthistimethestart bit is sampled, and if it is still a logic 0 it is validated. Evaluating the start bit inthismannerpreventsthereceiverfromassemblingafalsecharacter.Receiverstatuscodes will be posted in the LSR.

7.2Interrupt Enable Register (IER)

The Interrupt Enable Register (IER) masks the interrupts from receiver ready,transmitter empty, line status and modem status registers. These interrupts wouldnormally be seen on the INTA, INTB output pins.

Table 8:Bit7Interrupt Enable Register bits descriptionSymbolIER[7]DescriptionCTS interrupt.Logic0 = Disable the CTS interrupt (normal default condition).Logic1 = Enable the CTS interrupt. The SC16C2550 issues aninterruptwhentheCTSpintransitionsfromalogic0toalogic1.

IER[6]

RTS interrupt.

Logic0 = Disable the RTS interrupt (normal default condition).Logic1 = Enable the RTS interrupt. The SC16C2550 issues aninterruptwhentheRTSpintransitionsfromalogic0toalogic1.

IER[5]

Xoff interrupt.

Logic0=Disablethesoftwareﬂowcontrol,receiveXoffinterrupt(normal default condition).

Logic1=Enablethesoftwareﬂowcontrol,receiveXoffinterrupt.

IER[4]

Sleep mode.

Logic0 = Disable sleep mode (normal default condition).Logic1 = Enable sleep mode.

IER[3]

Modem Status Interrupt. This interrupt will be issued wheneverthere is a modem status change as reﬂected in MSR[0-3].Logic0 = Disable the modem status register interrupt (normaldefault condition).

Logic1 = Enable the modem status register interrupt.

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Dual UART with 16 bytes of transmit and receive FIFOs andIrDA

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Interrupt Enable Register bits description…continuedSymbolIER[2]

DescriptionReceive Line Status interrupt. This interrupt will be issuedwhenever a receive data error condition exists as reﬂected inLSR[1-4].

Logic0 = Disable the receiver line status interrupt (normaldefault condition).

Logic1 = Enable the receiver line status interrupt.

Table 8:Bit2

1IER[1]

Transmit Holding Register interrupt. In the 16C450 mode, thisinterrupt will be issued whenever the THR is empty, and is

associated with LSR[5]. In the FIFO modes, this interrupt will beissued whenever the FIFO is empty.

Logic0=DisabletheTransmitHoldingRegisterEmpty(TXRDY)interrupt (normal default condition).

Logic1 = Enable the TXRDY (ISR level 3) interrupt.

0IER[0]

Receive Holding Register. In the 16C450 mode, this interrupt willbe issued when the RHR has data, or is cleared when the RHR isempty. In the FIFO mode, this interrupt will be issued when theFIFOhasreachedtheprogrammedtriggerlevelorisclearedwhenthe FIFO drops below the trigger level.

Logic0 = Disable the receiver ready (ISR level 2, RXRDY)interrupt (normal default condition).

Logic1 = Enable the RXRDY (ISR level 2) interrupt.

7.2.1IER versus Transmit/Receive FIFO interrupt mode operation

When the receive FIFO (FCR[0]=logic1), and receive interrupts (IER[0]=logic1)are enabled, the receive interrupts and register status will reﬂect the following:

•ThereceiveRXRDYinterrupt(Level2ISRinterrupt)isissuedtotheexternalCPU

whenthereceiveFIFOhasreachedtheprogrammedtriggerlevel.Itwillbeclearedwhen the receive FIFO drops below the programmed trigger level.

•ReceiveFIFOstatuswillalsobereﬂectedintheuseraccessibleISRregisterwhen

the receive FIFO trigger level is reached. Both the ISR register receive status bitand the interrupt will be cleared when the FIFO drops below the trigger level.

•The receive data ready bit (LSR[0]) is set as soon as a character is transferred

from the shift register (RSR) to the receive FIFO. It is reset when the FIFO isempty.

•When the Transmit FIFO and interrupts are enabled, an interrupt is generated

when the transmit FIFO is empty due to the unloading of the data by the TSR andUART for transmission via the transmission media. The interrupt is cleared eitherby reading the ISR register, or by loading the THR with new data characters.

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Dual UART with 16 bytes of transmit and receive FIFOs andIrDA

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7.2.2IER versus Receive/Transmit FIFO polled mode operation

When FCR[0]=logic1, resetting IER[0-3] enables theSC16C2550 in the FIFOpolled mode of operation. In this mode, interrupts are not generated and the usermust poll the LSR register for TX and/or RX data status. Since the receiver andtransmitter have separate bits in the LSR either or both can be used in the polledmode by selecting respective transmit or receive control bit(s).

••••

LSR[0] will be a logic1 as long as there is one byte in the receive FIFO.

LSR[1-4] will provide the type of receive errors, or a receive break, if encountered.LSR[5] will indicate when the transmit FIFO is empty.

LSR[6] will indicate when both the transmit FIFO and transmit shift register areempty.

•LSR[7] will show if any FIFO data errors occurred.

7.3FIFO Control Register (FCR)

This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFOtrigger levels, and select the DMA mode.

7.3.1

DMA mode

Mode 0 (FCR bit 3 = 0):Set and enable the interrupt for each single transmit orreceive operation, and is similar to the 16C450 mode. Transmit Ready (TXRDY) onPLCC44andLQFP48packageswillgotoalogic0whenevertheFIFO(THR,ifFIFOis not enabled) is empty. Receive Ready (RXRDY) on PLCC44 and LQFP48packageswillgotoalogic0whenevertheReceiveHoldingRegister(RHR)isloadedwith a character.

Mode 1 (FCR bit 3 = 1):Setandenabletheinterruptinablockmodeoperation.Thetransmit interrupt is set when the transmit FIFO is empty.TXRDY on PLCC andLQFP48packagesremainsalogic0aslongasoneemptyFIFOlocationisavailable.The receive interrupt is set when the receive FIFO ﬁlls to the programmed triggerlevel.However,theFIFOcontinuestoﬁllregardlessoftheprogrammedleveluntiltheFIFO is full.RXRDY on PLCC44 and LQFP48 packages transitions LOW when theFIFO reaches the trigger level, and transitions HIGH when the FIFO empties.

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Dual UART with 16 bytes of transmit and receive FIFOs andIrDA

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7.3.2FIFO mode

Table 9:Bit7-6FIFO Control Register bits descriptionSymbolFCR[7](MSB),FCR[6](LSB)

DescriptionRCVR trigger. These bits are used to set the trigger level for thereceive FIFO interrupt.

Logic0 (or cleared) = normal default condition.Logic1 = RX trigger level.

An interrupt is generated when the number of characters in theFIFO equals the programmed trigger level. However, the FIFO willcontinue to be loaded until it is full. Refer toTable10.

5-43

FCR[5-4]FCR[3]

Not used; initialized to logic0.DMA mode select.

Logic0 = Set DMA mode ‘0’Logic1 = Set DMA mode ‘1’

Transmit operation in mode ‘0’: When the SC16C2550 is in the16C450 mode (FIFOs disabled; FCR[0] = logic0) or in the FIFOmode (FIFOs enabled; FCR[0] = logic1; FCR[3] = logic0), andwhen there are no characters in the transmit FIFO or transmitholding register, theTXRDY pin in PLCC44 or LQFP48 packageswill be a logic0. Once active, theTXRDY pin will go to a logic1after the ﬁrst character is loaded into the transmit holding register.Receive operation in mode ‘0’: When the SC16C2550 is in

mode‘0’(FCR[0]=logic0),orintheFIFOmode(FCR[3]=logic0)and there is at lease one character in the receive FIFO, theRXRDY pin will be a logic0. Once active, theRXRDY pin onPLCC44andLQFP48packageswillgotoalogic1whenthereareno more characters in the receiver.

Transmit operation in mode ‘1’: When the SC16C2550 is inFIFOmode(FCR[0]=logic1;FCR[3]=logic1),theTXRDYpinonPLCC44andLQFP48packageswillbealogic1whenthetransmitFIFO is completely full. It will be a logic0 if one or more FIFOlocations are empty.

Receiveoperationinmode‘1’:WhentheSC16C2550isinFIFOmode(FCR[0]=logic1;FCR[3]=logic1)andthetriggerlevelhasbeen reached, or a Receive Time-Out has occurred, theRXRDYpin on PLCC44 and LQFP48 packages will go to a logic0. Onceactivated,itwillgotoalogic1aftertherearenomorecharactersinthe FIFO.

FCR[2]

XMIT FIFO reset.

Logic0 = Transmit FIFO not reset (normal default condition).Logic1 = Clears the contents of the transmit FIFO and resetsthe FIFO counter logic (the transmit shift register is not clearedoraltered).Thisbitwillreturntoalogic0afterclearingtheFIFO.

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FIFO Control Register bits description…continuedSymbolFCR[1]

DescriptionRCVR FIFO reset.

Logic0 = Receive FIFO not reset (normal default condition).Logic1=ClearsthecontentsofthereceiveFIFOandresetstheFIFO counter logic (the receive shift register is not cleared oraltered). This bit will return to a logic0 after clearing the FIFO.

Table 9:Bit1

0FCR[0]FIFOs enabled.

Logic0=DisablethetransmitandreceiveFIFO(normaldefaultcondition).

Logic1 = Enable the transmit and receive FIFO.This bit mustbe a ‘1’ when other FCR bits are written to, or they will notbe programmed.

Table 10:FCR[7]0011

RCVR trigger levelsFCR[6]0101

RX FIFO trigger level01040814

7.4Interrupt Status Register (ISR)

TheSC16C2550 provides four levels of prioritized interrupts to minimize externalsoftware interaction. The Interrupt Status Register (ISR) provides the user with fourinterruptstatusbits.PerformingareadcycleontheISRwillprovidetheuserwiththehighest pending interrupt level to be serviced. No other interrupts are acknowledgeduntil the pending interrupt is serviced. A lower level interrupt may be seen afterservicing the higher level interrupt and re-reading the interrupt status bits.Table 11“Interrupt source” shows the data values (bits 0-3) for the four prioritized interruptlevels and the interrupt sources associated with each of these interrupt levels.

Table 11:Prioritylevel1223456

Interrupt sourceISR[5]0000001

ISR[4]0000010

ISR[3]0010000

ISR[2]1110000

ISR[1]1001000

ISR[0]0000000

Source of the interruptLSR(ReceiverLineStatusRegister)

RXRDY (Received DataReady)

RXRDY (Receive Datatime-out)

TXRDY (Transmitter

Holding Register Empty)MSR (Modem StatusRegister)

RXRDY (Received Xoffsignal) / Special character CTS, RTSchange of state

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Interrupt Status Register bits descriptionSymbolISR[7-6]

DescriptionFIFOsenabled.Thesebitsaresettoalogic0whentheFIFOsarenot being used in the 16C450 mode. They are set to a logic1when the FIFOs are enabled in the SC16C2550 mode.Logic0 or cleared = default condition.

INT priority bits 4-3. These bits are enabled when EFR[4] is set toa logic1. ISR[4] indicates that matching Xoff character(s) havebeen detected. ISR[5] indicates that CTS, RTS have been

generated.Notethatoncesettoalogic1,theISR[4]bitwillstayalogic1 until Xon character(s) are received.Logic0 or cleared = default condition.

INT priority bits 2-0. These bits indicate the source for a pendinginterrupt at interrupt priority levels 1, 2, and 3 (seeTable11).Logic0 or cleared = default condition.INT status.

Logic0 = An interrupt is pending and the ISR contents may beused as a pointer to the appropriate interrupt service routine.Logic1 = No interrupt pending (normal default condition).

Table 12:Bit7-6

5-4ISR[5-4]

3-1ISR[3-1]

0ISR[0]

7.5Line Control Register (LCR)

The Line Control Register is used to specify the asynchronous data communicationformat. The word length, the number of stop bits, and the parity are selected bywriting the appropriate bits in this register.

Table 13:Bit7Line Control Register bits descriptionSymbolLCR[7]DescriptionDivisor latch enable. The internal baud rate counter latch andEnhance Feature mode enable.

Logic0= Divisor latch disabled (normal default condition).Logic1 = Divisor latch enabled.

LCR[6]

Set break. When enabled, the Break control bit causes a breakcondition to be transmitted (the TX output is forced to a logic0state). This condition exists until disabled by setting LCR[6] to alogic0.

Logic0 = no TX break condition (normal default condition)Logic1 = forces the transmitter output (TX) to a logic0 foralerting the remote receiver to a line break condition.

5-32

LCR[5-3]LCR[2]

Programs the parity conditions (seeTable14).

Stop bits. The length of stop bit is speciﬁed by this bit in

conjunction with the programmed word length (seeTable15).Logic0 or cleared = default condition.

1-0

LCR[1-0]

Wordlengthbits1,0.Thesetwobitsspecifythewordlengthtobetransmitted or received (seeTable16).Logic0 or cleared = default condition.

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Dual UART with 16 bytes of transmit and receive FIFOs andIrDA

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LCR[5-3] parity selectionLCR[4]X0101

LCR[3]01111

Parity selectionno parityODD parityEVEN parityforced parity ‘1’forced parity ‘0’

Table 14:LCR[5]XX001Table 15:LCR[2]011Table 16:LCR[1]0011

LCR[2] stop bit lengthWord length5, 6, 7, 856, 7, 8

Stop bit length (bit times)11-1⁄22

LCR[1-0] word lengthLCR[0]0101

Word length5678

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7.6Modem Control Register (MCR)

This register controls the interface with the modem or a peripheral device.

Table 17:Bit76

Modem Control Register bits descriptionSymbolMCR[7]MCR[6]

DescriptionReserved; set to ‘0’.IR enable.

Logic0 = Enable the standard modem receive and transmitinput/output interface (normal default condition).

Logic1 = Enable infrared IrDA receive and transmit inputs/outputs.While in this mode, the TX/RX output/inputs are routed to theinfrared encoder/decoder. The data input and output levels willconform to the IrDA infrared interface requirement. As such, whileinthismode,theinfraredTXoutputwillbealogic0duringidledataconditions.

MCR[5]MCR[4]

Reserved; set to ‘0’.

Loop-back. Enable the local loop-back mode (diagnostics). In thismode the transmitter output (TX) and the receiver input (RX),CTS,DSR,CD, andRI are disconnected from the SC16C2550 I/O pins.Internally the modem data and control pins are connected into a

loop-backdataconﬁguration(seeFigure6).Inthismode,thereceiverand transmitter interrupts remain fully operational. The Modem

ControlInterruptsarealsooperational,buttheinterrupts’sourcesareswitched to the lower four bits of the Modem Control. Interruptscontinue to be controlled by the IER register.

Logic0 = Disable loop-back mode (normal default condition).Logic1 = Enable local loop-back mode (diagnostics).

3MCR[3]OP2/INT enableLogic0 = Forces INT (A-B) outputs to the 3-State mode and setsOP2 to a logic1 (normal default condition).

Logic1 = Forces the INT (A-B outputs to the active mode and setsOP2 to a logic0.

2MCR[2](OP1).OP1A/OP1B are not available as an external signal in theSC16C2550. This bit is instead used in the Loop-back mode only. Intheloop-backmode,thisbitisusedtowritethestateofthemodemRIinterface signal.RTSLogic0= ForceRTS output to a logic1 (normal default condition).Logic1=ForceRTS output to a logic0.

0MCR[0]DTRLogic0= ForceDTR output to a logic1 (normal default condition).Logic1 = ForceDTR output to a logic0.

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Dual UART with 16 bytes of transmit and receive FIFOs andIrDA

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7.7Line Status Register (LSR)

This register provides the status of data transfers between theSC16C2550 andtheCPU.

Table 18:Bit7Line Status Register bits descriptionSymbolLSR[7]DescriptionFIFO data error.Logic0 = No error (normal default condition).

Logic1 = At least one parity error, framing error or break

indication is in the current FIFO data. This bit is cleared whentherearenoremainingerrorﬂagsassociatedwiththeremainingdata in the FIFO.

LSR[6]

THRandTSRempty.ThisbitistheTransmitEmptyindicator.Thisbitissettoalogic1wheneverthetransmitholdingregisterandthetransmitshiftregisterarebothempty.Itisresettologic0whenevereither the THR or TSR contains a data character. In the FIFO

mode,thisbitissetto‘1’wheneverthetransmitFIFOandtransmitshift register are both empty.

THR empty. This bit is the Transmit Holding Register Empty

indicator.ThisbitindicatesthattheUARTisreadytoacceptanewcharacterfortransmission.Inaddition,thisbitcausestheUARTtoissue an interrupt to CPU when the THR interrupt enable is set.TheTHRbitissettoalogic1whenacharacteristransferredfromthe transmit holding register into the transmitter shift register. Thebit is reset to a logic0 concurrently with the loading of the

transmitter holding register by the CPU. In the FIFO mode, this bitis set when the transmit FIFO is empty; it is cleared when at least1byte is written to the transmit FIFO.Break interrupt.

Logic0 = No break condition (normal default condition).Logic1=Thereceiverreceivedabreaksignal(RXwasalogic0foronecharacterframetime).IntheFIFOmode,onlyonebreakcharacter is loaded into the FIFO.

LSR[3]

Framing error.

Logic0 = No framing error (normal default condition).

Logic1 = Framing error. The receive character did not have avalid stop bit(s). In the FIFO mode, this error is associated withthe character at the top of the FIFO.

LSR[2]

Parity error.

Logic0 = No parity error (normal default condition.

Logic1 = Parity error. The receive character does not have

correctparityinformationandissuspect.IntheFIFOmode,thiserror is associated with the character at the top of the FIFO.

5LSR[5]

4LSR[4]

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Line Status Register bits description…continuedSymbolLSR[1]

DescriptionOverrun error.

Logic0= No overrun error (normal default condition).

Logic1=Overrun error. A data overrun error occurred in thereceiveshiftregister.Thishappenswhenadditionaldataarriveswhile the FIFO is full. In this case, the previous data in the shiftregister is overwritten. Note that under this condition, the databyte in the receive shift register is not transferred into the FIFO,therefore the data in the FIFO is not corrupted by the error.

Table 18:Bit1

0LSR[0]Receive data ready.

Logic0= No data in receive holding register or FIFO (normaldefault condition).

Logic1 = Data has been received and is saved in the receiveholding register or FIFO.

7.8Modem Status Register (MSR)

This register provides the current state of the control interface signals from the

modem, or other peripheral device to which theSC16C2550 is connected. Four bitsof this register are used to indicate the changed information. These bits are set to alogic1wheneveracontrolinputfromthemodemchangesstate.Thesebitsaresettoa logic0 whenever the CPU reads this register.

Table 19:Bit7Modem Status Register bits descriptionSymbolMSR[7]DescriptionCD. During normal operation, this bit is the complement of theCDinput.Readingthisbitintheloop-backmodeproducesthestateofMCR[3] (OP2).RI. During normal operation, this bit is the complement of theRIinput.Readingthisbitintheloop-backmodeproducesthestateofMCR[2] (OP1).DSR. During normal operation, this bit is the complement of theDSR input. During the loop-back mode, this bit is equivalent toMCR[0] (DTR).CTS. During normal operation, this bit is the complement of theCTS input. During the loop-back mode, this bit is equivalent toMCR[1] (RTS).∆CD[1]Logic 0= NoCD change (normal default condition).Logic 1=TheCD input to the SC16C2550 has changed statesincethelasttimeitwasread.AmodemStatusInterruptwillbegenerated.

2MSR[2]∆RI[1]Logic 0= NoRI change (normal default condition).Logic 1=TheRI input to the SC16C2550 has changed from alogic0 to a logic1. A modem Status Interrupt will be generated.

6MSR[6]5MSR[5]

4MSR[4]

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Dual UART with 16 bytes of transmit and receive FIFOs andIrDA

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Modem Status Register bits description…continuedSymbolMSR[1]Description∆DSR[1]Logic0= NoDSR change (normal default condition).Logic1=TheDSR input to the SC16C2550 has changed statesincethelasttimeitwasread.AmodemStatusInterruptwillbegenerated.

Table 19:Bit10MSR[0]∆CTS[1]Logic0= NoCTS change (normal default condition).Logic1 = TheCTS input to the SC16C2550 has changed statesincethelasttimeitwasread.AmodemStatusInterruptwillbegenerated.

[1]Whenever any MSR bit 0-3 is set to logic 1, a Modem Status Interrupt will be generated.

7.9Scratchpad Register (SPR)

TheSC16C2550 provides a temporary data register to store 8 bits of userinformation.

7.10Enhanced Feature Register (EFR)

Enhanced features are enabled or disabled using this register.

Bits 0 through 4 provide single or dual character software ﬂow control selection.When the Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected, the double8-bit words are concatenated into two sequential numbers.

Table 20:Bit7Enhanced Feature Register bits description

DescriptionAutomatic CTS ﬂow control.Logic0=Automatic CTS ﬂow control is disabled (normal defaultcondition).

Logic1=Enable Automatic CTS ﬂow control. Transmission will stopwhenCTS goes to a logical1. Transmission will resume when theCTSpin returns to a logical0.

EFR[6]

AutomaticRTSﬂowcontrol.AutomaticRTSmaybeusedforhardwareﬂowcontrol by enabling EFR[6]. When Auto-RTS is selected, an interrupt willbe generated when the receive FIFO is ﬁlled to the programmed triggerlevelandRTSwillgotoalogic1atthenexttriggerlevel.RTSwillreturntoa logic0 when data is unloaded below the next lower trigger level

(programmedtriggerlevel1).Thestateofthisregisterbitchangeswiththestatus of the hardware ﬂow control.RTS functions normally whenhardware ﬂow control is disabled.

0=Automatic RTS ﬂow control is disabled (normal default condition).1=Enable Automatic RTS ﬂow control.

Product dataRev. 03 — 19 June 200327 of 46

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SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs andIrDA

encoder/decoder

Enhanced Feature Register bits description…continuedDescriptionSpecial Character Detect.

Logic 0 = Special character detect disabled (normal default condition).Logic 1 = Special character detect enabled. The SC16C2550 compareseach incoming receive character with Xoff2 data. If a match exists, thereceived data will be transferred to FIFO and ISR[4] will be set toindicate detection of special character. Bit-0 in the X-registers

correspondswiththeLSBbitforthereceivecharacter.Whenthisfeatureisenabled,thenormalsoftwareﬂowcontrolmustbedisabled(EFR[3-0]must be set to a logic0).

Table 20:Bit5

SymbolEFR[5]

4EFR[4]

Enhancedfunctioncontrolbit.ThecontentofIER[7-4],ISR[5-4],FCR[5-4],andMCR[7-5]canbemodiﬁedandlatched.Aftermodifyinganybitsintheenhancedregisters,EFR[4]canbesettoalogic0tolatchthenewvalues.This feature prevents existing software from altering or overwriting theSC16C2550 enhanced functions.

Logic0=disable/latchenhancedfeatures.IER[7-4],ISR[5-4],FCR[5-4],and MCR[7-5] are saved to retain the user settings, then IER[7-4]

ISR[5-4], FCR[5-4], and MCR[7-5] are set to a logic0 to be compatiblewith SC16C5 mode. (Normal default condition.)

Logic1 = Enables the enhanced functions. When this bit is set to alogic1, all enhanced features of the SC16C2550 are enabled and usersettings stored during a reset will be restored.

3-0

EFR[3-0]Cont-3-0 Tx, Rx control. Logic 0 or cleared is the default condition.

Combinations of software ﬂow control can be selected by programmingthese bits. SeeTable21.

Software ﬂow control functions[1]Cont-20011XXX011

Cont-1XXXX010111

Cont-0XXXX001111

TX, RX software ﬂow controlsNo transmit ﬂow controlTransmit Xon1/Xoff1Transmit Xon2/Xoff2

Transmit Xon1 and Xon2/Xoff1 and Xoff2No receive ﬂow controlReceiver compares Xon1/Xoff1Receiver compares Xon2/Xoff2Transmit Xon1/Xoff1

Receiver compares Xon1 and Xon2, Xoff1 and Xoff2Transmit Xon2/Xoff2

Receiver compares Xon1 and Xon2/Xoff1 and Xoff2Transmit Xon1 and Xon2/Xoff1 and Xoff2

Receiver compares Xon1 and Xon2/Xoff1 and Xoff2

Table 21:Cont-30101XXX101

[1]When using a software ﬂow control the Xon/Xoff characters cannot be used for data transfer.

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Dual UART with 16 bytes of transmit and receive FIFOs andIrDA

encoder/decoder

7.11SC16C2550 external reset condition

Table 22:RegisterIERFCRISRLCRMCRLSRMSRSPRDLLDLMTable 23:OutputTXA, TXBOP2A,OP2BRTSA,RTSBDTRA,DTRBINTA, INTB

Reset state for registers

Reset stateIER[7-0] = 0FCR[7-0] = 0

ISR[7-1] = 0; ISR[0] = 1LCR[7-0] = 0MCR[7-0] = 0

LSR[7] = 0; LSR[6-5] = 1; LSR[4-0] = 0MSR[7-4] = input signals; MSR[3-0] = 0SFR[7-0] = 1DLL[7-0] = XDLM[7-0] = X

Reset state for outputs

Reset stateLogic 1Logic 1Logic 1Logic 13-State condition

8.Limiting values

Table 24:Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).SymbolVCCVnTambTstgPtot(pack)

Parametersupply voltagevoltage at any pinoperating temperaturestorage temperaturetotal power dissipationper package

ConditionsMin-GND−0.3−40−65-Max7VCC+0.3+85+150500

UnitVV°C°CmW

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Dual UART with 16 bytes of transmit and receive FIFOs andIrDA

encoder/decoder

9.Static characteristics

Table 25:DC electrical characteristics

Tamb=−40°C to +85°C; VCC=2.5V, 3.3V or 5.0V±10%, unless otherwise speciﬁed.SymbolVIL(CK)VIH(CK)VILVIHVOL

ParameterLOW-level clock input voltageHIGH-level clock input voltageLOW-level input voltage(except X1 clock)HIGH-level input voltage(except X1 clock)LOW-level output voltageonall outputs[1]

IOL=5mA(databus)IOL=4mA(other outputs)IOL=2mA(databus)IOL=1.6mA(other outputs)

VOH

HIGH-level output voltage

IOH=−5mA(databus)IOH=−1mA(other outputs)IOH=−800µA(data bus)IOH=−400µA(other outputs)

ILILICLICCCi

[1]

ConditionsMin−0.31.8−0.31.6------1.851.85--f=5MHz

2.5VMax0.45VCC0.65---0.40.4----±10±303.55

Min−0.32.4−0.32.0-----2.0------

3.3VMax0.6VCC0.8--0.4------±10±304.55

Min−0.53.0−0.52.2----2.4-------

5.0VMax0.6VCC0.8-0.4-------±10±304.55

UnitVVVVVVVVVVVVµAµAmApF

LOW-level input leakagecurrentclock leakagesupply currentinput capacitance

Except x2, VOL=1V typical.

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Dual UART with 16 bytes of transmit and receive FIFOs andIrDA

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10.Dynamic characteristics

Table 26:AC electrical characteristics

Tamb=−40°C to +85°C; VCC=2.5V, 3.3V or 5.0V±10%, unless otherwise speciﬁed.Symbolt1w, t2wt3wt6st6ht7dt7wt7ht9dt12dt12ht13dt13wt13ht15dt16st16ht17dt18dt19dt20dt21dt22dt23dt24dt25dt26dt27dt28dtRESETN

[1][2]

Parameterclock pulse durationoscillator/clock frequencyaddress set-up timeaddress hold timeIOR delay from chip selectIOR strobe widthchip select hold time fromIORread cycle delaydelay fromIOR to datadata disable time

IOW delay from chip selectIOW strobe widthchip select hold time fromIOW write cycle delaydata set-up timedata hold time

delay fromIOW to outputdelay to set interrupt from Modeminput

delay to reset interrupt fromIORdelay from stop to set interruptdelay fromIOR to reset interruptdelay from start to set interruptdelay fromIOW to transmit startdelay fromIOW to reset interruptdelay from stop to setRXRDYdelay fromIOR to resetRXRDYdelay fromIOW to setTXRDYdelay from start to resetTXRDYReset pulse widthbaud rate divisor

ConditionsMin10

[1]

2.5VMax-48------7715--[2]----10010010011001002410011001008-216−1

Min6-001026020--1020025205------8-----401

3.3VMax-80------2615--[2]----3324241294524451458-216−1

001023020--1015020155------8-----401Min6

5.0VMax-80------2315--[2]----292323128402440140408-216−1

UnitnsMHznsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsRclknsnsRclknsRclknsnsRclknsRclk

-001025pF load25pF load25pF load25pF load

77020--10200[3]

252015

25pF load25pF load25pF load25pF load------8-----2001

Applies to external clock, crystal oscillator max 24MHz.

IOWstrobemax=--------------------------------------2(Baudratemax)

= 333ns (for Baudratemax = 1.5Mbits/s)= 1µs (for Baudratemax = 460.8kbits/s)= 4µs (for Baudratemax = 115.2kbits/s)

When inboth DMA mode0and FIFO enable mode, the write cycle delay should be larger than one x1, clock cycle.

[3]

939775011621

Product dataRev. 03 — 19 June 200331 of 46

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SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs andIrDA

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10.1Timing diagrams

t6hVALIDADDRESSA0–A2t6st13hCSxACTIVEt13dt13wt15dIOWACTIVEt16ht16sD0–D7DATA002aaa109Fig 7.General write timing.t6hVALIDADDRESSA0–A2t6st7hCSxACTIVEt7dt7wt9dIORACTIVEt12ht12dD0–D7DATA002aaa110Fig 8.General read timing.939775011621© Koninklijke Philips Electronics N.V. 2003. All rights reserved.

Product dataRev. 03 — 19 June 200332 of 46

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Dual UART with 16 bytes of transmit and receive FIFOs andIrDA

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IOWACTIVEt17dRTSDTRCHANGE OF STATECHANGE OF STATEDCDCTSDSRt18dt18dCHANGE OF STATECHANGE OF STATEINTACTIVEACTIVEACTIVEt19dIORACTIVEACTIVEACTIVEt18dRICHANGE OF STATE002aaa111Fig 9.Modem input/output timing.t2wt1wEXTERNALCLOCKt3w002aaa112Fig 10.External clock timing.939775011621© Koninklijke Philips Electronics N.V. 2003. All rights reserved.

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Dual UART with 16 bytes of transmit and receive FIFOs andIrDA

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STARTBITDATA BITS (5-8)PARITYBITSTOPBITNEXTDATASTARTBITRXD0D1D2D3D4D5D6D75 DATA BITS6 DATA BITSt20d7 DATA BITSINTACTIVEt21dIORACTIVE16 BAUD RATE CLOCK002aaa113Fig 11.Receive timing.939775011621© Koninklijke Philips Electronics N.V. 2003. All rights reserved.

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Dual UART with 16 bytes of transmit and receive FIFOs andIrDA

encoder/decoder

STARTBITDATA BITS (5–8)PARITYBITSTOPBITNEXTDATASTARTBITRXD0D1D2D3D4D5D6D7t25dACTIVEDATAREADYt26dRXRDYIORACTIVE002aaa114Fig 12.Receive ready timing in non-FIFO mode.STARTBITDATA BITS (5–8)PARITYBITSTOPBITRXD0D1D2D3D4D5D6D7FIRST BYTE THATREACHES THETRIGGER LEVELt25dACTIVEDATAREADYt26dRXRDYIORACTIVE002aaa115Fig 13.Receive ready timing in FIFO mode.939775011621© Koninklijke Philips Electronics N.V. 2003. All rights reserved.

Product dataRev. 03 — 19 June 200335 of 46

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SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs andIrDA

encoder/decoder

STARTBITDATA BITS (5–8)PARITYBITSTOPBITNEXTDATASTARTBITTXD0D1D2D3D4D5D6D75 DATA BITS6 DATA BITS7 DATA BITSINTt22dt23dIOWACTIVEACTIVE TX READYt24dACTIVE16 BAUD RATE CLOCK002aaa116Fig 14.Transmit timing.939775011621© Koninklijke Philips Electronics N.V. 2003. All rights reserved.

Product dataRev. 03 — 19 June 200336 of 46

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SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs andIrDA

encoder/decoder

STARTBITDATA BITS (5-8)PARITYBITSTOPBITNEXTDATASTARTBITTXD0D1D2D3D4D5D6D7IOWACTIVED0–D7BYTE #1t27dTXRDYTRANSMITTERNOT READYACTIVETRANSMITTER READY002aaa117Fig 15.Transmit ready timing in non-FIFO mode.939775011621© Koninklijke Philips Electronics N.V. 2003. All rights reserved.

Product dataRev. 03 — 19 June 200337 of 46

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SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs andIrDA

encoder/decoder

STARTBITDATA BITS (5-8)PARITYBITSTOPBITTXD0D1D2D3D4D5D6D75 DATA BITS6 DATA BITS7 DATA BITSIOWACTIVEt28dD0–D7BYTE #16t27dTXRDYFIFO FULL002aaa118Fig 16.Transmit ready timing in FIFO mode (DMA mode ‘1’).939775011621© Koninklijke Philips Electronics N.V. 2003. All rights reserved.

Product dataRev. 03 — 19 June 200338 of 46

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Dual UART with 16 bytes of transmit and receive FIFOs andIrDA

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11.Package outline

DIP40: plastic dual in-line package; 40 leads (600 mil)

SOT129-1

seating planeDMEA2ALA1cZeb1b4021wM(e )1MHpin 1 indexE12005scale10 mmDIMENSIONS (inch dimensions are derived from the original mm dimensions)UNITmminchesAmax.4.70.19A 1min.0.510.02A 2max.40.16b1.701.140.0670.045b10.530.380.0210.015c0.360.230.0140.009D(1)E(1)e2.0.1e115.240.6L3.603.050.140.12ME15.8015.240.620.60MH17.4215.900.690.63w0.20.01Z(1)max.2.25 0.0 52.551.52.0672.02814.113.70.560.Note1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINEVERSIONSOT129-1 REFERENCES IEC051G08 JEDECMO-015 JEITASC-511-40EUROPEANPROJECTIONISSUE DATE99-12-2703-02-13Fig 17.DIP40 package outline (SOT129-1).

939775011621

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PLCC44: plastic leaded chip carrier; 44 leadsSOT187-2

eDyXAZEeE392928bpb1wM40441pin 1 indexEHEAA4A1(A )3eβk618Lp7eDHD17ZDBvMBvMAdetail X05scale10 mmDIMENSIONS (mm dimensions are derived from the original inch dimensions)A4A1UNITAA3D(1)E(1)eeDeEHDbpb1max.min.mminches4.574.190.510.250.013.050.120.530.330.810.66HEkLp1.441.02v0.18w0.18y0.1ZD(1)ZE(1)max.max.2.162.16β16.6616.6616.0016.0017.6517.651.221.2716.5116.5114.9914.9917.4017.401.070.630.590.630.590.1800.020.1650.0210.0320.6560.6560.050.0130.0260.6500.6500.6950.6950.0480.0570.0070.0070.0040.0850.0850.6850.6850.0420.04045oNote1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINEVERSIONSOT187-2 REFERENCES IEC112E10 JEDECMS-018 JEITAEDR-7319EUROPEANPROJECTIONISSUE DATE99-12-2701-11-14Fig 18.PLCC44 package outline (SOT187-2).

939775011621

Product dataRev. 03 — 19 June 200340 of 46

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Dual UART with 16 bytes of transmit and receive FIFOs andIrDA

encoder/decoder

LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mmSOT313-2

cyX36372524ZEAeEHEAA2A1(A )3θwMpin 1 index48 112ZDvMA13detail XbpLLpebpDHDwMBvMB02.5scale5 mmDIMENSIONS (mm are the original dimensions)UNITmmNote1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINEVERSION SOT313-2 REFERENCES IEC136E05 JEDECMS-026 JEITAEUROPEANPROJECTIONAmax.1.6A10.200.05A21.451.35A30.25bp0.270.17c0.180.12D(1)7.16.9E(1)7.16.9e0.5HD9.158.85HE9.158.85L1Lp0.750.45v0.2w0.12y0.1ZD(1)ZE(1)0.950.550.950.55θ70ooISSUE DATE00-01-1903-02-25Fig 19.LQFP48 package outline (SOT313-2).

939775011621

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Dual UART with 16 bytes of transmit and receive FIFOs andIrDA

encoder/decoder

12.Soldering

12.1Introduction

This text gives a very brief insight to a complex technology. A more in-depth accountof soldering ICs can be found in ourData Handbook IC26; Integrated CircuitPackages (document order number 939865290011).

ThereisnosolderingmethodthatisidealforallICpackages.Wavesolderingisoftenpreferred when through-hole and surface mount components are mixed on one

printed-circuit board. Wave soldering can still be used for certain surface mount ICs,but it is not suitable for ﬁne pitch SMDs. In these situations reﬂow soldering is

recommended. Driven by legislation and environmental forces the worldwide use oflead-free solder pastes is increasing.

12.2Through-hole mount packages

12.2.1

Soldering by dipping or by solder wave

Typical dwell time of the leads in the wave ranges from 3to4seconds at 250°C or265°C, depending on solder material applied, SnPb or Pb-free respectively.The total contact time of successive solder waves must not exceed 5seconds.The device may be mounted up to the seating plane, but the temperature of the

plasticbodymustnotexceedthespeciﬁedmaximumstoragetemperature(Tstg(max)).If the printed-circuit board has been pre-heated, forced cooling may be necessaryimmediately after soldering to keep the temperature within the permissible limit.

12.2.2Manual soldering

Apply the soldering iron (24V or less) to the lead(s) of the package, either below theseatingplaneornotmorethan2mmaboveit.Ifthetemperatureofthesolderingironbit is less than 300°C it may remain in contact for up to 10seconds. If the bittemperature is between 300and400°C, contact may be up to 5seconds.

12.3Surface mount packages

12.3.1

Reﬂow soldering

Reﬂowsolderingrequiressolderpaste(asuspensionofﬁnesolderparticles,ﬂuxandbindingagent)tobeappliedtotheprinted-circuitboardbyscreenprinting,stencillingor pressure-syringe dispensing before package placement.

Several methods exist for reﬂowing; for example, convection or convection/infraredheating in a conveyor type oven. Throughput times (preheating, soldering andcooling) vary between 100and200seconds depending on heating method.Typical reﬂow peak temperatures range from 215to270°C depending on solderpaste material. The top-surface temperature of the packages should preferably bekept:

•below 220°C (SnPb process) or below 245°C (Pb-free process)

–for all the BGA and SSOP-T packages

939775011621

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Dual UART with 16 bytes of transmit and receive FIFOs andIrDA

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–for packages with a thickness≥2.5mm

–for packages with a thickness <2.5mm and a volume≥350mm3 so calledthick/large packages.

•below235°C(SnPbprocess)orbelow260°C(Pb-freeprocess)forpackageswith

a thickness <2.5mm and a volume <350mm3 so called small/thin packages.Moisture sensitivity precautions, as indicated on packing, must be respected at alltimes.

12.3.2

Wave soldering

Conventional single wave soldering is not recommended for surface mount devices(SMDs) or printed-circuit boards with a high component density, as solder bridgingand non-wetting can present major problems.

To overcome these problems the double-wave soldering method was speciﬁcallydeveloped.

If wave soldering is used the following conditions must be observed for optimalresults:

•Use a double-wave soldering method comprising a turbulent wave with high

upward pressure followed by a smooth laminar wave.

•For packages with leads on two sides and a pitch (e):

–largerthanorequalto1.27mm,thefootprintlongitudinalaxisispreferredtobeparallel to the transport direction of the printed-circuit board;

–smaller than 1.27mm, the footprint longitudinal axismust be parallel to thetransport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

•For packages with leads on four sides, the footprint must be placed at a 45° angle

to the transport direction of the printed-circuit board. The footprint mustincorporate solder thieves downstream and at the side corners.

During placement and before soldering, the package must be ﬁxed with a droplet ofadhesive. The adhesive can be applied by screen printing, pin transfer or syringedispensing. The package can be soldered after the adhesive is cured.

Typical dwell time of the leads in the wave ranges from 3to4seconds at 250°C or265°C, depending on solder material applied, SnPb or Pb-free respectively.Amildly-activated ﬂux will eliminate the need for removal of corrosive residues inmost applications.

12.3.3

Manual soldering

Fix the component by ﬁrst soldering two diagonally-opposite end leads. Use a lowvoltage (24V or less) soldering iron applied to the ﬂat part of the lead. Contact timemust be limited to 10seconds at up to 300°C.

When using a dedicated tool, all other leads can be soldered in one operation within2to5seconds between 270and320°C.

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Dual UART with 16 bytes of transmit and receive FIFOs andIrDA

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12.4Package related soldering information

Table 27:MountingThrough-holemountSurface mount

Suitability of IC packages for wave, reﬂow and dipping soldering methods

Package[1]Soldering methodWaveDBS, DIP, HDIP, SDIP, SILsuitable[3]BGA, LBGA, LFBGA,SQFP, SSOP-T[4],TFBGA, VFBGADHVQFN, HBCC, HBGA,HLQFP, HSQFP, HSOP,HTQFP, HTSSOP,

HVQFN, HVSON, SMSPLCC[6], SO, SOJLQFP, QFP, TQFPSSOP, TSSOP, VSO,VSSOP

[1][2]

Reﬂow[2]−suitable

Dippingsuitable−

not suitable

not suitable[5]suitable−

suitable

not recommended[6][7]not recommended[8]

suitablesuitablesuitable

−−−

[3][4]

[5]

[6][7][8]

For more detailed information on the BGA packages refer to the(LF)BGA Application Note(AN01026); order a copy from your Philips Semiconductors sales ofﬁce.

Allsurfacemount(SMD)packagesaremoisturesensitive.Dependinguponthemoisturecontent,themaximumtemperature(withrespecttotime)andbodysizeofthepackage,thereisariskthatinternalor external package cracks may occur due to vaporization of the moisture in them (the so calledpopcorn effect). For details, refer to the Drypack information in theDataHandbook IC26; IntegratedCircuit Packages; Section: Packing Methods.

For SDIP packages, the longitudinal axis must be parallel to the transport direction of theprinted-circuit board.

These transparent plastic packages are extremely sensitive to reﬂow soldering conditions and muston no account be processed through more than one soldering cycle or subjected to infrared reﬂowsolderingwithpeaktemperatureexceeding217°C±10°Cmeasuredintheatmosphereofthereﬂowoven. The package body peak temperature must be kept as low as possible.

These packages are not suitable for wave soldering. On versions with the heatsink on the bottomside,thesoldercannotpenetratebetweentheprinted-circuitboardandtheheatsink.Onversionswiththe heatsink on the top side, the solder might be deposited on the heatsink surface.

If wave soldering is considered, then the package must be placed at a 45° angle to the solder wavedirection. Thepackage footprint must incorporate solder thieves downstream and at the side corners.Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8mm; itis deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.65mm.

Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than0.65mm; itis deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.5mm.

13.Revision history

Table 28:RevDate03

20030619

Revision history

CPCN-DescriptionProduct data (939775011621). ECN 853-236830033 of 16June2003.Modiﬁcations:

•

0201

2003031420020904

Figure 5 “Crystal oscillator connection.” on page 13: changed capacitors’ values andadded connection with resistor.

Product data (939775011204). ECN 853-236829624 of 07March2003.Product data (939775008831). ECN 853-236828865 of 04September2002.

939775011621

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Dual UART with 16 bytes of transmit and receive FIFOs andIrDA

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14.Data sheet status

LevelIII

Data sheet status[1]Objective dataPreliminary data

Product status[2][3]DevelopmentQualiﬁcation

DeﬁnitionThis data sheet contains data from the objective speciﬁcation for product development. PhilipsSemiconductors reserves the right to change the speciﬁcation in any manner without notice.

Thisdatasheetcontainsdatafromthepreliminaryspeciﬁcation.Supplementarydatawillbepublishedatalaterdate.PhilipsSemiconductorsreservestherighttochangethespeciﬁcationwithoutnotice,inorder to improve the design and supply the best possible product.

This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves therighttomakechangesatanytimeinordertoimprovethedesign,manufacturingandsupply.Relevantchanges will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN).

IIIProduct dataProduction

[1][2][3]

Please consult the most recently issued data sheet before initiating or completing a design.

The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet atURLhttp://www.semiconductors.philips.com.

For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

15.Deﬁnitions

Short-form speciﬁcation —The data in a short-form speciﬁcation isextracted from a full data sheet with the same type number and title. Fordetailed information see the relevant data sheet or data handbook.

Limiting values deﬁnition — Limiting values given are in accordance withthe Absolute Maximum Rating System (IEC60134). Stress above one ormore of the limiting values may cause permanent damage to the device.These are stress ratings only and operation of the device at these or at anyother conditions above those given in the Characteristics sections of thespeciﬁcation is not implied. Exposure to limiting values for extended periodsmay affect device reliability.

Application information — Applications that are described herein for anyof these products are for illustrative purposes only. Philips Semiconductorsmakenorepresentationorwarrantythatsuchapplicationswillbesuitableforthe speciﬁed use without further testing or modiﬁcation.

16.Disclaimers

Life support —These products are not designed for use in life supportappliances, devices, or systems where malfunction of these products canreasonably be expected to result in personal injury. Philips Semiconductorscustomers using or selling these products for use in such applications do soat their own risk and agree to fully indemnify Philips Semiconductors for anydamages resulting from such application.

Right to make changes —Philips Semiconductors reserves the right tomake changes in the products - including circuits, standard cells, and/orsoftware - described or contained herein in order to improve design and/orperformance. When the product is in full production (status ‘Production’),relevant changes will be communicated via a Customer Product/ProcessChange Notiﬁcation (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys nolicence or title under any patent, copyright, or mask work right to these

products,andmakesnorepresentationsorwarrantiesthattheseproductsarefreefrompatent,copyright,ormaskworkrightinfringement,unlessotherwisespeciﬁed.

Contact information

For additional information, please visithttp://www.semiconductors.philips.com.

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939775011621

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Product dataRev. 03 — 19 June 200345 of 46

Philips Semiconductors

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs andIrDA

Contents

1Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Ordering information. . . . . . . . . . . . . . . . . . . . . 24Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 35Pinning information. . . . . . . . . . . . . . . . . . . . . . 45.1Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45.2Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 66Functional description . . . . . . . . . . . . . . . . . . . 96.1UART A-B functions . . . . . . . . . . . . . . . . . . . . . 96.2Internal registers. . . . . . . . . . . . . . . . . . . . . . . 106.3FIFO operation . . . . . . . . . . . . . . . . . . . . . . . . 116.4Hardware ﬂow control. . . . . . . . . . . . . . . . . . . 116.5Software ﬂow control . . . . . . . . . . . . . . . . . . . 116.6Special feature software ﬂow control . . . . . . . 126.7Hardware/software and time-out interrupts. . . 126.8Programmable baud rate generator . . . . . . . . 136.9DMA operation . . . . . . . . . . . . . . . . . . . . . . . . 146.10Loop-back mode. . . . . . . . . . . . . . . . . . . . . . . 147Register descriptions . . . . . . . . . . . . . . . . . . . 167.1Transmit (THR) and Receive (RHR)

Holding Registers . . . . . . . . . . . . . . . . . . . . . 177.2Interrupt Enable Register (IER) . . . . . . . . . . . 177.2.1IER versus Transmit/Receive FIFO interrupt

mode operation . . . . . . . . . . . . . . . . . . . . . . . 187.2.2IER versus Receive/Transmit FIFO polled

mode operation . . . . . . . . . . . . . . . . . . . . . . . 197.3FIFO Control Register (FCR) . . . . . . . . . . . . . 197.3.1DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 197.3.2FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 207.4Interrupt Status Register (ISR). . . . . . . . . . . . 217.5Line Control Register (LCR). . . . . . . . . . . . . . 227.6Modem Control Register (MCR). . . . . . . . . . . 247.7Line Status Register (LSR). . . . . . . . . . . . . . . 257.8Modem Status Register (MSR). . . . . . . . . . . . 267.9Scratchpad Register (SPR) . . . . . . . . . . . . . . 277.10Enhanced Feature Register (EFR). . . . . . . . . 277.11

SC16C2550 external reset condition . . . . . . . 29

Allrightsarereserved.Reproductioninwholeorinpartisprohibitedwithoutthepriorwritten consent of the copyright owner.

Theinformationpresentedinthisdocumentdoesnotformpartofanyquotationorcontract,isbelievedtobeaccurateandreliableandmaybechangedwithoutnotice.Noliabilitywillbeacceptedbythepublisherforanyconsequenceofitsuse.Publicationthereofdoesnotconveynorimplyanylicenseunderpatent-orotherindustrialorintellectual property rights.Date of release: 19 June 2003

Document order number: 939775011621

encoder/decoder

8Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 299Static characteristics . . . . . . . . . . . . . . . . . . . 3010Dynamic characteristics. . . . . . . . . . . . . . . . . 3110.1Timing diagrams. . . . . . . . . . . . . . . . . . . . . . . 3211Package outline. . . . . . . . . . . . . . . . . . . . . . . . 3912Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4212.1Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . 4212.2Through-hole mount packages . . . . . . . . . . . 4212.2.1Soldering by dipping or by solder wave . . . . . 4212.2.2Manual soldering . . . . . . . . . . . . . . . . . . . . . . 4212.3Surface mount packages . . . . . . . . . . . . . . . . 4212.3.1Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 4212.3.2Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 4312.3.3Manual soldering . . . . . . . . . . . . . . . . . . . . . . 4312.4Package related soldering information. . . . . . 4413Revision history . . . . . . . . . . . . . . . . . . . . . . . 4414Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 4515Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4516

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . .

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