专利名称：CMOS cell for logic operations with fast
carry
发明人：Luigi Licciardi,Alessandro Torielli申请号：US07/1865申请日：19880427公开号：US04905179A公开日：19900227
摘要：The elementary adder, as far as carry propagation is concerned, has two circuitbranches: the first is an inverter (II) followed by a transfer gate (T1, T2) activated whentwo operands have opposite logic levels, in which case it transfers complemented inputcarry Cin to the output CoutN; the second consists of a 4-transistor series cirucit, two P-MOS (T3, T4) and two N-MOS (T5, T6) geenrating carry output CoutN complementedwhen the two operands have equal logic levels.
申请人：CSELT - CENTRO STUDI E LABORATORI TELECOMUNICAZIONI S.P.A.
代理人：Herbert Dubno
更多信息请下载全文后查看
因篇幅问题不能全部显示，请点此查看更多更全内容
Copyright © 2019- haog.cn 版权所有 赣ICP备2024042798号-2
违法及侵权请联系：TEL:199 1889 7713 E-MAIL:2724546146@qq.com
本站由北京市万商天勤律师事务所王兴未律师提供法律服务