ADuM1400BRWZ

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Quad-Channel Digital IsolatorsADuM1400/ADuM1401/ADuM1402GENERAL DESCRIPTION

The ADuM140x are 4-channel digital isolators based on Analog Devices’ iCoupler® technology. Combining high speed CMOS and monolithic air core transformer technology, these isolation components provide outstanding performance characteristics superior to alternatives such as optocoupler devices.

By avoiding the use of LEDs and photodiodes, iCoupler devices remove the design difficulties commonly associated with optocouplers. The typical optocoupler concerns regarding uncertain current transfer ratios, nonlinear transfer functions, and temperature and lifetime effects are eliminated with the simple iCoupler digital interfaces and stable performance

characteristics. The need for external drivers and other discretes is eliminated with these iCoupler products. Furthermore,

iCoupler devices consumes one-tenth to one-sixth the power of optocouplers at comparable signal data rates.

The ADuM140x isolators provide four independent isolation channels in a variety of channel configurations and data rates (see the Ordering Guide). All models operate with the supply voltage on either side ranging from 2.7 V to 5.5 V, providing compatibility with lower voltage systems as well as enabling a voltage translation functionality across the isolation barrier. In addition, the ADuM140x provides low pulse-width distortion (<2 ns for CRW grade) and tight channel-to-channel matching (<2 ns for CRW grade). Unlike other optocoupler alternatives, the ADuM140x isolators have a patented refresh feature that ensures dc correctness in the absence of input logic transitions and during power-up/power-down conditions.

FEATURES

Low power operation 5 V operation

1.0 mA per channel max @ 0 Mbps to 2 Mbps 3.5 mA per channel max @ 10 Mbps 31 mA per channel max @ 90 Mbps 3 V operation

0.7 mA per channel max @ 0 Mbps to 2 Mbps 2.1 mA per channel max @ 10 Mbps 20 mA per channel max @ 90 Mbps Bidirectional communication 3 V/5 V level translation

High temperature operation: 105°C High data rate: dc to 90 Mbps (NRZ) Precise timing characteristics

2 ns max pulse-width distortion

2 ns max channel-to-channel matching

High common-mode transient immunity: >25 kV/μs Output enable function

Wide body 16-lead SOIC package, Pb-free models available Safety and regulatory approvals

UL recognition: 2500 V rms for 1 minute per UL 1577 CSA component acceptance notice #5A VDE certificate of conformity

DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01

DIN EN 60950 (VDE 0805): 2001-12; EN 60950: 2000 VIORM = 560 V peak

APPLICATIONS

General-purpose multichannel isolation SPI® interface/data converter isolation RS-232/RS-422/RS-485 transceiver Industrial field bus isolation

FUNCTIONAL BLOCK DIAGRAMS

VDD11GND12VIA3VIB4VIC5VID6NC7GND18ENCODEENCODEENCODEENCODEDECODEDECODEDECODEDECODE16VDD215GND214VOA13VOB12VOC11VOD10VE203786-0-001VDD11GND12VIA3VIB4VIC5VOD6VE17GND18ENCODEENCODEDECODEDECODEDECODEDECODEENCODEENCODE16VDD215GND214VOA13VOB12VOC11VID10VE203786-0-002VDD11GND12VIA3VIB4VOC5VOD6VE17GND18ENCODEENCODEDECODEDECODEDECODEDECODEENCODEENCODE16VDD215GND214VOA13VOB12VIC11VID10VE299GND2

9GND2

GND203786-0-003

Figure 1. ADuM1400 Functional Block Diagram

Figure 2. ADuM1401 Functional Block Diagram Figure 3. ADuM1402 Functional Block Diagram

Rev. B

nformation furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

ADuM1400/ADuM1401/ADuM1402

TABLE OF CONTENTS Specifications.....................................................................................3 Electrical Characteristics—5 V Operation................................3 Electrical Characteristics—3 V Operation................................6 Electrical Characteristics—Mixed 5 V/3 V or 3 V/5 V

Operation.......................................................................................8 Package Characteristics.............................................................12 Regulatory Information.............................................................12 Insulation and Safety-Related Specifications..........................12 DIN EN 60747-5-2 (VDE 0884 Part 2) Insulation

Characteristics............................................................................13 Recommended Operating Conditions....................................13 Absolute Maximum Ratings..........................................................14

ESD Caution................................................................................14 Pin Configurations and Pin Function Descriptions..................15 Typical Performance Characteristics...........................................17 Application Information................................................................19 PC Board Layout........................................................................19 Propagation Delay-Related Parameters...................................19 DC Correctness and Magnetic Field Immunity...........................19 Power Consumption..................................................................20 Outline Dimensions.......................................................................21 Ordering Guide..........................................................................21

REVISION HISTORY

6/04—Data Sheet Changed from Rev. A to Rev. B.

Changes to Format.............................................................Universal Changes to Features..........................................................................1 Changes to Electrical Characteristics—5 V Operation...............3 Changes to Electrical Characteristics—3 V Operation...............5 Changes to Electrical Characteristics—Mixed 5 V/3 V or

3 V/5 V Operation............................................................................7 Changes to DIN EN 60747-5-2 (VDE 0884 Part 2)

Insulation Characteristics Title.....................................................11 Changes to the Ordering Guide....................................................19

5/04—Data Sheet Changed from Rev. 0 to Rev. A.

Updated Format..................................................................Universal Changes to the Features...................................................................1 Changes to Table 7 and Table 8.....................................................14 Changes to Table 9..........................................................................15 Changes to the DC Correctness and Magnetic Field Immunity Section..............................................................................................20 Changes to the Power Consumption Section.............................21 Changes to the Ordering Guide....................................................22 9/03—Revision 0: Initial Version.

Rev. B | Page 2 of 24

ADuM1400/ADuM1401/ADuM1402SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V OPERATION1

4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all min/max specifications apply over the entire recommended operation range, unless other-wise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V. Table 1.

Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current, per Channel, Quiescent IDDI (Q) 0.50 0.53 mA Output Supply Current, per Channel, Quiescent IDDO (Q) 0.19 0.21 mA ADuM1400, Total Supply Current, Four Channels2 DC to 2 Mbps VDD1 Supply Current IDD1 (Q) 2.2 2.8 mA DC to 1 MHz logic signal freq. VDD2 Supply Current IDD2 (Q) 0.9 1.4 mA DC to 1 MHz logic signal freq. 10 Mbps (BRW and CRW Grades Only) VDD1 Supply Current IDD1 (10) 8.6 10.6 mA 5 MHz logic signal freq. VDD2 Supply Current IDD2 (10) 2.6 3.5 mA 5 MHz logic signal freq. 90 Mbps (CRW Grade Only) VDD1 Supply Current IDD1 (90) 76 100 mA 45 MHz logic signal freq. VDD2 Supply Current IDD2 (90) 21 25 mA 45 MHz logic signal freq. ADuM1401, Total Supply Current, Four Channels2 DC to 2 Mbps VDD1 Supply Current IDD1 (Q) 1.8 2.4 mA DC to 1 MHz logic signal freq. VDD2 Supply Current IDD2 (Q) 1.2 1.8 mA DC to 1 MHz logic signal freq. 10 Mbps (BRW and CRW Grades Only) VDD1 Supply Current IDD1 (10) 7.1 9.0 mA 5 MHz logic signal freq. VDD2 Supply Current IDD2 (10) 4.1 5.0 mA 5 MHz logic signal freq. 90 Mbps (CRW Grade Only) VDD1 Supply Current IDD1 (90) 62 82 mA 45 MHz logic signal freq. VDD2 Supply Current IDD2 (90) 35 43 mA 45 MHz logic signal freq.

ADuM1402, Total Supply Current, Four Channels DC to 2 Mbps VDD1 or VDD2 Supply Current IDD1 (Q), IDD2 (Q) 1.5 2.1 mA DC to 1 MHz logic signal freq. 10 Mbps (BRW and CRW Grades Only) VDD1 or VDD2 Supply Current IDD1 (10), IDD2 (10) 5.6 7.0 mA 5 MHz logic signal freq. 90 Mbps (CRW Grade Only) VDD1 or VDD2 Supply Current IDD1 (90), IDD2 (90) 49 62 mA 45 MHz logic signal freq. For All Models Input Currents –10 +0.01+10 µA 0 ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2, IIA, IIB, IIC,

IID, IE1, IE20 ≤ VE1, VE2 ≤ VDD1 or VDD2

Logic High Input ThresholdVIH, VEH2.0 V Logic Low Input Threshold VIL, VEL 0.8 V Logic High Output Voltages 5.0 V IOx = –20 µA, VIx = VIxHVDD1, VOAH, VOBH,

VDD2 – 0.1VOCH, VODH

4.8 V IOx = –4 mA, VIx = VIxHVDD1,

VDD2 – 0.4

Logic Low Output Voltages 0.0 0.1 V IOx = 20 µA, VIx = VIxLVOAL, VOBL,

VOCL, VODL 0.04 0.1 V IOx = 400 µA, VIx = VIxL

0.2 0.4 V IOx = 4 mA, VIx = VIxL

Rev. B | Page 3 of 24

ADuM1400/ADuM1401/ADuM1402

Parameter Symbol Min Typ Max Unit Test Conditions SWITCHING SPECIFICATIONS ADuM140xARW

Minimum Pulse WidthPW 1000ns CL = 15 pF, CMOS signal levels Maximum Data Rate4 1 Mbps CL = 15 pF, CMOS signal levels

Propagation DelaytPHL, tPLH50 65 100 ns CL = 15 pF, CMOS signal levels Pulse-Width Distortion, |tPLH – tPHL|5 PWD 40 ns CL = 15 pF, CMOS signal levels

Propagation Delay SkewtPSK 50 ns CL = 15 pF, CMOS signal levels

Channel-to-Channel MatchingtPSKCD/OD 50 ns CL = 15 pF, CMOS signal levels ADuM140xBRW

Minimum Pulse Width PW 100 ns CL = 15 pF, CMOS signal levels Maximum Data Rate4 10 Mbps CL = 15 pF, CMOS signal levels

Propagation Delay tPHL, tPLH20 32 50 ns CL = 15 pF, CMOS signal levels Pulse-Width Distortion, |tPLH – tPHL|5 PWD 3 ns CL = 15 pF, CMOS signal levels Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels

Propagation Delay Skew tPSK 15 ns CL = 15 pF, CMOS signal levels

3 ns CL = 15 pF, CMOS signal levels tPSKCDChannel-to-Channel Matching,

Codirectional Channels

tPSKOD 6 ns CL = 15 pF, CMOS signal levels Channel-to-Channel Matching,

Opposing-Directional Channels

ADuM140xCRW Minimum Pulse Width3 PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels

Maximum Data Rate 90 120 Mbps CL = 15 pF, CMOS signal levels

Propagation Delay tPHL, tPLH18 27 32 ns CL = 15 pF, CMOS signal levels Pulse-Width Distortion, |tPLH – tPHL|5 PWD 0.5 2 ns CL = 15 pF, CMOS signal levels Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew6 tPSK 10 ns CL = 15 pF, CMOS signal levels

2 ns CL = 15 pF, CMOS signal levels tPSKCDChannel-to-Channel Matching,

Codirectional Channels

tPSKOD 5 ns CL = 15 pF, CMOS signal levels Channel-to-Channel Matching,

Opposing-Directional Channels For All Models

tPHZ, tPLH 6 8 ns CL = 15 pF, CMOS signal levels Output Disable Propagation Delay

(High/Low-to-High Impedance)

6 8 ns CL = 15 pF, CMOS signal levels tPZH, tPZLOutput Enable Propagation Delay

(High Impedance to High/Low) Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels

|CMH| 25 35 kV/µs Common-Mode Transient Immunity VIx = VDD1/VDD2, VCM = 1000 V,

at Logic High Outputtransient magnitude = 800 V

|CML| 25 35 kV/µs Common-Mode Transient Immunity VIx = 0 V, VCM = 1000 V,

at Logic Low Output8 transient magnitude = 800 V Refresh Rate fr 1.2 Mbps

Input Dynamic Supply Current, per ChannelIDDI (D) 0.19 mA/Mbps Output Dynamic Supply Current, per Channel9 IDDO (D) 0.05 mA/Mbps

See Notes on next page.

Rev. B | Page 4 of 24

ADuM1400/ADuM1401/ADuM1402 All voltages are relative to their respective ground.

The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section on Page 20. See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 14 for total IDD1 and IDD2 supply currents as a function of data rate for ADuM1400/ADuM1401/ADuM1402 channel configurations. 3

The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed. 4

The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed. 5

tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 6

tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 7

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 8

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 9

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section on Page 20 for guidance on calculating the per-channel sup-ply current for a given data rate.

Rev. B | Page 5 of 24

ADuM1400/ADuM1401/ADuM1402

ELECTRICAL CHARACTERISTICS—3 V OPERATION1

2.7 V ≤ VDD1 ≤ 3.6 V, 2.7 V ≤ VDD2 ≤ 3.6 V; all min/max specifications apply over the entire recommended operation range, unless other-wise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V. Table 2.

Parameter Symbol Min Typ MaxUnit Test Conditions DC SPECIFICATIONS Input Supply Current, per Channel, Quiescent IDDI (Q) 0.26 0.31 mA Output Supply Current, per Channel, Quiescent IDDO (Q) 0.11 0.14 mA

ADuM1400, Total Supply Current, Four Channels DC to 2 Mbps VDD1 Supply Current IDD1 (Q) 1.2 1.9 mA DC to 1 MHz logic signal freq. VDD2 Supply Current IDD2 (Q) 0.5 0.9 mA DC to 1 MHz logic signal freq. 10 Mbps (BRW and CRW Grades Only) VDD1 Supply Current IDD1 (10) 4.5 6.5 mA 5 MHz logic signal freq. VDD2 Supply Current IDD2 (10) 1.4 2.0 mA 5 MHz logic signal freq. 90 Mbps (CRW Grade Only) VDD1 Supply Current IDD1 (90) 42 65 mA 45 MHz logic signal freq. VDD2 Supply Current IDD2 (90) 11 15 mA 45 MHz logic signal freq. ADuM1401, Total Supply Current, Four Channels2 DC to 2 Mbps VDD1 Supply Current IDD1 (Q) 1.0 1.6 mA DC to 1 MHz logic signal freq. VDD2 Supply Current IDD2 (Q) 0.7 1.2 mA DC to 1 MHz logic signal freq. 10 Mbps (BRW and CRW Grades Only) VDD1 Supply Current IDD1 (10) 3.7 5.4 mA 5 MHz logic signal freq. VDD2 Supply Current IDD2 (10) 2.2 3.0 mA 5 MHz logic signal freq. 90 Mbps (CRW Grade Only) VDD1 Supply Current IDD1 (90) 34 52 mA 45 MHz logic signal freq. VDD2 Supply Current IDD2 (90) 19 27 mA 45 MHz logic signal freq. ADuM1402, Total Supply Current, Four Channels2 DC to 2 Mbps VDD1 or VDD2 Supply Current IDD1 (Q), IDD2 (Q) 0.9 1.5 mA DC to 1 MHz logic signal freq. 10 Mbps (BRW and CRW Grades Only) VDD1 or VDD2 Supply Current IDD1 (10), IDD2 (10) 3.0 4.2 mA 5 MHz logic signal freq. 90 Mbps (CRW Grade Only) VDD1 or VDD2 Supply Current IDD1 (90), IDD2 (90) 27 39 mA 45 MHz logic signal freq. For All Models Input Currents –10 +0.01+10 µA IIA, IIB, IIC, 0 ≤ VIA, VIB, VIC, VID ≤ VDD1 or

IID, IE1, IE2VDD2, 0 ≤ VE1,VE2 ≤ VDD1 or VDD2

Logic High Input Threshold VIH, VEH1.6 V

Logic Low Input ThresholdVIL, VEL 0.4 V Logic High Output Voltages VDD1, VDD2 – 0.1 3.0 V IOx = –20 µA, VIx = VIxHVOAH, VOBH,

VOCH, VODHVDD1, VDD2 – 0.4 2.8 V IOx = –4 mA, VIx = VIxH

Logic Low Output Voltages 0.0 0.1 V IOx = 20 µA, VIx = VIxLVOAL, VOBL,

VOCL, VODL 0.04 0.1 V IOx = 400 µA, VIx = VIxL

0.2 0.4 V IOx = 4 mA, VIx = VIxL

SWITCHING SPECIFICATIONS ADuM140xARW Minimum Pulse Width3PW 1000ns CL = 15 pF, CMOS signal levels

Maximum Data Rate 1 Mbps CL = 15 pF, CMOS signal levels Propagation Delay5tPHL, tPLH50 75 100 ns CL = 15 pF, CMOS signal levels

Pulse-Width Distortion, |tPLH – tPHL|PWD 40 ns CL = 15 pF, CMOS signal levels

Propagation Delay SkewtPSK 50 ns CL = 15 pF, CMOS signal levels Channel-to-Channel Matching7tPSKCD/OD 50 ns CL = 15 pF, CMOS signal levels

Rev. B | Page 6 of 24

ADuM1400/ADuM1401/ADuM1402Parameter Symbol Min Typ MaxUnit Test Conditions ADuM140xBRW Minimum Pulse Width3 PW 100 ns CL = 15 pF, CMOS signal levels

Maximum Data Rate 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay5 tPHL, tPLH20 38 50 ns CL = 15 pF, CMOS signal levels

Pulse-Width Distortion, |tPLH – tPHL|PWD 3 ns CL = 15 pF, CMOS signal levels Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels

Propagation Delay Skew tPSK 22 ns CL = 15 pF, CMOS signal levels

3 ns CL = 15 pF, CMOS signal levels tPSKCDChannel-to-Channel Matching,

Codirectional Channels

tPSKOD 6 ns CL = 15 pF, CMOS signal levels Channel-to-Channel Matching,

Opposing-Directional Channels7

ADuM140xCRW

Minimum Pulse Width PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels Maximum Data Rate4 90 120 Mbps CL = 15 pF, CMOS signal levels

Propagation Delay tPHL, tPLH20 34 45 ns CL = 15 pF, CMOS signal levels

Pulse-Width Distortion, |tPLH – tPHL|PWD 0.5 2 ns CL = 15 pF, CMOS signal levels Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels

Propagation Delay Skew tPSK 16 ns CL = 15 pF, CMOS signal levels

2 ns CL = 15 pF, CMOS signal levels tPSKCDChannel-to-Channel Matching,

Codirectional Channels

5 ns CL = 15 pF, CMOS signal levels tPSKODChannel-to-Channel Matching,

Opposing-Directional Channels For All Models

6 8 ns CL = 15 pF, CMOS signal levels tPHZ, tPLHOutput Disable Propagation Delay

(High/Low-to-High Impedance)

6 8 ns CL = 15 pF, CMOS signal levels tPZH, tPZLOutput Enable Propagation Delay

(High Impedance to High/Low) Output Rise/Fall Time (10% to 90%) tR/tF 3 ns CL = 15 pF, CMOS signal levels

|CMH| 25 35 kV/µs Common-Mode Transient Immunity VIx = VDD1/VDD2, VCM = 1000 V,

at Logic High Output8transient magnitude = 800 V

|CML| 25 35 kV/µs Common-Mode Transient Immunity VIx = 0 V, VCM = 1000 V,

at Logic Low Outputtransient magnitude = 800 V Refresh Rate fr 1.1 Mbps Input Dynamic Supply Current, per Channel9IDDI (D) 0.10 mA/Mbps

Output Dynamic Supply Current, per Channel IDDO (D) 0.03 mA/Mbps

All voltages are relative to their respective ground.

The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load

The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed. 4

The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed. 5

Rev. B | Page 7 of 24

ADuM1400/ADuM1401/ADuM1402

ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V OPERATION1

5 V/3 V operation: 4.5 V ≤ VDD1 ≤ 5.5 V, 2.7 V ≤ VDD2 ≤ 3.6 V; 3 V/5 V operation: 2.7 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all min/max specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25°C; VDD1 = 3.0 V, VDD2 = 5 V; or VDD1 = 5 V, VDD2 = 3.0 V. Table 3.

Parameter Symbol Min Typ MaxUnit Test Conditions DC SPECIFICATIONS Input Supply Current, per Channel, Quiescent IDDI (Q) 5 V/3 V Operation 0.50 0.53 mA 3 V/5 V Operation 0.26 0.31 mA Output Supply Current, per Channel, Quiescent IDDO (Q) 5 V/3 V Operation 0.11 0.14 mA 3 V/5 V Operation 0.19 0.21 mA

ADuM1400, Total Supply Current, Four Channels DC to 2 Mbps VDD1 Supply Current IDD1 (Q) 5 V/3 V Operation 2.2 2.8 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 1.2 1.9 mA DC to 1 MHz logic signal freq. VDD2 Supply Current IDD2 (Q) 5 V/3 V Operation 0.5 0.9 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 0.9 1.4 mA DC to 1 MHz logic signal freq. 10 Mbps (BRW and CRW Grades Only) VDD1 Supply Current IDD1 (10) 5 V/3 V Operation 8.6 10.6 mA 5 MHz logic signal freq. 3 V/5 V Operation 4.5 6.5 mA 5 MHz logic signal freq. VDD2 Supply Current IDD2 (10) 5 V/3 V Operation 1.4 2.0 mA 5 MHz logic signal freq. 3 V/5 V Operation 2.6 3.5 mA 5 MHz logic signal freq. 90 Mbps (CRW Grade Only) VDD1 Supply Current IDD1 (90) 5 V/3 V Operation 76 100 mA 45 MHz logic signal freq. 3 V/5 V Operation 42 65 mA 45 MHz logic signal freq. VDD2 Supply Current IDD2 (90) 5 V/3 V Operation 11 15 mA 45 MHz logic signal freq. 3 V/5 V Operation 21 25 mA 45 MHz logic signal freq. ADuM1401, Total Supply Current, Four Channels2 DC to 2 Mbps VDD1 Supply Current IDD1 (Q) 5 V/3 V Operation 1.8 2.4 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 1.0 1.6 mA DC to 1 MHz logic signal freq. VDD2 Supply Current IDD2 (Q) 5 V/3 V Operation 0.7 1.2 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 1.2 1.8 mA DC to 1 MHz logic signal freq. 10 Mbps (BRW and CRW Grades Only) VDD1 Supply Current IDD1 (10) 5 V/3 V Operation 7.1 9.0 mA 5 MHz logic signal freq. 3 V/5 V Operation 3.7 5.4 mA 5 MHz logic signal freq. VDD2 Supply Current IDD2 (10) 5 V/3 V Operation 2.2 3.0 mA 5 MHz logic signal freq. 3 V/5 V Operation 4.1 5.0 mA 5 MHz logic signal freq.

Rev. B | Page 8 of 24

ADuM1400/ADuM1401/ADuM1402Parameter Symbol Min Typ MaxUnit Test Conditions

90 Mbps (CRW Grade Only) VDD1 Supply Current IDD1 (90) 5 V/3 V Operation 62 82 mA 45 MHz logic signal freq. 3 V/5 V Operation 34 52 mA 45 MHz logic signal freq. VDD2 Supply Current IDD2 (90) 5 V/3 V Operation 19 27 mA 45 MHz logic signal freq. 3 V/5 V Operation 35 43 mA 45 MHz logic signal freq.

ADuM1402, Total Supply Current, Four Channels DC to 2 Mbps VDD1 Supply Current IDD1 (Q) 5 V/3 V Operation 1.5 2.1 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 0.9 1.5 mA DC to 1 MHz logic signal freq. VDD2 Supply Current IDD2 (Q) 5 V/3 V Operation 0.9 1.5 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 1.5 2.1 mA DC to 1 MHz logic signal freq. 10 Mbps (BRW and CRW Grades Only) VDD1 Supply Current IDD1 (10) 5 V/3 V Operation 5.6 7.0 mA 5 MHz logic signal freq. 3 V/5 V Operation 3.0 4.2 mA 5 MHz logic signal freq. VDD2 Supply Current IDD2 (10) 5 V/3 V Operation 3.0 4.2 mA 5 MHz logic signal freq. 3 V/5 V Operation 5.6 7.0 mA 5 MHz logic signal freq. 90 Mbps (CRW Grade Only) VDD1 Supply Current IDD1 (90) 5 V/3 V Operation 49 62 mA 45 MHz logic signal freq. 3 V/5 V Operation 27 39 mA 45 MHz logic signal freq. VDD2 Supply Current IDD2 (90) 5 V/3 V Operation 27 39 mA 45 MHz logic signal freq. 3 V/5 V Operation 49 62 mA 45 MHz logic signal freq. For All Models Input Currents –10 +0.01 +10 µA IIA, IIB, IIC, 0 ≤ VIA,VIB, VIC,VID ≤ VDD1 or

IID, IE1, IE2VDD2, 0 ≤ VE1,VE2 ≤ VDD1 or VDD2

Logic High Input ThresholdVIH, VEH 5 V/3 V Operation 2.0 V 3 V/5 V Operation 1.6 V

Logic Low Input ThresholdVIL, VEL 5 V/3 V Operation 0.8 V 3 V/5 V Operation 0.4 V Logic High Output Voltages V IOx = –20 µA, VIx = VIxHVDD1/VDD2VDD1/ VOAH, VOBH,

VOCH, VODHVDD2 – 0.1

V IOx = –4 mA, VIx = VIxHVDD1/ VDD1/

VDD2 – 0.4 VDD2 – 0.2

Logic Low Output Voltages 0.0 0.1 V IOx = 20 µA, VIx = VIxLVOAL, VOBL,

VOCL, VODL 0.04 0.1 V IOx = 400 µA, VIx = VIxL

0.2 0.4 V IOx = 4 mA, VIx = VIxL

SWITCHING SPECIFICATIONS ADuM140xARW Minimum Pulse Width3PW 1000ns CL = 15 pF, CMOS signal levels

Maximum Data Rate 1 Mbps CL = 15 pF, CMOS signal levelsPropagation Delay5tPHL, tPLH50 70 100 ns CL = 15 pF, CMOS signal levels

Pulse-Width Distortion, |tPLH – tPHL|PWD 40 ns CL = 15 pF, CMOS signal levelsPropagation Delay Skew6tPSK 50 ns CL = 15 pF, CMOS signal levels

Channel-to-Channel MatchingtPSKCD/OD 50 ns CL = 15 pF, CMOS signal levels

Rev. B | Page 9 of 24

ADuM1400/ADuM1401/ADuM1402

Parameter Symbol Min Typ MaxUnit Test Conditions ADuM140xBRW Minimum Pulse Width3PW 100 ns CL = 15 pF,CMOS signal levels

Maximum Data Rate 10 Mbps CL = 15 pF, CMOS signal levelsPropagation Delay5 tPHL, tPLH15 35 50 ns CL = 15 pF, CMOS signal levels

Pulse-Width Distortion, |tPLH – tPHL|PWD 3 ns CL = 15 pF, CMOS signal levelsChange vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels

Propagation Delay SkewtPSK 22 ns CL = 15 pF, CMOS signal levels

3 ns CL = 15 pF, CMOS signal levelstPSKCDChannel-to-Channel Matching,

Codirectional Channels

tPSKOD 6 ns CL = 15 pF, CMOS signal levelsChannel-to-Channel Matching,

Opposing-Directional Channels7

ADuM140xCRW

Minimum Pulse Width PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels

CL = 15 pF, CMOS signal levelsMaximum Data Rate4 90 120 Mbps 5

Propagation Delay tPHL, tPLH20 30 40 ns CL = 15 pF, CMOS signal levels

Pulse-Width Distortion, |tPLH – tPHL|PWD 0.5 2 ns CL = 15 pF, CMOS signal levelsChange vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels

Propagation Delay Skew tPSK 14 ns CL = 15 pF, CMOS signal levels

2 ns CL = 15 pF, CMOS signal levelstPSKCDChannel-to-Channel Matching,

Codirectional Channels

5 ns CL = 15 pF, CMOS signal levelstPSKODChannel-to-Channel Matching,

Opposing-Directional Channels For All Models

6 8 ns CL = 15 pF, CMOS signal levelstPHZ, tPLHOutput Disable Propagation Delay

(High/Low to High Impedance)

6 8 ns CL = 15 pF, CMOS signal levelstPZH, tPZLOutput Enable Propagation Delay

(High Impedance to High/Low) Output Rise/Fall Time (10% to 90%) tR/tf CL = 15 pF, CMOS signal levels5 V/3 V Operation 3.0 ns 3 V/5 V Operation 2.5 ns

|CMH| 25 35 kV/µs Common-Mode Transient Immunity VIx = VDD1/VDD2, VCM = 1000 V,

at Logic High Outputtransient magnitude = 800 V

|CML| 25 35 kV/µs Common-Mode Transient Immunity VIx = 0 V, VCM = 1000 V,

at Logic Low Outputtransient magnitude = 800 VRefresh Rate fr 5 V/3 V Operation 1.2 Mbps 3 V/5 V Operation 1.1 Mbps

Input Dynamic Supply Current, per ChannelIDDI (D) 5 V/3 V Operation 0.19 mA/Mbps 3 V/5 V Operation 0.10 mA/Mbps Output Dynamic Supply Current, per Channel9 IDDI (D) 5 V/3 V Operation 0.03 mA/Mbps 3 V/5 V Operation 0.05 mA/Mbps

See Notes on next page.

Rev. B | Page 10 of 24

ADuM1400/ADuM1401/ADuM1402 All voltages are relative to their respective ground.

The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section on Page 20. See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 14 for total IDD1 and IDD2 supply currents as a function of data rate for ADuM1400/ADuM1401/ADuM1402 channel configurations. 3

The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed. 4

The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed. 5

Rev. B | Page 11 of 24

ADuM1400/ADuM1401/ADuM1402

PACKAGE CHARACTERISTICS

Table 4.

Parameter Symbol Min Typ Max Unit Test Conditions Resistance (Input-Output)1RI-O 1012 Ω Capacitance (Input-Output)1 CI-O 2.2 pF f = 1 MHz

Input CapacitanceCI 4.0 p IC Junction-to-Case Thermal Resistance, Side 1 θJCI 33 °C/W Thermocouple located

at center of package IC Junction-to-Case Thermal Resistance, Side 2 θJCO 28 °C/W underside

Device considered a 2-terminal device; Pins 1, 2, 3, 4, 5, 6, 7, and 8 shorted together and Pins 9, 10, 11, 12, 13, 14, 15, and 16 shorted together. Input capacitance is from any input data pin to ground.

REGULATORY INFORMATION

The ADuM140x have been approved by the organizations listed in Table 5. Table 5.

UL1

Recognized under 1577

component recognition program1

Double insulation, 2500 V rms isolation voltage

File E214100

CSA VDE2Approved under CSA Component Certified according to DIN EN 60747-5-2 Acceptance Notice #5A (VDE 0884 Part 2): 2003-012

Basic insulation, 560 V peak Reinforced insulation per

CSA 60950-1-03 and IEC 60950-1,

400 V rms maximum working voltage Complies with DIN EN 60747-5-2 (VDE 0884 Part 2): 2003- 01, DIN EN 60950 (VDE 0805): 2001-12; EN 60950:2000 Reinforced insulation, 560 V peak File 205078 File 2471900-4880-0001

In accordance with UL1577, each ADuM140x is proof tested by applying an insulation test voltage ≥ 3000 V rms for 1 second (current leakage detection limit = 5 µA).

In accordance with DIN EN 60747-5-2, each ADuM140x is proof tested by applying an insulation test voltage ≥ 1050 V peak for 1 second (partial discharge detection limit = 5 pC). A “*” mark branded on the component designates DIN EN 60747-5-2 approval.

INSULATION AND SAFETY-RELATED SPECIFICATIONS

Table 6.

Parameter Symbol Value Unit Conditions Rated Dielectric Insulation Voltage 2500 V rms 1 minute duration Minimum External Air Gap (Clearance) L(I01) 8.40 min mm Measured from input terminals to output terminals,

shortest distance through air

Minimum External Tracking (Creepage) L(I02) 8.10 min mm Measured from input terminals to output terminals,

shortest distance path along body

Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1 Isolation Group IIIa Material Group (DIN VDE 0110, 1/, Table 1)

Rev. B | Page 12 of 24

ADuM1400/ADuM1401/ADuM1402

DIN EN 60747-5-2 (VDE 0884 PART 2) INSULATION CHARACTERISTICS

Table 7.

Description Symbol Characteristic Unit

Installation Classification per DIN VDE 0110

I–IV For Rated Mains Voltage ≤ 150 V rms

I–III For Rated Mains Voltage ≤ 300 V rms

I–II For Rated Mains Voltage ≤ 400 V rms

Climatic Classification 40/105/21 Pollution Degree (DIN VDE 0110, Table 1) 2 Maximum Working Insulation Voltage VIORM560 V peak Input to Output Test Voltage, Method b1 1050 V peak VPR

VIORM × 1.875 = VPR, 100% Production Test, tm = 1 sec, Partial Discharge < 5 pC Input to Output Test Voltage, Method a VPR

After Environmental Tests Subgroup 1

V peak 6 VIORM × 1.6 = VPR, tm = 60 sec, Partial Discharge < 5 pC

After Input and/or Safety Test Subgroup 2/3 V peak 672 VIORM × 1.2 = VPR, tm = 60 sec, Partial Discharge < 5 pC

Highest Allowable Overvoltage (Transient Overvoltage, tTR = 10 sec) VTR4000 V peak

Safety-Limiting Values (Maximum value allowed in the event of a failure; also see Thermal Derating Curve, Figure 4) TS °C Case Temperature 150

mA Side 1 Current 265 IS1

mA Side 2 Current 335 IS2

Insulation Resistance at TS, VIO = 500 V RS>109Ω

This isolator is suitable for basic electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by protec-tive circuits.

The * marking on packages denotes DIN EN 60747-5-2 approval for 560 V peak working voltage.

350300SAFETY-LIMITING CURRENT (mA)RECOMMENDED OPERATING CONDITIONS

Table 8.

SIDE #2250200150SIDE #110050003787-0-003Parameter Symbol Min Max Unit

Operating Temperature TA–40 +105 °C

Supply VoltagesVDD1, VDD 22.7 5.5 V Input Signal Rise and Fall Times 1.0 ms

050100150CASE TEMPERATURE (°C)200

All voltages are relative to their respective ground.

See the DC Correctness and Magnetic Field Immunity section on Page 19 for information on immunity to external magnetic fields.

Figure 4. Thermal Derating Curve, Dependence of Safety Limiting Values

with Case Temperature per DIN EN 60747-5-2

Rev. B | Page 13 of 24

ADuM1400/ADuM1401/ADuM1402

ABSOLUTE MAXIMUM RATINGS

Ambient temperature = 25°C, unless otherwise noted. Table 9.

Parameter Symbol Min Max Unit Storage Temperature TST–65 +150 °C Ambient Operating Temperature TA–40 +105 °C Supply Voltages1VDD1, VDD2–0.5 +7.0 V

1, 2

Input VoltageVIA, VIB, VIC, VID, VE1,VE2–0.5 VDDI + 0.5 V

1, 2

Output VoltageVOA, VOB, VOC, VOD–0.5 VDDO + 0.5 V Average Output Current, Per Pin3 Side 1 IO1–18 +18 mA Side 2 IO2–22 +22 mA

Common-Mode Transients –100 +100 kV/µs

All voltages are relative to their respective ground.

VDDI and VDDO refer to the supply voltages on the input and output sides of a given channel, respectively. See the PC Board Layout section. 3

See Figure 4 for maximum rated current values for various temperatures. 4

Refers to common-mode transients across the insulation barrier. Common-mode transients exceeding the Absolute Maximum Rating may cause latch-up or perma-nent damage.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Table 10. Truth Table (Positive Logic) VIX Input1H L X X VDDI State1 VDDO State1 VOX Output1 Notes Powered Powered H Powered Powered L Powered Powered Z Unpowered Powered H Outputs return to the input state within 1 µs of VDDI power restoration. X L Unpowered Powered Z X X Powered Unpowered IndeterminateOutputs return to the input state within 1 µs of VDDO power restoration if VEX state is H or NC. Outputs returns to high impedance state within 8 ns of VDDO power restoration if VEX state is L. VEX Input2H or NC H or NC L H or NC VIX and VOX refer to the input and output signals of a given channel (A, B, C, or D). VEX refers to the output enable signal on the same side as the VOX outputs. VDDI and VDDO refer to the supply voltages on the input and output sides of the given channel, respectively. 2 In noisy environments, connecting VEX to an external logic high or low is recommended. 1 Rev. B | Page 14 of 24

ADuM1400/ADuM1401/ADuM1402PIN CONFIGURATIONS AND PIN FUNCTION DESCRIPTIONS

VDD1116VDD2VDD1116VDD2VDD1116VDD2*GND12ADuM140015GND2*VIA3TOP VIEW14VOAVIB4(Not to Scale)13VOBVIC5VID6NC7*GND181211109*GND12ADuM140115GND2*VIA3TOP VIEW14VOAVIB4(Not to Scale)13VOBVIC5VOD603786-0-005*GND12ADuM140215GND2*VIA3TOP VIEW14VOAVIB4(Not to Scale)13VOBVOC5VOD603786-0-006VOCVODVE2GND2*1211109VOCVIDVE2GND2*1211109VICVIDGND2*03786-0-007VE17*GND18VE17*GND18VE2NC = NO CONNECT

Figure 5. ADuM1400 Pin Configuration

Figure 6. ADuM1401 Pin Configuration

Figure 7. ADuM1402 Pin Configuration

* Pins 2 and 8 are internally connected. Connecting both to GND1 is recommended. Pins 9 and 15 are internally connected. Connecting both to GND2 is recommended. Output enable Pin 10 on the ADuM1400 may be left disconnected if outputs are to be always enabled. Output enable Pins 7 and 10 on the ADuM1401/ADuM1402 may be left disconnected if outputs are to be always enabled. In noisy environments, connecting Pin 7 (for ADuM1401 and ADuM1402) and Pin 10 (for all models) to an external logic high or low is recommended.

Table 11. ADuM1400 Pin Function Descriptions

No. Mnemonic Function 1 VDD1Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V. 2 GND1Ground 1. Ground reference for isolator Side 1. 3 VIALogic Input A. 4 VIBLogic Input B. 5 VICLogic Input C. 6 VIDLogic Input D. 7 NC No Connect. 8 GND1Ground 1. Ground reference for isolator Side 1. 9 GND2Ground 2. Ground reference for isolator Side 2. 10 VE2Output Enable 2. Active high logic input. VOA, VOB, VOC, and VOD outputs are enabled when VE2 is high or disconnected. VOA, VOB, VOC, and

VOD outputs are disabled when VE2 is low. In noisy environments, connecting VE2 to an external logic high or low is recommended.

11 VODLogic Output D. 12 VOCLogic Output C. 13 VOBLogic Output B. 14 VOALogic Output A. 15 GND2Ground 2. Ground reference for isolator Side 2. 16 VDD2Supply Voltage for Isolator Side 2, 2.7 V to 5.5 V.

Rev. B | Page 15 of 24

ADuM1400/ADuM1401/ADuM1402

Table 12. ADuM1401 Pin Function Descriptions

No. Mnemonic Function 1 VDD1Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V. 2 GND1Ground 1. Ground reference for isolator Side 1. 3 VIALogic Input A. 4 VIBLogic Input B. 5 VICLogic Input C. 6 VODLogic Output D. 7 VE1Output Enable 1. Active high logic input. VOD output is enabled when VE1 is high or disconnected. VOD is disabled when VE1 is low. In

noisy environments, connecting VE1 to an external logic high or low is recommended.

8 GND1Ground 1. Ground reference for isolator Side 1. 9 GND2Ground 2. Ground reference for isolator Side 2. 10 VE2Output Enable 2. Active high logic input. VOA, VOB, and VOC outputs are enabled when VE2 is high or disconnected. VOA, VOB, and VOC

outputs are disabled when VE2 is low. In noisy environments, connecting VE2 to an external logic high or low is recommended.

11 VIDLogic Input D. 12 VOCLogic Output C. 13 VOBLogic Output B. 14 VOALogic Output A. 15 GND2Ground 2. Ground reference for isolator Side 2. 16 VDD2Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V.

Table 13. ADuM1402 Pin Function Descriptions

No. Mnemonic Function 1 VDD1Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V. 2 GND1Ground 1. Ground reference for isolator Side 1. 3 VIALogic Input A. 4 VIBLogic Input B. 5 VOCLogic Output C. 6 VODLogic Output D. 7 VE1Output Enable 1. Active high logic input. VOC and VOD outputs are enabled when VE1 is high or disconnected. VOC and VOD outputs are

disabled when VE1 is low. In noisy environments, connecting VE1 to an external logic high or low is recommended.

8 GND1Ground 1. Ground reference for isolator Side 1. 9 GND2Ground 2. Ground reference for isolator Side 2. 10 VE2Output Enable 2. Active high logic input. VOA and VOB outputs are enabled when VE2 is high or disconnected. VOA and VOB outputs are

disabled when VE2 is low. In noisy environments, connecting VE2 to an external logic high or low is recommended.

11 VIDLogic Input D. 12 VICLogic Input C. 13 VOBLogic Output B. 14 VOALogic Output A. 15 GND2Ground 2. Ground Reference for Isolator Side 2. 16 VDD2Supply Voltage for Isolator Side 2, 2.7 V to 5.5 V.

Rev. B | Page 16 of 24

ADuM1400/ADuM1401/ADuM1402TYPICAL PERFORMANCE CHARACTERISTICS

20807015CURRENT (mA)CURRENT/CHANNEL (mA)60504030201004407-0-011105V53V5V3V00204060DATA RATE (Mbps)801000020

4060DATA RATE (Mbps)8010004407-0-01404407-0-01504407-0-016

Figure 8. Typical Input Supply Current per Channel vs. Data Rate

for 5 V and 3 V Operation

6Figure 11. Typical ADuM1400 VDD1 Supply Current vs. Data Rate

for 5 V and 3 V Operation

205CURRENT/CHANNEL (mA)1CURRENT (mA)1035V23V1105V3V500204060DATA RATE (Mbps)8010004407-0-0120020

4060DATA RATE (Mbps)80100

Figure 9. Typical Output Supply Current per Channel vs. Data Rate

for 5 V and 3 V Operation (No Output Load)

10Figure 12. Typical ADuM1400 VDD2 Supply Current vs. Data Rate

for 5 V and 3 V Operation

50308CURRENT/CHANNEL (mA)256CURRENT (mA)20155V1045V23V3V500204060DATA RATE (Mbps)8010004407-0-0130020

4060DATA RATE (Mbps)80100

Figure 10. Typical Output Supply Current per Channel vs. Data Rate

for 5 V and 3 V Operation (15 pF Output Load) Figure 13. Typical ADuM1401 VDD1 Supply Current vs. Data Rate

for 5 V and 3 V Operation

Rev. B | Page 17 of 24

ADuM1400/ADuM1401/ADuM1402

403530)ns( )A25AYmL( DET N20NEOR5VITR15AUGCA103VOPRP50710-0204060801000-70DATA RATE (Mbps)440

Figure 14. Typical ADuM1401 VDD2 Supply Current vs. Data Rate

for 5 V and 3 V Operation

504035)Am30( TN25RER20UC5V153V1050810-0204060801000-70DATA RATE (Mbps)440

Figure 15. Typical ADuM1402 VDD1 or VDD2 Supply Current vs.

Data Rate for 5 V and 3 V Operation

Rev. B | Page 18 of 24

403V35305V25320–50–250255075100-0-6TEMPERATURE (°C)8730Figure 16. Propagation Delay vs. Temperature, C Grade

ADuM1400/ADuM1401/ADuM1402DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY

Positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder via the transformer. The decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. In the absence of logic transitions at the input for more than 2 µs, a periodic set of refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output. If the decoder receives no internal pulses of more than about 5 µs, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a default state (see Table 10) by the watchdog timer circuit.

The limitation on the ADuM140x’s magnetic field immunity is set by the condition in which induced voltage in the transformer’s receiving coil is sufficiently large to either falsely set or reset the decoder. The following analysis defines the conditions under which this may occur. The 3 V operating condition of the ADuM140x is examined because it represents the most susceptible mode of operation.

The pulses at the transformer output have an amplitude greater than 1.0 V. The decoder has a sensing threshold at about 0.5 V, therefore establishing a 0.5 V margin in which induced voltages can be toler-ated. The voltage induced across the receiving coil is given by

V = (–dβ/dt)∑∏rn2; n = 1, 2,…, N where:

β is magnetic flux density (gauss).

N is the number of turns in the receiving coil.

rn is the radius of the nth turn in the receiving coil (cm). Given the geometry of the receiving coil in the ADuM140x and an imposed requirement that the induced voltage be at most 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated as shown in Figure 19.

100.00003786-0-020APPLICATION INFORMATION

PC BOARD LAYOUT

The ADuM140x digital isolator requires no external interface circuitry for the logic interfaces. Power supply bypassing is strongly recommended at the input and output supply pins (Figure 17). Bypass capacitors are most conveniently connected between Pins 1 and 2 for VDD1 and between Pins 15 and 16 for VDD2. The capacitor value should be between 0.01 µF and 0.1 µF. The total lead length between both ends of the capacitor and the input power supply pin should not exceed 20 mm. Bypass-ing between Pins 1 and 8 and between Pins 9 and 16 should also be considered unless the ground pair on each package side is connected close to the package.

VDD1GND1VIAVIBVIC/OCVID/ODVE1GND1VDD2GND2VOAVOBVOC/ICVOD/IDVE2GND203786-0-019

Figure 17. Recommended Printed Circuit Board Layout

In applications involving high common-mode transients, care should be taken to ensure that board coupling across the isola-tion barrier is minimized. Furthermore, the board layout should be designed such that any coupling that does occur equally affects all pins on a given component side. Failure to ensure this could cause voltage differentials between pins exceeding the device’s Absolute Maximum Ratings, thereby leading to latch-up or permanent damage.

PROPAGATION DELAY-RELATED PARAMETERS

Propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. The propaga-tion delay to a logic low output may differ from the propagation delay to a logic high.

INPUT (VIX)50%tPLHOUTPUT (VOX)tPHL50%

MAXIMUM ALLOWABLE MAGNETIC FLUXDENSITY (kgauss)10.000Figure 18. Propagation Delay Parameters

Pulse-width distortion is the maximum difference between these two propagation delay values and is an indication of how accurately the input signal’s timing is preserved.

Channel-to-channel matching refers to the maximum that

amount the propagation delay differs between channels within a single ADuM140x component.

Propagation delay skew refers to the maximum that amount the propagation delay differs between multiple ADuM140x compo-nents operating under the same conditions.

1.0000.1000.0100.0011k10k10M1M100kMAGNETIC FIELD FREQUENCY (Hz)100M03786-0-021

Figure 19. Maximum Allowable External Magnetic Flux Density

Rev. B | Page 19 of 24

ADuM1400/ADuM1401/ADuM1402

For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event were to occur during a transmitted pulse (and was of the worst-case polarity), it would reduce the received pulse from > 1.0 V to 0.75 V—still well above the 0.5 V sensing threshold of the decoder.

The preceding magnetic flux density values correspond to specific current magnitudes at given distances from the ADuM140x trans-formers. Figure 20 expresses these allowable current magnitudes as a function of frequency for selected distances. As seen, the

ADuM140x is extremely immune and can be affected only by ex-tremely large currents operated at high frequency, very close to the component. For the 1 MHz example noted, one would have to place a 0.5 kA current 5 mm away from the ADuM140x to affect the component’s operation.

1000.00MAXIMUM ALLOWABLE CURRENT (kA)DISTANCE = 1m100.00

POWER CONSUMPTION

The supply current at a given channel of the ADuM140x isola-tor is a function of the supply voltage, the channel’s data rate, and the channel’s output load.

For each input channel, the supply current is given by

IDDI = IDDI (Q)

IDDI = IDDI (D) × (2f – fr) + IDDI (Q)

f ≤ 0.5frf > 0.5fr

For each output channel, the supply current is given by

IDDO = IDDO (Q)

f ≤ 0.5fr

IDDO = (IDDO (D) + (0.5 × 10−3) × CLVDDO) × (2f – fr) + IDDO (Q)

f > 0.5fr where:

IDDI (D), IDDO (D) are the input and output dynamic supply currents

per channel (mA/Mbps). CL is output load capacitance (pF). VDDO is the output supply voltage (V).

10.00

DISTANCE = 100mm1.00

DISTANCE = 5mm0.10

f is the input logic signal frequency (MHz, half of the input data rate, NRZ signaling).

fr is the input stage refresh rate (Mbps).

IDDI (Q), IDDO (Q) are the specified input and output quiescent sup-ply currents (mA).

1k10k100k1M10M100M

03786-0-0220.01

MAGNETIC FIELD FREQUENCY (Hz)

Figure 20. Maximum Allowable Current for Various Current-to-ADuM140x Spacings

Note that at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces could induce sufficiently large error voltages to trigger the thresholds of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility.

To calculate the total IDD1 and IDD2 supply current, the supply currents for each input and output channel corresponding to IDD1 and IDD2 are calculated and totaled. Figure 8 and Figure 9 provide per-channel supply currents as a function of data rate for an unloaded output condition. Figure 10 provides per-channel supply current as a function of data rate for a 15 pF output condition. Figure 11 through Figure 14 provide total IDD1 and IDD2 supply current as a function of data rate for

ADuM1400/ADuM1401/ADuM1402 channel configurations.

Rev. B | Page 20 of 24

ADuM1400/ADuM1401/ADuM1402OUTLINE DIMENSIONS

10.50 (0.4134)10.10 (0.3976)1697.60 (0.2992)7.40 (0.2913)1810.65 (0.4193)10.00 (0.3937)1.27 (0.0500)BSC0.30 (0.0118)0.10 (0.0039)COPLANARITY0.100.51 (0.0201)0.31 (0.0122)2.65 (0.1043)2.35 (0.0925)0.75 (0.0295)× 45°0.25 (0.0098)SEATINGPLANE8°0.33 (0.0130)0°0.20 (0.0079)1.27 (0.0500)0.40 (0.0157)COMPLIANT TO JEDEC STANDARDS MS-013AACONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FORREFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

Figure 21. 16-Lead Standard Small Outline Package [SOIC]

Wide Body (RW-16)

Dimension shown in millimeters (inches)

ORDERING GUIDE

Model

ADuM1400ARW2ADuM1400BRW2 ADuM1400CRW2 ADuM1400ARWZ2, 3ADuM1400BRWZ2, 3ADuM1400CRWZ2, 3ADuM1401ARW2 ADuM1401BRW2 ADuM1401CRW2 ADuM1401ARWZ2, 3ADuM1401BRWZ2, 3 ADuM1401CRWZ2, 3ADuM1402ARW2 ADuM1402BRW2 ADuM1402CRW2 ADuM1402ARWZ2, 3ADuM1402BRWZ2, 3ADuM1402CRWZ2, 3

Number of Inputs, VDD1 Side 4 4 4 4 4 4 3 3 3 3 3 3 2 2 2 2 2 2 Number of Inputs, VDD2 Side 0 0 0 0 0 0 1 1 1 1 1 1 2 2 2 2 2 2 Maximum Data Rate (Mbps) 1 10 90 1 10 90 1 10 90 1 10 90 1 10 90 1 10 90 Maximum Propagation Delay, 5 V (ns) 100 50 32 100 50 32 100 50 32 100 50 32 100 50 32 100 50 32 Maximum Pulse-Width Distortion (ns) 40 3 2 40 3 2 40 3 2 40 3 2 40 3 2 40 3 2

Temperature Range (°C) –40 to +105 –40 to +105 –40 to +105 –40 to +105 –40 to +105 –40 to +105 –40 to +105 –40 to +105 –40 to +105 –40 to +105 –40 to +105 –40 to +105 –40 to +105 –40 to +105 –40 to +105 –40 to +105 –40 to +105 –40 to +105

PackageOption1RW-16 RW-16 RW-16 RW-16 RW-16 RW-16 RW-16 RW-16 RW-16 RW-16 RW-16 RW-16 RW-16 RW-16 RW-16 RW-16 RW-16 RW-16

RW-16 = 16-lead wide body SOIC.

Tape and reel are available. The addition of an “-RL” suffix designates a 13” (1,000 units) tape and reel option. 3

Z = Pb-free part.

Rev. B | Page 21 of 24

ADuM1400/ADuM1401/ADuM1402

NOTES

Rev. B | Page 22 of 24

ADuM1400/ADuM1401/ADuM1402NOTES

Rev. B | Page 23 of 24

ADuM1400/ADuM1401/ADuM1402

NOTES

Rev. B | Page 24 of 24

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