Circuit arrangement for testing a digital circuit

专利名称：Circuit arrangement for testing a digital

circuit

发明人：Karl-Heinz Annecke,Volker Bredemeier-Klonki

申请号：US06/630066申请日：19840712公开号：US04641306A公开日：19870203

摘要：Circuit arrangement for dynamic real time testing of a synchronous digitalcircuit having a clock pulse input, a stimulus input and a circuit node at which a digital testsignal is produced after a time delay of &tgr; seconds relative to the time of receipt of asignal at the stimulus input. The arrangement includes a clock pulse generator forgenerating clock pulses; a transmitter device connected to the clock pulse generator andincluding a counter for counting the clock pulses and a digital signal generator forgenerating a reproducible digital stimulus signal having a length corresponding to apredetermined count of the counter. The transmitter device is connected for coupling anumber of clock pulses corresponding to the predetermined count of the counter to theclock pulse input of the digital circuit and for delivering the digital stimulus signal to thestimulus input of the digital circuit in synchronism with the clock pulses coupled to theclock pulse input. An analyzing device has a first input arranged for receiving the digitaltest signal from the digital circuit and a second input connected for receiving the samenumber of clock pulses coupled to the digital circuit. The analyzing device is arranged forcompressing and analyzing the test signal for errors. A device is provided for imparting a

time delay of . tau. seconds to the clock pulses received by the analyzing means.

申请人：ANT NACHRICHTENTECHNIK GMBH

代理机构：Spencer & Frank

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