8-BitUSBMultimediaKeyboardEncoderOTPMCU
Features
·Operatingvoltage:
·4096´15programmemoryROM·160´8datamemoryRAM
·HALTfunctionandwake-upfeaturereducepower
fSYS=6M/12MHz:4.4V~5.5V
·Lowvoltageresetfunction·32bidirectionalI/Olines(max.)
·8-bitprogrammabletimer/eventcounterwithover-
consumption
·8-levelsubroutinenesting
·Upto0.33msinstructioncyclewith12MHzsystem
flowinterrupt
·16-bitprogrammabletimer/eventcounterandover-flowinterrupts
·Crystaloscillator(6MHzor12MHz)·WatchdogTimer
·6channels8-bitA/Dconverter·PS2andUSBmodessupported·USB1.1lowspeedfunction
·4endpointssupported(endpoint0included)
clockatVDD=5V
·Bitmanipulationinstruction·15-bittablereadinstruction·63powerfulinstructions
·Allinstructionsinoneortwomachinecycles·20-pinSOP,48-pinSSOPpackage
GeneralDescription
Thisdeviceisan8-bithighperformanceRISC-likemicrocontrollerdesignedforUSBproductapplications.Itisparticularlysuitableforuseinproductssuchas
mice,keyboardsandjoystick.AHALTfeatureisin-cludedtoreducepowerconsumption.
Rev.1.701April22,2004
元器件交易网www.cecb2b.comHT82K96EBlockDiagram
Rev.1.702April22,2004
元器件交易网www.cecb2b.comHT82K96EPinAssignment
PinDescription
PinName
I/O
ROMCodeOption
Description
PA0~PA5PA6/TMR0PA7/TMR1
Bidirectional8-bitinput/outputport.Eachbitcanbeconfiguredasawake-upinputbyROMcodeoption.Theinputoroutputmodeiscon-trolledbyPAC(PAcontrolregister).Pull-highresistoroptions:PA0~PA7Pull-lowresistoroptions:PA0~PA5Pull-low
CMOS/NMOS/PMOSoptions:PA0~PA7Pull-high
I/O
Wakeupoptions:PA0~PA7Wake-up
CMOS/NMOS/PMOSPA6andPA7arepin-sharedwithTMR0andTMR1input,respectively.
PA0~PA5canbeusedasUSBmouseX1,X2,Y1,Y2,Z1,Z2inputformousehardwarewake-upfunction
PA6,PA7canbeusedasUSBmousebuttoninputformousehardwarewake-upfunction
Bidirectional8-bitinput/outputport.SoftwareinstructionsdeterminetheCMOSoutputorSchmitttriggerinputwithpull-highresistor(determinedbypull-highoptions).
ThePBcanbeusedasanaloginputoftheanalogtodigitalconverter(determinedbyoptions).
PB6,PB7canbeusedasUSBmousebuttoninputformouseHardwarewake-upfunction
BidirectionalI/Olines.SoftwareinstructionsdeterminetheCMOSout-putorSchmitttriggerinputwithpull-highresistor(determinedby1-bitpull-highoption).
PD4canbeusedasUSBmousebuttoninputformousehardwarewake-upfunction
PB0/AN0PB1/AN1PB2/AN2PB3/AN3PB4/AN4PB5/AN5PB6/VRLPB7/VRH
I/O
Pull-highAnaloginput
PD0~PD7I/OPull-high
Rev.1.703April22,2004
元器件交易网www.cecb2b.comHT82K96EPinNameVSS
I/O¾
ROMCodeOption
¾
Description
Negativepowersupply,ground
BidirectionalI/Olines.SoftwareinstructionsdeterminetheCMOSout-putorSchmitttriggerinputwithpull-highresistor(determinedbypull-highoptions).
PC0canbeusedasUSBmouseIRPTcontrolpinformousehardwarewake-upfunction
Schmitttriggerresetinput.ActivelowPositivepowersupply3.3Vregulatoroutput
USBD+orPS2CLKI/Oline
USBORPS2functioniscontrolledbysoftwarecontrolregisterUSBD-orPS2DATAI/Oline
USBorPS2functioniscontrolledbysoftwarecontrolregisterOSC1,OSC2areconnectedtoan6MHzor12MHzCrystal/resonator(determinedbysoftwareinstructions)fortheinternalsystemclock.
PC0~PC7I/OPull-high
RESVDDV33OUSBD+/CLKUSBD-/DATAOSC1OSC2
I¾OI/OI/OIO
¾¾¾¾¾¾
AbsoluteMaximumRatings
SupplyVoltage...........................VSS-0.3VtoVSS+6.0VInputVoltage..............................VSS-0.3VtoVDD+0.3V
StorageTemperature............................-50°Cto125°COperatingTemperature...............................0°Cto70°C
Note:Thesearestressratingsonly.Stressesexceedingtherangespecifiedunder²AbsoluteMaximumRatings²may
causesubstantialdamagetothedevice.Functionaloperationofthisdeviceatotherconditionsbeyondthoselistedinthespecificationisnotimpliedandprolongedexposuretoextremeconditionsmayaffectdevicereliabil-ity.
D.C.Characteristics
Symbol
Parameter
TestConditionsVDD¾5V5V5V5V5V5V5V5V5V5V5V
VOL=3.4VVOL=0.4VVOL=0.4V
ConditionsfSYS=6MHzfSYS=12MHzNoload,fSYS=6MHzNoload,fSYS=12MHzNoload,systemHALT,USBsuspend
Noload,systemHALT,USBsuspend
¾¾¾¾
Min.4.44.4¾¾¾¾0200.9VDD1225
Typ.¾¾6.57.5¾¾¾¾¾¾17410
Max.5.55.512162502300.850.4VDDVDD¾¾¾
Ta=25°CUnitVVmAmAmAmAVVVVmAmAmA
VDDIDD1IDD2ISTB1ISTB2VIL1VIH1VIL2VIH2IOL1IOL2IOL3
OperatingVoltage
OperatingCurrent(6MHzCrystal)OperatingCurrent(12MHzCrystal)StandbyCurrent(WDTEnabled)StandbyCurrent(WDTDisabled)InputLowVoltageforI/OPortsInputHighVoltageforI/OPortsInputLowVoltage(RES)InputHighVoltage(RES)
I/OPortSinkCurrentforPB,PC1~PC7,PDI/OPortSinkCurrentforPB,PC1~PC7,PDI/OPortSinkCurrentforPA
Rev.1.704April22,2004
元器件交易网www.cecb2b.comHT82K96ESymbolIOL4IOH1IOH2RPHRPLVLVRVV33OEA/D
Parameter
I/OPortSinkCurrentforPC0I/OPortSourceCurrentforPC0
TestConditionsVDD5V5V
ConditionsVOL=0.4VVOH=3.4VVOH=3.4V
¾¾¾
IV33O=-5mATotalerror
Min.10-8-2251533.0¾
Typ.25-16-550303.43.31
Max.¾¾¾80454.03.62
UnitmAmAmAkWkWVVLSB
I/OPortSourceCurrentforPA,PB,
5V
PC1~PC7,PD
Pull-highResistanceforPA,PB,PC,PDPull-lowResistanceforPA1~PA5LowVoltageReset3.3VRegulatorOutputA/DConversionError
5V5V¾5V5V
A.C.Characteristics
SymbolfSYSfTIMER
Parameter
SystemClock(CrystalOSC)TimerI/PFrequency(TMR0/TMR1)
TestConditionsVDD5V5V5V5V¾¾
Conditions
¾¾¾
WithoutWDTprescalerWithoutWDTprescaler
¾
Wake-upfromHALT
tSSTtINTtADCNote:tA/D=
SystemStart-upTimerPeriod
¾
Power-up,WatchdogTime-outfromnormal
¾¾
Min.60154¾1¾¾1¾
Typ.Max.¾¾3181024¾10241024¾64
12127016¾¾¾¾¾¾
Ta=25°CUnitMHzMHzmsmstSYSmstSYStWDTOSC
mstA/D
tWDTOSCWatchdogOscillatortWDT1tWDT2tRES
WatchdogTime-outPeriod(WDTOSC)WatchdogTime-outPeriod(SystemClock)ExternalResetLowPulseWidth
InterruptPulseWidthA/DConversionTime1fA/D
¾¾
,fA/D=A/Dclocksourcefrequencies(6MHz,3MHz,1.5MHz,0.75MHz)
Rev.1.705April22,2004
元器件交易网www.cecb2b.comHT82K96EFunctionalDescription
ExecutionFlow
ThesystemclockforthemicrocontrollerisderivedfromeitheracrystaloranRCoscillator.Thesystemclockisinternallydividedintofournon-overlappingclocks.Oneinstructioncycleconsistsoffoursystemclockcycles.Instructionfetchingandexecutionarepipelinedinsuchawaythatafetchtakesaninstructioncyclewhilede-codingandexecutiontakesthenextinstructioncycle.However,thepipeliningschemecauseseachinstruc-tiontoeffectivelyexecuteinacycle.Ifaninstructionchangestheprogramcounter,twocyclesarerequiredtocompletetheinstruction.ProgramCounter-PC
Theprogramcounter(PC)controlsthesequenceinwhichtheinstructionsstoredintheprogramROMareexecutedanditscontentsspecifyafullrangeofpro-grammemory.
Afteraccessingaprogrammemorywordtofetchanin-structioncode,thecontentsoftheprogramcounterare
incrementedbyone.Theprogramcounterthenpointstothememorywordcontainingthenextinstructioncode.Whenexecutingajumpinstruction,conditionalskipex-ecution,loadingPCLregister,subroutinecallorreturnfromsubroutine,initialreset,internalinterrupt,externalinterruptorreturnfrominterrupts,thePCmanipulatestheprogramtransferbyloadingtheaddresscorre-spondingtoeachinstruction.
Theconditionalskipisactivatedbyinstructions.Oncetheconditionismet,thenextinstruction,fetchedduringthecurrentinstructionexecution,isdiscardedandadummycyclereplacesittogettheproperinstruction.Otherwiseproceedtothenextinstruction.
Thelowerbyteoftheprogramcounter(PCL)isaread-ableandwriteableregister(06H).MovingdataintothePCLperformsashortjump.ThedestinationwillbewithinthecurrentprogramROMpage.
Whenacontroltransfertakesplace,anadditionaldummycycleisrequired.
ExecutionFlow
Mode
InitialresetUSBinterrupt
Timer/EventCounter0overflowTimer/EventCounter1overflowSkipLoadingPCLJump,callbranchReturnfromsubroutine
ProgramCounter
*110000
*100000
*90000
*80000
*70000
*60000
*50000
*40000
*30011
*20101
*10000
*00000
PC+2
*11#11S11
*10#10S10
*9#9S9
*8#8S8
@7#7S7
@6#6S6
@5#5S5
@4#4S4
@3#3S3
@2#2S2
@1#1S1
@0#0S0
ProgramCounter
Note:*11~*0:Programcounterbits
#11~#0:Instructioncodebits
S11~S0:Stackregisterbits@7~@0:PCLbits
Rev.1.706April22,2004
元器件交易网www.cecb2b.comHT82K96EProgramMemory-ROM
Theprogrammemoryisusedtostoretheprogramin-structionswhicharetobeexecuted.Italsocontainsdata,table,andinterruptentries,andisorganizedinto4096´15bits,addressedbytheprogramcounterandta-blepointer.
Certainlocationsintheprogrammemoryarereservedforspecialusage:
·Location000H
·Location00CH
ThislocationisreservedfortheTimer/EventCounter1interruptserviceprogram.IfatimerinterruptresultsfromaTimer/EventCounter1overflow,andtheinter-ruptisenabledandthestackisnotfull,theprogrambeginsexecutionatlocation00CH.
·Tablelocation
Thisareaisreservedforprograminitialization.Afterchipreset,theprogramalwaysbeginsexecutionatlo-cation000H.
·Location004H
ThisareaisreservedfortheUSBinterruptserviceprogram.IftheUSBinterruptisactivated,theinterruptisenabledandthestackisnotfull,theprogrambeginsexecutionatlocation004H.
·Location008H
ThisareaisreservedfortheTimer/EventCounter0in-terruptserviceprogram.IfatimerinterruptresultsfromaTimer/EventCounter0overflow,andifthein-terruptisenabledandthestackisnotfull,theprogrambeginsexecutionatlocation008H.
Anylocationintheprogrammemorycanbeusedaslook-uptables.Theinstructions²TABRDC[m]²(thecurrentpage,onepage=256words)and²TABRDL[m]²(thelastpage)transferthecontentsofthelower-orderbytetothespecifieddatamemory,andthehigher-orderbytetoTBLH(08H).Onlythedesti-nationofthelower-orderbyteinthetableiswell-defined,theotherbitsofthetablewordaretrans-ferredtothelowerportionofTBLH,andtheremaining1-bitwordsarereadas²0².TheTableHigher-orderbyteregister(TBLH)isreadonly.Thetablepointer(TBLP)isaread/writeregister(07H),whichindicatesthetablelocation.Beforeaccessingthetable,thelo-cationmustbeplacedintheTBLP.TheTBLHisreadonlyandcannotberestored.IfthemainroutineandtheISR(InterruptServiceRoutine)bothemploythetablereadinstruction,thecontentsoftheTBLHinthemainroutinearelikelytobechangedbythetablereadinstructionusedintheISR.Errorscanoccur.Inotherwords,usingthetablereadinstructioninthemainrou-tineandtheISRsimultaneouslyshouldbeavoided.However,ifthetablereadinstructionhastobeappliedinboththemainroutineandtheISR,theinterruptissupposedtobedisabledpriortothetablereadin-struction.ItwillnotbeenableduntiltheTBLHhasbeenbackedup.Alltablerelatedinstructionsrequiretwocyclestocompletetheoperation.Theseareasmayfunctionasnormalprogrammemorydependingupontherequirements.StackRegister-STACK
ProgramMemory
Thisisaspecialpartofthememorywhichisusedtosavethecontentsoftheprogramcounter(PC)only.Thestackisorganizedinto8levelsandisneitherpartofthedatanorpartoftheprogramspace,andisneitherread-ablenorwriteable.Theactivatedlevelisindexedbythestackpointer(SP)andisneitherreadablenorwriteable.
InstructionTABRDC[m]TABRDL[m]
TableLocation
*11P111
*10P101
*9P91
*8P81
*7@7@7
*6@6@6
*5@5@5
*4@4@4
*3@3@3
*2@2@2
*1@1@1
*0@0@0
TableLocation
Note:*11~*0:Tablelocationbits
@7~@0:Tablepointerbits
P11~P8:Currentprogramcounterbits
Rev.1.707April22,2004
元器件交易网www.cecb2b.comHT82K96EAtasubroutinecallorinterruptacknowledgesignal,thecontentsoftheprogramcounterarepushedontothestack.Attheendofasubroutineoraninterruptroutine,signaledbyareturninstruction(RETorRETI),thepro-gramcounterisrestoredtoitspreviousvaluefromthestack.Afterachipreset,theSPwillpointtothetopofthestack.
Ifthestackisfullandanon-maskedinterrupttakesplace,theinterruptrequestflagwillberecordedbuttheacknowledgesignalwillbeinhibited.Whenthestackpointerisdecremented(byRETorRETI),theinterruptwillbeserviced.Thisfeaturepreventsstackoverflowal-lowingtheprogrammertousethestructuremoreeasily.Inasimilarcase,ifthestackisfullanda²CALL²issub-sequentlyexecuted,stackoverflowoccursandthefirstentrywillbelost(onlythemostrecent8returnad-dressesarestored).
DataMemory-RAMforBank0
Thedatamemoryisdesignedwith190´8bits.Thedatamemoryisdividedintotwofunctionalgroups:spe-cialfunctionregistersandgeneralpurposedatamem-ory(160´8).Mostareread/write,butsomearereadonly.
Thespecialfunctionregistersincludetheindirectad-dressingregisters(R0;00H,R1;02H),Bankregister(BP,04H),Timer/EventCounter0(TMR0;0DH),Timer/EventCounter0controlregister(TMR0C;0EH),Timer/EventCounter1higherorderbyteregister(TMR1H;0FH),Timer/EventCounter1lowerorderbyteregister(TMR1L;10H),Timer/EventCounter1controlregister(TMR1C;11H),programcounterlower-orderbyteregister(PCL;06H),memorypointerregisters(MP0;01H,MP1;03H),accumulator(ACC;05H),tablepointer(TBLP;07H),tablehigher-orderbyteregister(TBLH;08H),statusregister(STATUS;0AH),interruptcontrolregister(INTC;0BH),WatchdogTimeroptionsettingregister(WDTS;09H),I/Oregisters(PA;12H,PB;14H,PC;16H,PD;18H),I/Ocontrolregisters(PAC;13H,PBC;15H,PCC;17H,PDC;19H).USB/PS2statusandcontrolregister(USC;1AH),USBendpointinterruptstatusregister(USR;1BH),systemclockcon-trolregister(SCC;1CH).A/Dconverterstatusandcon-trolregister(ADSC;1DH)andA/Dconverterresultregister(ADR;1EH).Theremainingspacebeforethe20Hisreservedforfutureexpandedusageandreadingtheselocationswillget²00H².Thegeneralpurposedatamemory,addressedfrom20HtoBFH,isusedfordataandcontrolinformationunderinstructioncom-mands.
Bank0RAMMapping
Allofthedatamemoryareascanhandlearithmetic,logic,increment,decrementandrotateoperationsdi-rectly.Exceptforsomededicatedbits,eachbitinthedatamemorycanbesetandresetby²SET[m].i²and²CLR[m].i².Theyarealsoindirectlyaccessiblethroughmemorypointerregisters(MP0orMP1).
Rev.1.708April22,2004
元器件交易网www.cecb2b.comHT82K96EDataMemory-RAMforBank1
ThespecialfunctionregistersusedinUSBinterfacearelocatedinRAMbank1.InordertoaccessBank1regis-ter,onlytheIndirectaddressingpointerMP1canbeusedandtheBankregisterBPshouldsetto1.Themap-pingofRAMbank1isasshown.
Theindirectaddressingpointer(MP1)canaccessBank0orBank1RAMdataaccordingthevalueofBPissetto0or1respectively.
Thememorypointerregisters(MP0andMP1)are8-bitregisters.Accumulator
TheaccumulatoriscloselyrelatedtoALUoperations.Itisalsomappedtolocation05Hofthedatamemoryandcancarryoutimmediatedataoperations.Thedatamovementbetweentwodatamemorylocationsmustpassthroughtheaccumulator.ArithmeticandLogicUnit-ALU
Thiscircuitperforms8-bitarithmeticandlogicopera-tions.TheALUprovidesthefollowingfunctions:
·Arithmeticoperations(ADD,ADC,SUB,SBC,DAA)·Logicoperations(AND,OR,XOR,CPL)·Rotation(RL,RR,RLC,RRC)·IncrementandDecrement(INC,DEC)·Branchdecision(SZ,SNZ,SIZ,SDZ....)
RAMBank1
Note:
Register45HisdefinedforversionCorlaterver-sion
TheALUnotonlysavestheresultsofadataoperationbutalsochangesthestatusregister.StatusRegister-STATUS
This8-bitregister(0AH)containsthezeroflag(Z),carryflag(C),auxiliarycarryflag(AC),overflowflag(OV),powerdownflag(PDF),andwatchdogtime-outflag(TO).Italsorecordsthestatusinformationandcontrolstheoperationsequence.
WiththeexceptionoftheTOandPDFflags,bitsinthestatusregistercanbealteredbyinstructionslikemostotherregisters.AnydatawrittenintothestatusregisterwillnotchangetheTOorPDFflag.Inaddi-tionoperationsrelatedtothestatusregistermaygivedifferentresultsfromthoseintended.Function
IndirectAddressingRegister
Location00Hand02Hareindirectaddressingregistersthatarenotphysicallyimplemented.Anyread/writeop-erationof[00H]([02H])willaccessdatamemorypointedtobyMP0(MP1).Readinglocation00H(02H)itselfindi-rectlywillreturntheresult00H.Writingindirectlyresultsinnooperation.
Theindirectaddressingpointer(MP0)alwayspointtoBank0RAMaddressesnomatterthevalueofBankRegister(BP).LabelsC
Bits0
Cissetiftheoperationresultsinacarryduringanadditionoperationorifaborrowdoesnottakeplaceduringasubtractionoperation;otherwiseCiscleared.Cisalsoaffectedbyarotatethroughcarryinstruction.
ACissetiftheoperationresultsinacarryoutofthelownibblesinadditionornoborrowfromthehighnibbleintothelownibbleinsubtraction;otherwiseACiscleared.
Zissetiftheresultofanarithmeticorlogicoperationiszero;otherwiseZiscleared.OVissetiftheoperationresultsinacarryintothehighest-orderbitbutnotacarryoutofthehighest-orderbit,orviceversa;otherwiseOViscleared.
PDFisclearedbysystempower-uporexecutingthe²CLRWDT²instruction.PDFissetbyex-ecutingthe²HALT²instruction.
TOisclearedbysystempower-uporexecutingthe²CLRWDT²or²HALT²instruction.TOissetbyaWDTtime-out.Unusedbit,readas²0²Unusedbit,readas²0²
StatusRegister
ACZOVPDFTO¾¾
1234567
Rev.1.709April22,2004
元器件交易网www.cecb2b.comHT82K96ETheTOflagcanbeaffectedonlybysystempower-up,aWDTtime-outorexecutingthe²CLRWDT²or²HALT²instruction.ThePDFflagcanbeaffectedonlybyex-ecutingthe²HALT²or²CLRWDT²instructionordur-ingasystempower-up.
TheZ,OV,ACandCflagsgenerallyreflectthestatusofthelatestoperations.
Inaddition,onenteringtheinterruptsequenceorexe-cutingthesubroutinecall,thestatusregisterwillnotbepushedontothestackautomatically.Ifthecontentsofthestatusareimportantandifthesubroutinecancor-ruptthestatusregister,precautionsmustbetakentosaveitproperly.Interrupt
Thedeviceprovidesanexternalinterruptandinternaltimer/eventcounterinterrupts.TheInterruptControlRegister(INTC;0BH)containstheinterruptcontrolbitstosettheenable/disableandtheinterruptrequestflags.Onceaninterruptsubroutineisserviced,alltheotherin-terruptswillbeblocked(byclearingtheEMIbit).Thisschememaypreventanyfurtherinterruptnesting.Otherinterruptrequestsmayoccurduringthisintervalbutonlytheinterruptrequestflagisrecorded.Ifacertaininter-ruptrequiresservicingwithintheserviceroutine,theEMIbitandthecorrespondingbitoftheINTCmaybesettoallowinterruptnesting.Ifthestackisfull,theinterruptrequestwillnotbeacknowledged,eveniftherelatedin-terruptisenabled,untiltheSPisdecremented.Ifimmedi-ateserviceisdesired,thestackmustbepreventedfrombecomingfull.
Allthesekindsofinterruptshaveawake-upcapability.Asaninterruptisserviced,acontroltransferoccursbypushingtheprogramcounterontothestack,followedbyabranchtoasubroutineatspecifiedlocationinthepro-grammemory.Onlytheprogramcounterispushedontothestack.Ifthecontentsoftheregisterorstatusregister(STATUS)arealteredbytheinterruptserviceprogramwhichcorruptsthedesiredcontrolsequence,thecon-tentsshouldbesavedinadvance.Register
BitNo.012
INTC(0BH)
34567
LabelEMIEUIET0IET1IUSBFT0FT1F¾
USBinterruptsaretriggeredbythefollowingUSBeventsandtherelatedinterruptrequestflag(USBF;bit4ofINTC)willbeset.
·TheaccessofthecorrespondingUSBFIFOfromPC·TheUSBsuspendsignalfromPC·TheUSBresumesignalfromPC·USBResetsignal
Whentheinterruptisenabled,thestackisnotfullandtheexternalinterruptisactive,asubroutinecalltoloca-tion04Hwilloccur.Theinterruptrequestflag(USBF)andEMIbitswillbeclearedtodisableotherinterrupts.WhenPCHostaccesstheFIFOoftheHT82K96E,thecorrespondingrequestbitofUSRisset,andaUSBin-terruptistriggered.SousercaneasytodecidewhichFIFOisaccessed.Whentheinterrupthasbeenserved,thecorrespondingbitshouldbeclearedbyfirmware.WhenHT82K96EreceiveaUSBSuspendsignalfromHostPC,thesuspendline(bit0ofUSC)oftheHT82K96EissetandaUSBinterruptisalsotriggered.AlsowhenHT82K96EreceiveaResumesignalfromHostPC,theresumeline(bit3ofUSC)ofHT82K96EissetandaUSBinterruptistriggered.
WhateverthereareUSBresetsignalisdetected,theUSBinterruptistriggered.
TheinternalTimer/EventCounter0interruptisinitial-izedbysettingtheTimer/EventCounter0interruptre-questflag(;bit5ofINTC),causedbyatimer0overflow.Whentheinterruptisenabled,thestackisnotfullandtheT0Fbitisset,asubroutinecalltolocation08Hwilloccur.Therelatedinterruptrequestflag(T0F)willbere-setandtheEMIbitclearedtodisablefurtherinterrupts.Theinternaltimer/evencounter1interruptisinitializedbysettingtheTimer/EventCounter1interruptrequestflag(;bit6ofINTC),causedbyatimer1overflow.Whentheinterruptisenabled,thestackisnotfullandtheT1Fisset,asubroutinecalltolocation0CHwilloccur.Therelatedinterruptrequestflag(T1F)willberesetandtheEMIbitclearedtodisablefurtherinterrupts.
Function
Controlsthemaster(global)interrupt(1=enabled;0=disabled)ControlstheUSBinterrupt(1=enabled;0=disabled)
ControlstheTimer/EventCounter0interrupt(1=enabled;0=disabled)ControlstheTimer/EventCounter1interrupt(1=enabled;0=disabled)USBinterruptrequestflag(1=active;0=inactive)
InternalTimer/EventCounter0requestflag(1=active;0=inactive)InternalTimer/EventCounter1requestflag(1=active;0=inactive)Unusedbit,readas²0²
INTCRegister
Rev.1.7010April22,2004
元器件交易网www.cecb2b.comHT82K96EDuringtheexecutionofaninterruptsubroutine,otherin-terruptacknowledgesignalsarehelduntilthe²RETI²in-structionisexecutedortheEMIbitandtherelatedinterruptcontrolbitaresetto1(ifthestackisnotfull).Toreturnfromtheinterruptsubroutine,²RET²or²RETI²maybeinvoked.RETIwillsettheEMIbittoenableanin-terruptservice,butRETwillnot.
Interrupts,occurringintheintervalbetweentherisingedgesoftwoconsecutiveT2pulses,willbeservicedonthelatterofthetwoT2pulses,ifthecorrespondinginter-ruptsareenabled.Inthecaseofsimultaneousrequeststhefollowingtableshowstheprioritythatisapplied.ThesecanbemaskedbyresettingtheEMIbit.No.abc
InterruptSource
USBinterrupt
Timer/EventCounter0overflowTimer/EventCounter1overflow
PriorityVector123
04H08H0CH
OscillatorConfiguration
Thereisanoscillatorcircuitsinthemicrocontroller.
SystemOscillator
Thisoscillatorisdesignedforsystemclocks.TheHALTmodestopsthesystemoscillatorandignoresanexter-nalsignaltoconservepower.
AcrystalacrossOSC1andOSC2isneededtoprovidethefeedbackandphaseshiftrequiredfortheoscillator.Nootherexternalcomponentsarerequired.Insteadofacrystal,aresonatorcanalsobeconnectedbetweenOSC1andOSC2togetafrequencyreference,buttwoexternalcapacitorsinOSC1andOSC2arerequired.TheWDToscillatorisafreerunningon-chipRCoscilla-tor,andnoexternalcomponentsarerequired.Evenifthesystementersthepowerdownmode,thesystemclockisstopped,buttheWDToscillatorstillworkswithinaperiodofapproximately31ms.TheWDToscillatorcanbedisabledbyROMcodeoptiontoconservepower.WatchdogTimer-WDT
TheWDTclocksourceisimplementedbyadedicatedRCoscillator(WDToscillator),orinstructionclock(sys-temclockdividedby4),determinestheROMcodeop-tion.Thistimerisdesignedtopreventasoftwaremalfunctionorsequencefromjumpingtoanunknownlocationwithunpredictableresults.TheWatchdogTimercanbedisabledbyROMcodeoption.IftheWatchdogTimerisdisabled,alltheexecutionsrelatedtotheWDTresultinnooperation.
TheTimer/EventCounter0/1interruptrequestflag(T0F/T1F),USBinterruptrequestflag(USBF),enableTimer/EventCounter0/1interruptbit(ET0I/ET1I),en-ableUSBinterruptbit(EUI)andenablemasterinterruptbit(EMI)constituteaninterruptcontrolregister(INTC)whichislocatedat0BHinthedatamemory.EMI,EUI,ET0IandET1Iareusedtocontroltheenabling/dis-ablingofinterrupts.Thesebitspreventtherequestedin-terruptfrombeingserviced.Oncetheinterruptrequestflags(T0F,T1F,USBF)areset,theywillremainintheINTCregisteruntiltheinterruptsareservicedorclearedbyasoftwareinstruction.
Itisrecommendedthataprogramdoesnotusethe²CALLsubroutine²withintheinterruptsubroutine.In-terruptsoftenoccurinanunpredictablemannerorneedtobeservicedimmediatelyinsomeapplications.Ifonlyonestackisleftandenablingtheinterruptisnotwellcontrolled,theoriginalcontrolsequencewillbedam-agedoncethe²CALL²operatesintheinterruptsubrou-tine.
WatchdogTimer
Rev.1.7011April22,2004
元器件交易网www.cecb2b.comHT82K96EOncetheinternalWDToscillator(RCoscillatorwithaperiodof31ms/5Vnormally)isselected,itisfirstdividedby256(8-stage)togetthenominaltime-outperiodof8ms/5V.Thistime-outperiodmayvarywithtempera-tures,VDDandprocessvariations.ByinvokingtheWDTprescaler,longertime-outperiodscanberealized.WritingdatatoWS2,WS1,WS0(bit2,1,0oftheWDTS)cangivedifferenttime-outperiods.IfWS2,WS1,andWS0areallequalto1,thedivisionratioisupto1:128,andthemaximumtime-outperiodis1s/5V.IftheWDToscillatorisdisabled,theWDTclockmaystillcomefromtheinstruc-tionclockandoperatesinthesamemannerexceptthatintheHALTstatetheWDTmaystopcountingandloseitsprotectingpurpose.Inthissituationthelogiccanonlyberestartedbyexternallogic.Thehighnibbleandbit3oftheWDTSarereservedforuser¢sdefinedflags,whichcanonlybesetto²10000²(WDTS.7~WDTS.3).Ifthedeviceoperatesinanoisyenvironment,usingtheon-chip32kHzRCoscillator(WDTOSC)isstronglyrec-ommended,sincetheHALTwillstopthesystemclock.WS200001111
WS100110011
WS001010101WDTSRegister
TheWDToverflowundernormaloperationwillinitialize²chipreset²andsetthestatusbit²TO².ButintheHALTmode,theoverflowwillinitializea²warmreset²andonlythePCandSPareresettozero.ToclearthecontentsofWDT(includingtheWDTprescaler),threemethodsareadopted;externalreset(alowleveltoRES),softwarein-structionanda²HALT²instruction.Thesoftwareinstruc-tioninclude²CLRWDT²andtheotherset-²CLRWDT1²and²CLRWDT2².Ofthesetwotypesofinstruc-tion,onlyonecanbeactivedependingontheROMcodeoption-²CLRWDTtimesselectionoption².Ifthe²CLRWDT²isselected(i.e.CLRWDTtimesequalone),anyexecutionofthe²CLRWDT²instructionwillcleartheWDT.Inthecasethat²CLRWDT²and²CLRWDT²arechosen(i.e.CLRWDTtimesequaltwo),thesetwoinstructionsmustbeexecutedtocleartheWDT;other-wise,theWDTmayresetthechipasaresultoftime-out.Thetime-outperiodsdefinedinWDTScanusedas²wake-upperiod²intheMouseHardwarewake-upfunc-tion.PleasereferencetoMouseHardwareWake-upfunctiondescription.
DivisionRatio
1:11:21:41:81:161:321:641:128
PowerDownOperation-HALT
TheHALTmodeisinitializedbythe²HALT²instructionandresultsinthefollowing...
·ThesystemoscillatorwillbeturnedoffbuttheWDT
oscillatorremainsrunning(iftheWDToscillatorisse-lected).
·ThecontentsoftheonchipRAMandregistersremainunchanged.
·WDTandWDTprescalerwillbeclearedandre-
countedagain(iftheWDTclockisfromtheWDTos-cillator).
·AlloftheI/Oportsmaintaintheiroriginalstatus.·ThePDFflagissetandtheTOflagiscleared.
ThesystemcanleavetheHALTmodebymeansofanexternalreset,aninterrupt,anexternalfallingedgesig-nalonportAoraWDToverflow.AnexternalresetcausesadeviceinitializationandtheWDToverflowper-formsa²warmreset².AftertheTOandPDFflagsareexamined,thereasonforchipresetcanbedetermined.ThePDFflagisclearedbysystempower-uporexecut-ingthe²CLRWDT²instructionandissetwhenexecut-ingthe²HALT²instruction.TheTOflagissetiftheWDTtime-outoccurs,andcausesawake-upthatonlyresetsthePCandSP;theothersremainintheiroriginalstatus.TheportAwake-upandinterruptmethodscanbecon-sideredasacontinuationofnormalexecution.EachbitinportAcanbeindependentlyselectedtowakeupthedevicebymaskoption.AwakeningfromanI/Oportstim-ulus,theprogramwillresumeexecutionofthenextin-struction.Ifitawakensfromaninterrupt,twosequencemayoccur.Iftherelatedinterruptisdisabledortheinter-ruptisenabledbutthestackisfull,theprogramwillre-sumeexecutionatthenextinstruction.Iftheinterruptisenabledandthestackisnotfull,theregularinterruptre-sponsetakesplace.Ifaninterruptrequestflagissetto²1²beforeenteringtheHALTmode,thewake-upfunc-tionoftherelatedinterruptwillbedisabled.Onceawake-upeventoccurs,ittakes1024tSYS(systemclockperiod)toresumenormaloperation.Inotherwords,adummyperiodwillbeinsertedafterawake-up.Ifthewake-upresultsfromaninterruptacknowledgesignal,theactualinterruptsubroutineexecutionwillbedelayedbyoneormorecycles.Ifthewake-upresultsinthenextinstructionexecution,thiswillbeexecutedimmediatelyafterthedummyperiodisfinished.
Tominimizepowerconsumption,alltheI/OpinsshouldbecarefullymanagedbeforeenteringtheHALTstatus.Reset
Therearethreewaysinwhicharesetcanoccur:
·RESresetduringnormaloperation·RESresetduringHALT
·WDTtime-outresetduringnormaloperation
Rev.1.7012April22,2004
元器件交易网www.cecb2b.comHT82K96ETheWDTtime-outduringHALTisdifferentfromotherchipresetconditions,sinceitcanperforma²warmre-set²thatresetsonlythePCandSP,leavingtheothercir-cuitsintheiroriginalstate.Someregistersremainun-changedduringotherresetconditions.Mostregistersareresettothe²initialcondition²whentheresetcondi-tionsaremet.ByexaminingthePDFandTOflags,theprogramcandistinguishbetweendifferent²chipresets².
TOPDF0u011
0u1u1
RESETConditions
RESresetduringpower-upRESresetduringnormaloperationRESwake-upHALT
WDTtime-outduringnormaloperationWDTwake-upHALT
ResetCircuit
Note:²u²standsfor²unchanged²
Toguaranteethatthesystemoscillatorisstartedandstabilized,theSST(SystemStart-upTimer)providesanextra-delayof1024systemclockpulseswhenthesys-temreset(power-up,WDTtime-outorRESreset)orthesystemawakesfromtheHALTstate.
Whenasystemresetoccurs,theSSTdelayisaddedduringtheresetperiod.Anywake-upfromHALTwillen-abletheSSTdelay.
ResetConfiguration
Thefunctionalunitchipresetstatusareshownbelow.PCInterruptPrescalerWDT
000HDisableClear
Clear.Aftermasterreset,WDTbeginscounting
Timer/eventCounterOff
ResetTimingChart
Input/outputPortsSP
Inputmode
Pointstothetopofthestack
Rev.1.7013April22,2004
元器件交易网www.cecb2b.comHT82K96EThestatesoftheregistersissummarizedinthetable.RegisterTMR0TMR0CTMR1HTMR1LTMR1CProgramCounterMP0MP1ACCTBLPTBLHSTATUSINTCWDTSPAPACPBPBCPCPCCPDPDCAWRPIPESTALLMISCFIFO0FIFO1FIFO2FIFO3USCUSRSCCADSCADRNote:
Reset(PowerOn)xxxxxxxx00-01000xxxxxxxxxxxxxxxx00-01---000Hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx-xxxxxxx--00xxxx-000000010000111111111111111111111111111111111111111111111111111111111111111111100000000000000000000000000000000xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx11xx0000010000000000000010000000xxxxxxxx
WDTTime-out(NormalOperation)uuuuuuuu00-01000uuuuuuuuuuuuuuuu00-01---000Huuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu-uuuuuuu--1uuuuu-0000000100001111111111111111111111111111111111111111111111111111111111111111111uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuxxuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu
RESReset(NormalOperation)uuuuuuuu00-01000uuuuuuuuuuuuuuuu00-01---000Huuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu-uuuuuuu--uuuuuu-000000010000111111111111111111111111111111111111111111111111111111111111111111100000000000000000000000000000000uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu11xx0000010000000000000010000000xxxxxxxx
RESReset(HALT)uuuuuuuu00-01000uuuuuuuuuuuuuuuu00-01---000Huuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu-uuuuuuu--01uuuu-000000010000111111111111111111111111111111111111111111111111111111111111111111100000000000000000000000000000000uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu11xx0000010000000000000010000000xxxxxxxx
WDTTime-Out(HALT)*uuuuuuuuuu-uuuuuuuuuuuuuuuuuuuuuuu-uu---000Huuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu-uuuuuuu--11uuuu-uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuxxuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu
USB-Reset(Normal)uuuuuuuu00-01000uuuuuuuuuuuuuuuu00-01---000Huuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu-uuuuuuu--uuuuuu-00000001000011111111111111111111111111111111111111111111111111111111111111111110000000000000000000000000000000000000000000000000000000000000000uu000u0001uu00000u00u00010000000xxxxxxxx
USB-Reset(HALT)uuuuuuuu00-01000uuuuuuuuuuuuuuuu00-01---000Huuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu-uuuuuuu--01uuuu-00000001000011111111111111111111111111111111111111111111111111111111111111111110000000000000000000000000000000000000000000000000000000000000000uu000u0001uu00000u00u00010000000xxxxxxxx
²*²standsfor²warmreset²²u²standsfor²unchanged²²x²standsfor²unknown²
Rev.1.7014April22,2004
元器件交易网www.cecb2b.comHT82K96ETimer/EventCounter
Twotimer/eventcounters(TMR0,TMR1)areimple-mentedinthemicrocontroller.TheTimer/EventCounter0containsan8-bitprogrammablecount-upcounterandtheclockmaycomesfromanexternalsourceorfromfSYS/4.
TheTimer/EventCounter1containsan16-bitprogram-mablecount-upcounterandtheclockmaycomefromanexternalsourceorfromthesystemclockdividedby4.
Label(TMR0C)
¾
TETON
¾
Bits0~2345
Unusedbit,readas²0²
TodefinetheTMR0activeedgeofTimer/EventCounter0(0=activeonlowtohigh;1=activeonhightolow)Toenable/disabletimer0counting(0=disabled;1=enabled)Unusedbit,readas²0²
Todefinetheoperatingmode
01=Eventcountmode(externalclock)10=Timermode(internalclock)
11=Pulsewidthmeasurementmode00=Unused
TMR0CRegister
Label(TMR1C)
¾TETON
¾
Bits0~2345
Unusedbit,readas²0²
TodefinetheTMR1activeedgeofTimer/EventCounter1(0=activeonlowtohigh;1=activeonhightolow)Toenable/disabletimer1counting(0=disabled;1=enabled)Unusedbit,readas²0²
Todefinetheoperatingmode
01=Eventcountmode(externalclock)10=Timermode(internalclock)
11=Pulsewidthmeasurementmode00=Unused
TMR1CRegisterFunction
Usingtheinternalclocksource,thereisonly1referencetime-baseforTimer/EventCounter0.TheinternalclocksourceiscomingfromfSYS/4.
Theexternalclockinputallowstheusertocountexter-nalevents,measuretimeintervalsorpulsewidths.Usingtheinternalclocksource,thereisonly1referencetime-baseforTimer/EventCounter1.TheinternalclocksourceiscomingfromfSYS/4.Theexternalclockinputallowstheusertocountexternalevents,measuretimeintervalsorpulsewidths.
Function
TM0TM167
TM0TM167
Timer/EventCounter0
Rev.1.7015April22,2004
元器件交易网www.cecb2b.comHT82K96ETimer/EventCounter1
Thereare2registersrelatedtotheTimer/EventCounter0;TMR0([0DH]),TMR0C([0EH]).Twophysicalregis-tersaremappedtoTMR0location;writingTMR0makesthestartingvaluebeplacedintheTimer/EventCounter0preloadregisterandreadingTMR0getsthecontentsoftheTimer/EventCounter0.TheTMR0Cisatimer/eventcountercontrolregister,whichdefinessomeoptions.
Thereare3registersrelatedtoTimer/EventCounter1;TMR1H(0FH),TMR1L(10H),TMR1C(11H).WritingTMR1Lwillonlyputthewrittendatatoaninternallower-orderbytebuffer(8bits)andwritingTMR1Hwilltransferthespecifieddataandthecontentsofthelower-orderbytebuffertoTMR1HandTMR1Lpreloadregisters,respectively.TheTimer/EventCounter1preloadregisterischangedbyeachwritingTMR1Hop-erations.ReadingTMR1HwilllatchthecontentsofTMR1HandTMR1Lcounterstothedestinationandthelower-orderbytebuffer,respectively.ReadingtheTMR1Lwillreadthecontentsofthelower-orderbytebuffer.TheTMR1CistheTimer/EventCounter1controlregister,whichdefinestheoperatingmode,countingen-ableordisableandactiveedge.
TheTM0,TM1bitsdefinetheoperatingmode.Theeventcountmodeisusedtocountexternalevents,whichmeanstheclocksourcecomesfromanexternal(TMR0/TMR1)pin.Thetimermodefunctionsasanor-maltimerwiththeclocksourcecomingfromthefSYS/4(Timer0/Timer1).Thepulsewidthmeasurementmodecanbeusedtocountthehighorlowleveldurationoftheexternalsignal(TMR0/TMR1).ThecountingisbasedonthefSYS/4(Timer0/Timer1).
Intheeventcountortimermode,oncetheTimer/EventCounter0/1startscounting,itwillcountfromthecurrentcontentsintheTimer/EventCounter0/1toFFHorFFFFH.Onceoverflowoccurs,thecounterisreloadedfromtheTimer/EventCounter0/1preloadregisterandgeneratestheinterruptrequestflag(T0F/T1F;bit5/6ofINTC)atthesametime.
InthepulsewidthmeasurementmodewiththeTONandTEbitsequaltoone,oncetheTMR0/TMR1hasre-ceivedatransientfromlowtohigh(orhightolowiftheTEbitsis²0²)itwillstartcountinguntiltheTMR0/TMR1returnstotheoriginallevelandresetstheTON.ThemeasuredresultwillremainintheTimer/EventCounter0/1eveniftheactivatedtransientoccursagain.Inotherwords,onlyonecyclemeasurementcanbedone.UntilsettingtheTON,thecyclemeasurementwillfunctionagainaslongasitreceivesfurthertransientpulse.Notethat,inthisoperatingmode,theTimer/EventCounter0/1startscountingnotaccordingtothelogiclevelbutaccordingtothetransientedges.Inthecaseofcounteroverflows,thecounter0/1isreloadedfromtheTimer/EventCounter0/1preloadregisterandissuestheinterruptrequestjustliketheothertwomodes.Toen-ablethecountingoperation,thetimerONbit(TON;bit4ofTMR0C/TMR1C)shouldbesetto1.Inthepulsewidthmeasurementmode,theTONwillbeclearedautomati-callyafterthemeasurementcycleiscompleted.ButintheothertwomodestheTONcanonlyberesetbyin-structions.TheoverflowoftheTimer/EventCounter0/1isoneofthewake-upsources.Nomatterwhattheoper-ationmodeis,writinga0toET0I/ET1Icandisablethecorrespondinginterruptservices.
InthecaseofTimer/EventCounter0/1OFFcondition,writingdatatotheTimer/EventCounter0/1preloadreg-isterwillalsoreloadthatdatatotheTimer/EventCoun-ter0/1.ButiftheTimer/EventCounter0/1isturnedon,datawrittentoitwillonlybekeptintheTimer/EventCounter0/1preloadregister.TheTimer/EventCounter0/1willstilloperateuntiloverflowoccurs(aTimer/EventCounter0/1reloadingwilloccuratthesametime).WhentheTimer/EventCounter0/1(readingTMR0/TMR1)isread,theclockwillbeblockedtoavoiderrors.Asclockblockingmayresultsinacountingerror,thismustbetakenintoconsiderationbytheprogram-mer.
Rev.1.7016April22,2004
元器件交易网www.cecb2b.comHT82K96EInput/OutputPorts
Thereare32bidirectionalinput/outputlinesinthemicrocontroller,labeledfromPAtoPD,whicharemappedtothedatamemoryof[12H],[14H],[16H]and[18H]respectively.AlloftheseI/Oportscanbeusedforinputandoutputoperations.Forinputoperation,theseportsarenon-latching,thatis,theinputsmustbereadyattheT2risingedgeofinstruction²MOVA,[m]²(m=12H,14H,16Hor18H).Foroutputoperation,allthedataislatchedandremainsunchangeduntiltheoutputlatchisrewritten.
EachI/Olinehasitsowncontrolregister(PAC,PBC,PCC,PDC)tocontroltheinput/outputconfiguration.Withthiscontrolregister,CMOS/NMOS/PMOSoutputorSchmitttriggerinputwithorwithoutpull-high/lowre-sistorstructurescanbereconfigureddynamically(i.e.on-the-fly)undersoftwarecontrol.Tofunctionasanin-put,thecorrespondinglatchofthecontrolregistermustwrite²1².Theinputsourcealsodependsonthecontrolregister.Ifthecontrolregisterbitis²1²,theinputwillreadthepadstate.Ifthecontrolregisterbitis²0²,thecontentsofthelatcheswillmovetotheinternalbus.Thelatterispossibleinthe²read-modify-write²instruction.Foroutputfunction,CMOS/NMOS/PMOSconfigura-tionscanbeselected(NMOSandPMOSareavailableforPAonly).Thesecontrolregistersaremappedtoloca-tions13H,15H,17Hand19H.
Afterachipreset,theseinput/outputlinesremainathighlevelsorfloatingstate(dependingonthepull-high/lowoptions).Eachbitoftheseinput/outputlatchescanbesetorclearedby²SET[m].i²and²CLR[m].i²(m=12H,14H,16Hor18H)instructions.
Someinstructionsfirstinputdataandthenfollowtheoutputoperations.Forexample,²SET[m].i²,²CLR[m].i²,²CPL[m]²,²CPLA[m]²readtheentireportstatesintotheCPU,executethedefinedoperations(bit-operation),andthenwritetheresultsbacktothelatchesortheaccumulator.
EachlineofportAhasthecapabilityofwaking-upthedevice.
Therearepull-high/low(PAonly)optionsavailableforI/Olines.Oncethepull-high/lowoptionofanI/Olineisselected,theI/Olinehavepull-high/lowresistor.Other-wise,thepull-high/lowresistorisabsent.Itshouldbenotedthatanon-pull-high/lowI/Olineoperatingininputmodewillcauseafloatingstate.
ItisrecommendedthatunusedornotbondedoutI/Olinesshouldbesetasoutputpinsbysoftwareinstructiontoavoidconsumingpowerunderinputfloatingstate.
Input/OutputPorts
Rev.1.7017April22,2004
元器件交易网www.cecb2b.comHT82K96ELowVoltageReset-LVR
Themicrocontrollerprovideslowvoltageresetcircuitinordertomonitorthesupplyvoltageofthedevice.Ifthesupplyvoltageofthedeviceiswithintherange0.9V~VLVRsuchaschangingabattery,theLVRwillau-tomaticallyresetthedeviceinternally.TheLVRincludesthefollowingspecifications:
·Thelowvoltage(0.9V~VLVR)hastoremainintheir
TherelationshipbetweenVDDandVLVRisshownbelow.
originalstatetoexceed1ms.Ifthelowvoltagestatedoesnotexceed1ms,theLVRwillignoreitanddonotperformaresetfunction.
·TheLVRusesthe²OR²functionwiththeexternal
RESsignaltoperformchipreset.
Note:
VOPRisthevoltagerangeforproperchipopera-tionat4MHzsystemclock.
LowVoltageReset
Note:
*1:Tomakesurethatthesystemoscillatorhasstabilized,theSSTprovidesanextradelayof1024system
clockpulsesbeforeenteringthenormaloperation.*2:Sincelowvoltagehastobemaintainedinitsoriginalstateandexceed1ms,therefore1msdelayentersthe
resetmode.
MouseHardwareWake-UpFunction
WhentheHT82K96EisusedforUSBmouseapplication,inordertodecreasethepowerconsumptionoftheHT82K96Einsuspendmode.TheHT82K96Ehasbuilt-inMouseHardwarewake-upfunction.OncetheHT82K96Ejumptosuspendmode,andtheHWKUPSB(bit7ofSCC)issetto1.TheHT82K96EwillautomaticallyswitchtheIRPTcontrolpin(PC0)anddetectmovementoftheX1,X2,Y1,Y2,Z1,Z2,correspondingto(PA0~PA5)andthestateofthefivebuttoncorrespondingtoPA6,PA7,PB6,PB7,andPD4.Oncetherearemousemovementorstatechange.TheHT82K96Ewillwake-uptheMCUbyI/Omethod,otherwisetheMCUisinsuspendmode.
HowlongtheHT82K96EtoturnontheIRPT,andthelowpulseperiodofthePC0isdefinedbybit0~3oftheWDTS(wake-upperiod)andthebit0~bit2oftheSCC(LED_onperiod)respectively.ThefollowingdiagramshowtheIRPTcontrolpintiming.
Rev.1.7018April22,2004
元器件交易网www.cecb2b.comHT82K96ESuspendWake-UpRemoteWake-Up
IfthereisnosignalonUSBbusisover3ms,theHT82K96Ewillgointosuspendmode.TheSuspendline(bit0ofUSC)willbesetto1andaUSBinterruptistriggeredtoindicatetheHT82K96Eshouldjumptosus-pendstatetomeetthe500mAUSBsuspendcurrentspec.
Inordertomeetthe500mAsuspendcurrent,thefirm-wareshoulddisabletheUSBclockbycleartheUSBCKEN(bit3oftheSCC)to²0².Thesuspendcur-rentisabout400mA.
Alsotheusercanfurtherdecreasethesuspendcurrentto250mAbysettheSUSP2(bit4oftheSCC).ButiftheSUSP2isset,theusermakesurecannotenabletheLVROPToption,otherwisetheHT82K96Ewillbereset.Whentheresumesignalissentoutbythehost,theHT82K96EwillwakeuptheMCUbyUSBinterruptandtheResumeline(bit3ofUSC)isset.InordertomakeHT82K96Eworkproperly,thefirmwaremustsettheUSBCKEN(bit3ofSCC)to1andcleartheSUSP2(bit4oftheSCC).SincetheResumesignalwillbeclearedbeforetheIdlesignalissentoutbythehostandtheSus-pendline(bit0ofUSC)isgoingto²0².SowhentheMCUisdetectingtheSuspendline(bit0ofUSC),theResumelineshouldberememberedandtokenintocon-sideration.
Afterfinishingtheresumesignal,thesuspendlinewillgoinactiveandaUSBinterruptistriggered.Thefollow-ingisthetimingdiagram
ToConfiguretheHT82K96EasPS2Device
TheHT82K96EcanbedefineasUSBinterfaceorPS2interfacebyconfiguringtheSPS2(bit4ofUSR)andSUSB(bit5ofUSR).IfSPS2=1,andSUSB=0,theHT82K96EisdefinedasPS2interface,pinUSBD-isnowdefinedasPS2DatapinandUSBD+isnowde-finedasPS2Clkpin.TheusercaneasytoreadorwritethePS2DataorPS2Clkpinbyaccessingthecorre-spondingbitPS2DAI(bit4ofUSC),PS2CKI(bit5ofUSC),PS2DAO(bit6ofUSC)andS2CKO(bit7ofUSC)respectively.
Theusershouldmakesurethatinordertoreadthedataproperly,thecorrespondingoutputbitmustsetto1.Forexample,ifitwanttoreadPS2DatabyreadingPS2DAI,thePS2DAOshouldsetto1.Otherwiseitalwaysread0.IfSPS2=0,andSUSB=1,theHT82K96EisdefinedasUSBinterface.BoththeUSBD-andUSBD+isdrivingbySIEoftheHT82K96E.TheuseronlywriteorreadtheUSBdatathroughthecorrespondingFIFO.BothSPS2andSUSBisdefault²0².ToConfiguretheADCBlock
TheHT82K96Ehasbuilt-ina8-bitA/Dconverterwith6channels(PB0~PB5).InordertomaketheA/Dcon-vertermoreflexibility,therearetwomode:ExternalRef-erencevoltageandInternalReferencevoltage.ItcaneasytoconfigurebysettingtheADREF(bit6ofUSR).ForExternalReferencevoltage,thereferencevoltageoftheA/DconvertercomesfromexternalPB6/VRLandPB7/VRHpins.Otherwise,thereferencevoltageiscomingfromtheVDDandVSSofMCU.
PB0~PB5isthe6-channelsinputoftheA/Dconverter,itcaneasytodefinewhichchannelisconvertingbycon-figuringACS2~ACS0(bit2~0ofADSC).AlsotherearefourconverterclocksourcetobeselectedbysettingADCS1(bit4ofADSC),ADCS0(bit3ofADSC).OncetheADON(bit6ofADSC)issetandsendthestartpulsethroughSTART(bit5ofADSC).TheA/Dcon-verterwillbeinoperation.ThereareEOCB(bit7ofADSC)toindicatewhethertheA/Dconverterisbusyornot.TheEOCBisclearwhentheconversioniscom-pleted.TheusercanreadtheconverterdatabyreadingtheregisterADR.Inordertomeet500uAsuspendcur-rentspec..TheusershoulddisabletheA/DbyclearingADONbeforejumptosuspendmode.
Thedevicewithremotewakeupfunctioncanwake-uptheUSBHostbysendingawake-uppulsethroughRMWK(bit1ofUSC).OncetheUSBHostreceivethewake-upsignalfromHT82K96E.itwillsendaResumesignaltodevice.Thetimingasfollow:
Rev.1.7019April22,2004
元器件交易网www.cecb2b.comHT82K96EThefollowingisA/Dconvertertimingdiagrams
USBInterfaceandA/DConverter
Thereare7registers,includingAWR(address+remotewakeup;42Hinbank1),STALL(43Hinbank1),PIPE(44Hinbank1),MISC(46Hinbank1),FIFO0(48Hinbank1),FIFO1(49Hinbank1),FIFO2(4AHinbank1)andFIFO3(4BHinbank1)usedfortheUSBfunction.AWRregistercontainscurrentaddressandaremotewakeupfunctioncontrolbit.TheinitialvalueofAWRis²00H².TheaddressvalueextractedfromtheUSBcommandhasnottobeloadedintothisregisteruntiltheSETUPstagebeingfinished.
AWRWKENAD6~AD0
Bits07~1
R/WWW
Remotewake-upenable/disableUSBdeviceaddress
Function
PIPEregisterrepresentswhetherthecorrespondingendpointisaccessedbyhostornot.Thisregisterissetonlyafterthetimewhenhostaccessesthecorrespondingendpoint.Onlythelastaccessedendpointisshowninthisregister.STALLregistershowswhetherthecorrespondingendpointworksproperlyornot.Assoonastheendpointworksim-properly,therelatedbitintheSTALLhastobesetto²1².TheSTALLwillbeclearedbyUSBresetsignal.
STALLSTL0STL1STL2STL3¾PIPEEP0RWEP1RWEP2RWEP3RW¾
Bits01237~4Bits01237~4
R/WWWWWWR/WRRRRR
Endpoint0accessedEndpoint1accessedEndpoint2accessedEndpoint3accessedUnusedbit,readas²0²Stalltheendpoint0Stalltheendpoint1Stalltheendpoint2Stalltheendpoint3Unusedbit,readas²0²
FunctionFunction
Rev.1.7020April22,2004
元器件交易网www.cecb2b.comHT82K96ESIES.Register(forversionCorlaterversion)isusedtoindicatethepresentsignalstatewhichtheSIEreceivesandalsodefineswhethertheSIEhastochangethedeviceaddressautomatically.
Bit7
Func.R/WReg_Adr
NMIR/W
Bit6EOTR
Bit5SetupR
Bit4NAKR
Bit3INR
Bit2OUTR/W
Bit1F0_ERRR/W
Bit0Adr_setR/W
01000101B
SIESRegisterTable
Func.NameR/WDescription
ThisbitisusedtoconfiguretheSIEtoautomaticallychangethedeviceaddresswiththevalueoftheAddress+Remote_WakeUpRegister(42H).
Whenthisbitissetto²1²byF/W,theSIEwillupdatethedeviceaddresswiththevalueoftheAddress+Remote_WakeUpRegister(42H)afterthePCHosthassuccessfullyreadthedatafromthedevicebytheINoperation.TheSIEwillclearthebitafterupdatingthedeviceaddress.Otherwise,whenthisbitisclearedto²0²,theSIEwillupdatethede-viceaddressimmediatelyafteranaddressiswrittentotheAddress+Remote_WakeUpRegister(42H)Default0
ThisbitisusedtoindicatethatsomeerrorshaveoccurredwhenaccessingtheFIFO0.ThisbitissetbySIEandclearedbyF/W.Default0
ThisbitisusedtoindicatethatanOUTtoken(exceptfortheOUTzerolength)hasbeenreceived.TheF/WclearthebitaftertheOUTdatahasbeenread.ThisbitwillalsobeclearedbytheSIEafterthenextvalidSETUPtokenisreceived.Default0
ThisbitisusedtoindicatethatthecurrentsignaltheUSBisreceivingfromthePCHostisINtoken.
ThisbitisusedtoindicatethattheSIEistransmittingNAKsignaltotheHostinresponsetothePCHostINorOUTtoken.
Thisbitindicatesthatthecurrenttokenissetuptoken.Don¢tcareCRCorEOPerrorofthesetuptoken,thisbithasbesetto²1².Whensuspend=¢1¢&setup=¢1¢,itindicatesthatsomethingiswrongintheUSBInterface.Firmwarein-chargemusttodosomethingtosavethedeviceandkeepitingoodcondition.
Endoftransactionflag,normalstatusis1.Ifsuspend=¢1¢line&=¢0¢indicatesthatsome-thingiswrongintheUSBInterface.Firmwarein-chargemusttodosomethingtosavethedeviceandkeepitingoodcondition.
ThisbitisusedtocontrolwhethertheUSBinterruptisoutputtotheMCUinNAKre-sponsetothePCHostINorOUTtoken.
1:onlyhasUSBinterrupt,dataistransmittedtothePChostordataisreceivedfromthePCHost
0:alwayshasUSBinterruptiftheUSBaccessesFIFO0Default0
SIESFunctionTable
Adr_setR/W
F0_ErrR/W
OutR/W
INNAK
RR
SetupR
EOTR
NMIR/W
Rev.1.7021April22,2004
元器件交易网www.cecb2b.comHT82K96EMISCregistercombinesacommandandstatustocontroldesiredendpointFIFOactionandtoshowthestatusofwantedendpointFIFO.TheMISCwillbeclearedbyUSBresetsignal.
MISCREQ
Bits0
R/W
Function
AftersettingotherstatusofdesiredoneintheMISC,endpointFIFOcanbere-R/Wquestedbysettingthisbitto²1².Afterjobhasbeendone,thisbithastobeclearedto
²0²ThisbitdefinesthedirectionofdatatransferringbetweenMCUandendpointFIFO.WhentheTXissetto²1²,thismeansthatMCUwantstowritedatatoendpointFIFO.Afterthejobhasbeendone,thisbithastobeclearedto²0²beforeterminat-R/W
ingrequesttorepresentendoftransferring.Forreadingaction,thisbithastobeclearedto²0²torepresentthatMCUwantstoreaddatafromendpointFIFOandhastobesetto²1²afterthejobdone.R/WCleartherequestedendpointFIFO,eventheendpointFIFOisnotready.TodefinewhichendpointFIFOisselected,SELP1,SELP0:00:endpointFIFO0R/W01:endpointFIFO1
10:endpointFIFO211:endpointFIFO3
ItisusedtoshowthatthedatainendpointFIFOisSETUPcommand.ThisbithastoR/Wbeclearedbyfirmware.Thatistosay,eventheMCUisbusing,thedevicewillnot
missanySETUPcommandsfromhost.RR/W
Readonlystatusbit,thisbitisusedtoindicatethatthedesiredendpointFIFOisreadytowork.
Itisusedtoindicatethata0-sizedpacketissentfromhosttoMCU.Thisbitshouldbeclearedbyfirmware.
TX1
CLEAR2
SELP1SELP043
SCMD5
READYLEN0
67
MCUcancommunicatewithendpointFIFObysettingthecorrespondingregisters,ofwhichaddressislistedinthefol-lowingtable.Afterreadingcurrentdata,nextdatawillshowonafter2ms.usingtocheckendpointFIFOstatusandre-sponsetoMSICregister,ifread/writeactionisstillgoingon.
RegistersFIFO0FIFO1FIFO2FIFO3
R/WR/WR/WR/WR/W
Bank1111
Address48H49H4AH4BH
Bit7~Bit0Data7~Data0Data7~Data0Data7~Data0Data7~Data0
Therearesometimingconstrainsandusagesillustratedhere.BysettingtheMISCregister,MCUcanperformreading,writingandclearingactions.TherearesomeexamplesshowninthefollowingtableforendpointFIFOreading,writingandclearing.
Actions
ReadFIFO0sequenceWriteFIFO1sequence
CheckwhetherFIFO0canbereadornotCheckwhetherFIFO1canbewrittenornotRead0-sizedpacketsequenceformFIFO0Write0-sizedpacketsequencetoFIFO1Note:
MiSCSettingFlowandStatus
00H®01H®delay2ms,check41H®read*fromFIFO0registerandchecknotready(01H)®03H®02H
0AH®0BH®delay2ms,check4BH®write*toFIFO1registerandchecknotready(0BH)®09H®08H
00H®01H®delay2ms,check41H(ready)or01H(notready)®00H0AH®0BH®delay2ms,check4BH(ready)or0BH(notready)®0AH00H®01H®delay2ms,check81H®readonce(01H)®03H®02H0AH®0BH®delay2ms,check0BH®0FH®0DH®08H
*:Thereare2msexistingbetween2readingactionorbetween2writingaction
Rev.1.7022April22,2004
元器件交易网www.cecb2b.comHT82K96EThedefinitionsoftheUSB/PS2statusandcontrolregister(USC;1AH)areasshown.
USCSUSP
Bits0
R/WR
Function
Readonly,USBsuspendindication.Whenthisbitissetto²1²(setbySIE),itindi-catestheUSBbusenterssuspendmode.TheUSBinterruptisalsotriggeredonanychangingofthisbit.
USBremotewakeupcommand.ItissetbyMCUtoforcetheUSBhostleavingthesuspendmode.Whenthisbitissetto²1²,2msdelayforclearingthisbitto²0²isneededtoinsuretheRMWKcommandisacceptedbySIE.
RMWK1W
URST2
USBresetindication.Thisbitisset/clearedbyUSBSIE.Thisbitisusedtodetectwhichbus(PS2orUSB)isattached.WhentheURSTissetto²1²,thisindicatesanR/W
USBresetisoccurred(TheattachedbusisUSB)andanUSBinterruptwillbeinitial-ized.
USBresumeindication.WhentheUSBleavessuspendmode,thisbitissetto²1²(setbySIE).Thisbitwillappear20mswaitingforMCUtodetect.WhentheRE-SUMEissetbySIE,aninterruptwillbegeneratedtowake-uptheMCU.Inordertodetectingthesuspendstate,MCUshouldsetUSBCKENandclearSUSP2(inSCCregister)toenabletheSIEdetectingfunction.TheRESUMEwillbeclearedwhiletheSUSPisgoing²0².WhenMCUisdetectingtheSUSP,theRESUME(causesMCUtowake-up)shouldberememberedandtokenintoconsideration.Readonly,USBD-/DATAinputReadonly,USBD+/CLKinput
DatafordrivingUSBD-/DATApinwhenworkunder3DPS2mousefunction.(Default=²1²)
DatafordrivingUSBD+/CLKpinwhenworkunder3DPS2mousefunction.(Default=²1²)
RESUME3R
PS2DAIPS2CKIPS2DAOPS2CKO
4567
RRWW
TheUSR(USBendpointinterruptstatusregister)registerisusedtoindicatewhichendpointisaccessedandtoselectserialbus(PS2orUSB)andA/Dconverteroperationmodes.Theendpointrequestflags(EP0IF,EP1IF,EP2IFandEP3IF)areusedtoindicatewhichendpointsareaccessed.Ifanendpointisaccessed,therelatedendpointrequestflagwillbesetto²1²andtheUSBinterruptwilloccur(ifUSBinterruptisenabledandthestackisnotfull).Whentheac-tiveendpointrequestflagisserved,theendpointrequestflaghastobeclearedto²0².
USREP0IF
Bits0
R/W
Function
Whenthisbitissetto²1²(setbySIE),itindicatestheendpoint0isaccessedandanR/WUSBinterruptwilloccur.Whentheinterrupthasbeenserved,thisbitshouldbe
clearedbyfirmware.Whenthisbitissetto²1²(setbySIE),itindicatestheendpoint1isaccessedandanR/WUSBinterruptwilloccur.Whentheinterrupthasbeenserved,thisbitshouldbe
clearedbyfirmware.Whenthisbitissetto²1²(setbySIE),itindicatestheendpoint2isaccessedandanR/WUSBinterruptwilloccur.Whentheinterrupthasbeenserved,thisbitshouldbe
clearedbyfirmware.Whenthisbitissetto²1²(setbySIE),itindicatestheendpoint3isaccessedandanR/WUSBinterruptwilloccur.Whentheinterrupthasbeenserved,thisbitshouldbe
clearedbyfirmware.R/WThePS2functionisselectedwhenthisbitissetto²1².(Default=²0²)R/WTheUSBfunctionisselectedwhenthisbitissetto²1².(Default=²0²)
ThereferencevoltageofA/DconverteriscomingfromtheVDDandVSSofMCUR/Wwhenthisbitisset²1².Otherwise,thereferencevoltageofA/Dconvertercomes
fromexternalPB6/VRLandPB7/VRHpins.(Default=²1²)W
ForICEonly,0forFIFOread(Default=²0²);1forFIFOwrite
EP1IF1
EP2IF2
EP3IFSPS2SUSBADREFFIFO-cntl
34567
Rev.1.7023April22,2004
元器件交易网www.cecb2b.comHT82K96EThereisasystemclockcontrolregisterimplementedtoselecttheclockusedintheMCU.ThisregisterconsistsofUSBclockcontrolbit(USBCKEN),secondsuspendmodecontrolbit(SUSP2)andsystemclockselection(SYSCLK).
SCC
Bits
R/W
Function
Led_onPeriod2~0
TodefinelowpulseperiodofIRPT(PC0)formousehardwarefunction.Thetimebaseis31.25ms(1/32kHz).Defaultvalueis000.000:2´base001:3´baseR/W
010:5´base011:9´base100:17´base101:33´base110:65´base111:127´baseR/W
USBclockcontrolbit.Whenthisbitissetto²1²,itindicatesthattheUSBclockisen-abled.Otherwise,theUSBclockisturned-off.(Default=²0²)
USBCKEN3
SUSP2¾SYSCLK
456
Thisbitisusedfordecreasingpowerconsumptioninsuspendmode.R/WInnormalmodecleanthisbit=0(Default=²0²)
InHALTmodesetthisbit=1fordecreasingpowerconsumption.R/WUndefined,shouldbeclearedto²0²
ThisbitisusedtospecifythesystemoscillatorfrequencyusedbyMCU.Ifa6MHzR/Wcrystaloscillatororresonatorisused,thisbitshouldbesetto²1².Ifa12MHzcrystal
oscillatororresonatorisused,thisbitshouldbeclearedto²0²(default).HardwareHALTmodewake-updetectcircuitactiveunderpowerdownmode.Lowactive.
R/W²0²:WDTtimeroverflowwillwake-upMCUsystem
²1²:WDTtimeroverflowwillstarthardwarewake-updetectcircuitbutnotwake-upMCUsystem.
HWKUPSB7
TheA/DconverterimplementedintheMCUisa6-channel8-bitA/Dconverter.Thereferencevoltage(highreferencevoltageandlowreferencevoltage)canbeselectedascomingfromexternalpins(PB6/VRLandPB7/VRH)orinternalpowersuppliesofMCU(VDDandVSS).TheVRLandVRHareusedtosettheminimalandmaximalboundariesofthefull-scalerangeoftheA/Dconverter.Ifananaloginputs,VRLorVRHisnotusedforA/Dconversion,italsocanbeusedasageneralpurposeI/Oline.TheADSC(A/Dconverterstatusandcontrolregister)registerisusedtosettheconfigu-rationsandA/DclocksourcesofA/DconverterandcontroltheoperationofA/Dconverter.
ADSC
Bits
Function
These3bitsareusetoselectoneofeightA/Dconverterchannelsfortheconversion.TheA/DconverterinputchannelsAN0~AN5arepin-sharedwithPB0~PB5.PB6/VRLandPB7/VRHareusedfortheA/Dconverterreferenceinputs.ACS2,ACS1,ACS0:000/001/010/011/100/101/110/111:AN0/AN1/AN2/AN3/AN4/AN5/VRL/VRHA/Dconverterclocksourceselection.ADCS1,ADCS0:00:6MHz01:3MHz10:1.5MHz11:0.75MHz
StarttheA/Dconversion.(0®1®0:start,0®1:resetA/DconverterandA/Ddataregister)Thisbitisusedtocontroltheenable/disableofA/Dconvertercircuit.Ifthisbitissetto²1²theA/Dconverterentersoperatingmode.Otherwise,theA/Dconverterwillbeturned-offEndofA/Dconversionindication.(0:endofA/Dconversion)
ACS2~ACS02~0
ADCS1ADCS043
STARTADONEOCB
567
TheA/DconverterdataregisterisusedtostoretheresultofA/Dconversion.
ADRD7~D0
Bits7~0
ResultofA/Dconversion
Function
Rev.1.7024April22,2004
元器件交易网www.cecb2b.comHT82K96EMaskOptions
Thefollowingtableshowsallkindsofmaskoptioninthemicrocontroller.Allofthemaskoptionsmustbedefinedtoen-surepropersystemfunctioning.
No.12345678910111213
Chiplockbit(bybit)
PA0~PA7pull-highresistorenabled/disabled(bybit)PA0~PA5pulldownresistorenabled/disabled(bybit)PB0~PB7pull-highresistorenabled/disabled(bynibble)PC0~PC7pull-highresistorenabled/disabled(bynibble)PD0~PD7pull-highresistorenabled/disabled(bynibble)LVRenable/disableWDTenable/disable
WDTclocksource:fSYS/4orWDTOSC²CLRWDT²instruction(s):1or2
PA0~PA7outputstructures:CMOS/NMOSopen-drain/PMOSopen-drain(bybit)PA0~PA7wake-upenabled/disabled(bybit)A/Dconverterenabled/disabled
Option
ApplicationCircuits
CrystalorCeramicResonatorforMultipleI/OApplications
Note:
TheresistanceandcapacitanceforresetcircuitshouldbedesignedinsuchawayastoensurethattheVDDisstableandremainswithinavalidoperatingvoltagerangebeforebringingREStohigh.X1canuse6MHzor12MHz,X1ascloseOSC1&OSC2aspossibleComponentswith*areusedforEMCissue.Componentswith**areusedforresonatoronly.
Rev.1.7025April22,2004
元器件交易网www.cecb2b.comHT82K96EInstructionSetSummary
MnemonicArithmeticADDA,[m]ADDMA,[m]ADDA,xADCA,[m]ADCMA,[m]SUBA,xSUBA,[m]SUBMA,[m]SBCA,[m]SBCMA,[m]DAA[m]
AdddatamemorytoACCAddACCtodatamemoryAddimmediatedatatoACC
AdddatamemorytoACCwithcarryAddACCtodatamemorywithcarrySubtractimmediatedatafromACCSubtractdatamemoryfromACC
SubtractdatamemoryfromACCwithresultindatamemorySubtractdatamemoryfromACCwithcarry
SubtractdatamemoryfromACCwithcarryandresultindatamemoryDecimaladjustACCforadditionwithresultindatamemory
11(1)111(1)111(1)11(1)1(1)
Z,C,AC,OVZ,C,AC,OVZ,C,AC,OVZ,C,AC,OVZ,C,AC,OVZ,C,AC,OVZ,C,AC,OVZ,C,AC,OVZ,C,AC,OVZ,C,AC,OV
C
Description
InstructionCycle
FlagAffected
LogicOperationANDA,[m]ORA,[m]XORA,[m]ANDMA,[m]ORMA,[m]XORMA,[m]ANDA,xORA,xXORA,xCPL[m]CPLA[m]
ANDdatamemorytoACCORdatamemorytoACC
Exclusive-ORdatamemorytoACCANDACCtodatamemoryORACCtodatamemory
Exclusive-ORACCtodatamemoryANDimmediatedatatoACCORimmediatedatatoACC
Exclusive-ORimmediatedatatoACCComplementdatamemory
ComplementdatamemorywithresultinACC
1111(1)1(1)1(1)1111(1)1
ZZZZZZZZZZZ
Increment&DecrementINCA[m]INC[m]DECA[m]DEC[m]RotateRRA[m]RR[m]RRCA[m]RRC[m]RLA[m]RL[m]RLCA[m]RLC[m]DataMoveMOVA,[m]MOV[m],AMOVA,xBitOperationCLR[m].iSET[m].i
ClearbitofdatamemorySetbitofdatamemory
1(1)1(1)
NoneNone
MovedatamemorytoACCMoveACCtodatamemoryMoveimmediatedatatoACC
11(1)1
NoneNoneNone
RotatedatamemoryrightwithresultinACCRotatedatamemoryright
RotatedatamemoryrightthroughcarrywithresultinACCRotatedatamemoryrightthroughcarryRotatedatamemoryleftwithresultinACCRotatedatamemoryleft
RotatedatamemoryleftthroughcarrywithresultinACCRotatedatamemoryleftthroughcarry
11(1)11(1)11(1)11(1)
NoneNoneCCNoneNoneCC
IncrementdatamemorywithresultinACCIncrementdatamemory
DecrementdatamemorywithresultinACCDecrementdatamemory
11(1)11(1)
ZZZZ
Rev.1.7026April22,2004
元器件交易网www.cecb2b.comHT82K96EMnemonicBranchJMPaddrSZ[m]SZA[m]SZ[m].iSNZ[m].iSIZ[m]SDZ[m]SIZA[m]SDZA[m]CALLaddrRETRETA,xRETITableReadTABRDC[m]TABRDL[m]MiscellaneousNOPCLR[m]SET[m]CLRWDTCLRWDT1CLRWDT2SWAP[m]SWAPA[m]HALTNote:
Nooperation
CleardatamemorySetdatamemory
ClearWatchdogTimerPre-clearWatchdogTimerPre-clearWatchdogTimerSwapnibblesofdatamemory
SwapnibblesofdatamemorywithresultinACCEnterpowerdownmode
11(1)1(1)1111(1)11
NoneNoneNoneTO,PDFTO(4),PDF(4)TO(4),PDF(4)
NoneNoneTO,PDF
ReadROMcode(currentpage)todatamemoryandTBLHReadROMcode(lastpage)todatamemoryandTBLH
2(1)2(1)
NoneNone
Jumpunconditionally
Skipifdatamemoryiszero
SkipifdatamemoryiszerowithdatamovementtoACCSkipifbitiofdatamemoryiszeroSkipifbitiofdatamemoryisnotzeroSkipifincrementdatamemoryiszeroSkipifdecrementdatamemoryiszero
SkipifincrementdatamemoryiszerowithresultinACCSkipifdecrementdatamemoryiszerowithresultinACCSubroutinecall
Returnfromsubroutine
ReturnfromsubroutineandloadimmediatedatatoACCReturnfrominterrupt
21(2)1(2)1(2)1(2)1(3)1(3)1(2)1(2)2222
NoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNone
Description
InstructionCycle
FlagAffected
x:Immediatedatam:DatamemoryaddressA:Accumulatori:0~7numberofbits
addr:ProgrammemoryaddressÖ:Flagisaffected-:Flagisnotaffected
(1)
:IfaloadingtothePCLregisteroccurs,theexecutioncycleofinstructionswillbedelayedforonemorecycle(foursystemclocks).
:Ifaskippingtothenextinstructionoccurs,theexecutioncycleofinstructionswillbedelayedforonemorecycle(foursystemclocks).Otherwisetheoriginalinstructioncycleisunchanged.:
and(2)
:Theflagsmaybeaffectedbytheexecutionstatus.IftheWatchdogTimerisclearedbyexecutingthe²CLRWDT1²or²CLRWDT2²instruction,theTOandPDFarecleared.OtherwisetheTOandPDFflagsremainunchanged.
(2)
(3)(1)(4)
Rev.1.7027April22,2004
元器件交易网www.cecb2b.comHT82K96EInstructionDefinition
ADCA,[m]DescriptionOperationAffectedflag(s)
TO¾
ADCMA,[m]DescriptionOperationAffectedflag(s)
TO¾
ADDA,[m]DescriptionOperationAffectedflag(s)
TO¾
ADDA,xDescriptionOperationAffectedflag(s)
TO¾
ADDMA,[m]DescriptionOperationAffectedflag(s)
TO¾
PDF¾
OVÖ
ZÖ
ACÖ
CÖ
PDF¾
OVÖ
ZÖ
ACÖ
CÖ
PDF¾
OVÖ
ZÖ
ACÖ
CÖ
PDF¾
OVÖ
ZÖ
ACÖ
CÖ
PDF¾
OVÖ
ZÖ
ACÖ
CÖ
Adddatamemoryandcarrytotheaccumulator
Thecontentsofthespecifieddatamemory,accumulatorandthecarryflagareaddedsi-multaneously,leavingtheresultintheaccumulator.ACC¬ACC+[m]+C
Addtheaccumulatorandcarrytodatamemory
Thecontentsofthespecifieddatamemory,accumulatorandthecarryflagareaddedsi-multaneously,leavingtheresultinthespecifieddatamemory.[m]¬ACC+[m]+C
Adddatamemorytotheaccumulator
Thecontentsofthespecifieddatamemoryandtheaccumulatorareadded.Theresultisstoredintheaccumulator.ACC¬ACC+[m]
Addimmediatedatatotheaccumulator
Thecontentsoftheaccumulatorandthespecifieddataareadded,leavingtheresultintheaccumulator.ACC¬ACC+x
Addtheaccumulatortothedatamemory
Thecontentsofthespecifieddatamemoryandtheaccumulatorareadded.Theresultisstoredinthedatamemory.[m]¬ACC+[m]
Rev.1.7028April22,2004
元器件交易网www.cecb2b.comHT82K96EANDA,[m]DescriptionOperationAffectedflag(s)
TO¾
ANDA,xDescriptionOperationAffectedflag(s)
TO¾
ANDMA,[m]DescriptionOperationAffectedflag(s)
TO¾
CALLaddrDescription
PDF¾
OV¾
ZÖ
AC¾
C¾
PDF¾
OV¾
ZÖ
AC¾
C¾
PDF¾
OV¾
ZÖ
AC¾
C¾
LogicalANDaccumulatorwithdatamemory
Dataintheaccumulatorandthespecifieddatamemoryperformabitwiselogical_ANDop-eration.Theresultisstoredintheaccumulator.ACC¬ACC²AND²[m]
LogicalANDimmediatedatatotheaccumulator
Dataintheaccumulatorandthespecifieddataperformabitwiselogical_ANDoperation.Theresultisstoredintheaccumulator.ACC¬ACC²AND²x
LogicalANDdatamemorywiththeaccumulator
Datainthespecifieddatamemoryandtheaccumulatorperformabitwiselogical_ANDop-eration.Theresultisstoredinthedatamemory.[m]¬ACC²AND²[m]
Subroutinecall
Theinstructionunconditionallycallsasubroutinelocatedattheindicatedaddress.Theprogramcounterincrementsoncetoobtaintheaddressofthenextinstruction,andpushesthisontothestack.Theindicatedaddressisthenloaded.Programexecutioncontinueswiththeinstructionatthisaddress.Stack¬PC+1PC¬addr
OperationAffectedflag(s)
TO¾
CLR[m]DescriptionOperationAffectedflag(s)
TO¾
PDF¾
OV¾
Z¾
AC¾
C¾
Cleardatamemory
Thecontentsofthespecifieddatamemoryareclearedto0.[m]¬00H
PDF¾
OV¾
Z¾
AC¾
C¾
Rev.1.7029April22,2004
元器件交易网www.cecb2b.comHT82K96ECLR[m].iDescriptionOperationAffectedflag(s)
TO¾
CLRWDTDescriptionOperationAffectedflag(s)
TO0
CLRWDT1Description
PDF0
OV¾
Z¾
AC¾
C¾
PDF¾
OV¾
Z¾
AC¾
C¾
Clearbitofdatamemory
Thebitiofthespecifieddatamemoryisclearedto0.[m].i¬0
ClearWatchdogTimer
TheWDTiscleared(clearstheWDT).Thepowerdownbit(PDF)andtime-outbit(TO)arecleared.
WDT¬00H
PDFandTO¬0
PreclearWatchdogTimer
TogetherwithCLRWDT2,clearstheWDT.PDFandTOarealsocleared.Onlyexecutionofthisinstructionwithouttheotherpreclearinstructionjustsetstheindicatedflagwhichim-pliesthisinstructionhasbeenexecutedandtheTOandPDFflagsremainunchanged.WDT¬00H*
PDFandTO¬0*
OperationAffectedflag(s)
TO0*
CLRWDT2Description
PDF0*
OV¾
Z¾
AC¾
C¾
PreclearWatchdogTimer
TogetherwithCLRWDT1,clearstheWDT.PDFandTOarealsocleared.Onlyexecutionofthisinstructionwithouttheotherpreclearinstruction,setstheindicatedflagwhichim-pliesthisinstructionhasbeenexecutedandtheTOandPDFflagsremainunchanged.WDT¬00H*
PDFandTO¬0*
OperationAffectedflag(s)
TO0*
CPL[m]DescriptionOperationAffectedflag(s)
TO¾
PDF0*
OV¾
Z¾
AC¾
C¾
Complementdatamemory
Eachbitofthespecifieddatamemoryislogicallycomplemented(1¢scomplement).Bitswhichpreviouslycontaineda1arechangedto0andvice-versa.[m]¬[m]
PDF¾
OV¾
ZÖ
AC¾
C¾
Rev.1.7030April22,2004
元器件交易网www.cecb2b.comHT82K96ECPLA[m]Description
Complementdatamemoryandplaceresultintheaccumulator
Eachbitofthespecifieddatamemoryislogicallycomplemented(1¢scomplement).Bitswhichpreviouslycontaineda1arechangedto0andvice-versa.Thecomplementedresultisstoredintheaccumulatorandthecontentsofthedatamemoryremainunchanged.ACC¬[m]
OperationAffectedflag(s)
TO¾
DAA[m]Description
PDF¾
OV¾
ZÖ
AC¾
C¾
Decimal-Adjustaccumulatorforaddition
TheaccumulatorvalueisadjustedtotheBCD(BinaryCodedDecimal)code.Theaccumu-latorisdividedintotwonibbles.EachnibbleisadjustedtotheBCDcodeandaninternalcarry(AC1)willbedoneifthelownibbleoftheaccumulatorisgreaterthan9.TheBCDad-justmentisdonebyadding6totheoriginalvalueiftheoriginalvalueisgreaterthan9oracarry(ACorC)isset;otherwisetheoriginalvalueremainsunchanged.Theresultisstoredinthedatamemoryandonlythecarryflag(C)maybeaffected.IfACC.3~ACC.0>9orAC=1
then[m].3~[m].0¬(ACC.3~ACC.0)+6,AC1=ACelse[m].3~[m].0¬(ACC.3~ACC.0),AC1=0and
IfACC.7~ACC.4+AC1>9orC=1
then[m].7~[m].4¬ACC.7~ACC.4+6+AC1,C=1else[m].7~[m].4¬ACC.7~ACC.4+AC1,C=C
Operation
Affectedflag(s)
TO¾
DEC[m]DescriptionOperationAffectedflag(s)
TO¾
DECA[m]DescriptionOperationAffectedflag(s)
TO¾
PDF¾
OV¾
ZÖ
AC¾
C¾
PDF¾
OV¾
ZÖ
AC¾
C¾
PDF¾
OV¾
Z¾
AC¾
CÖ
Decrementdatamemory
Datainthespecifieddatamemoryisdecrementedby1.[m]¬[m]-1
Decrementdatamemoryandplaceresultintheaccumulator
Datainthespecifieddatamemoryisdecrementedby1,leavingtheresultintheaccumula-tor.Thecontentsofthedatamemoryremainunchanged.ACC¬[m]-1
Rev.1.7031April22,2004
元器件交易网www.cecb2b.comHT82K96EHALTDescription
Enterpowerdownmode
Thisinstructionstopsprogramexecutionandturnsoffthesystemclock.ThecontentsoftheRAMandregistersareretained.TheWDTandprescalerarecleared.Thepowerdownbit(PDF)issetandtheWDTtime-outbit(TO)iscleared.PC¬PC+1PDF¬1TO¬0
Operation
Affectedflag(s)
TO0
INC[m]DescriptionOperationAffectedflag(s)
TO¾
INCA[m]DescriptionOperationAffectedflag(s)
TO¾
JMPaddrDescriptionOperationAffectedflag(s)
TO¾
MOVA,[m]DescriptionOperationAffectedflag(s)
TO¾
PDF¾
OV¾
Z¾
AC¾
C¾
PDF¾
OV¾
Z¾
AC¾
C¾
Directlyjump
Theprogramcounterarereplacedwiththedirectly-specifiedaddressunconditionally,andcontrolispassedtothisdestination.PC¬addr
PDF¾
OV¾
ZÖ
AC¾
C¾
PDF¾
OV¾
ZÖ
AC¾
C¾
PDF1
OV¾
Z¾
AC¾
C¾
Incrementdatamemory
Datainthespecifieddatamemoryisincrementedby1[m]¬[m]+1
Incrementdatamemoryandplaceresultintheaccumulator
Datainthespecifieddatamemoryisincrementedby1,leavingtheresultintheaccumula-tor.Thecontentsofthedatamemoryremainunchanged.ACC¬[m]+1
Movedatamemorytotheaccumulator
Thecontentsofthespecifieddatamemoryarecopiedtotheaccumulator.ACC¬[m]
Rev.1.7032April22,2004
元器件交易网www.cecb2b.comHT82K96EMOVA,xDescriptionOperationAffectedflag(s)
TO¾
MOV[m],ADescriptionOperationAffectedflag(s)
TO¾
NOPDescriptionOperationAffectedflag(s)
TO¾
ORA,[m]DescriptionOperationAffectedflag(s)
TO¾
ORA,xDescriptionOperationAffectedflag(s)
TO¾
ORMA,[m]DescriptionOperationAffectedflag(s)
TO¾
PDF¾
OV¾
ZÖ
AC¾
C¾
PDF¾
OV¾
ZÖ
AC¾
C¾
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Nooperation
Nooperationisperformed.Executioncontinueswiththenextinstruction.PC¬PC+1
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Moveimmediatedatatotheaccumulator
The8-bitdataspecifiedbythecodeisloadedintotheaccumulator.ACC¬x
Movetheaccumulatortodatamemory
Thecontentsoftheaccumulatorarecopiedtothespecifieddatamemory(oneofthedatamemories).[m]¬ACC
LogicalORaccumulatorwithdatamemory
Dataintheaccumulatorandthespecifieddatamemory(oneofthedatamemories)per-formabitwiselogical_ORoperation.Theresultisstoredintheaccumulator.ACC¬ACC²OR²[m]
LogicalORimmediatedatatotheaccumulator
Dataintheaccumulatorandthespecifieddataperformabitwiselogical_ORoperation.Theresultisstoredintheaccumulator.ACC¬ACC²OR²x
LogicalORdatamemorywiththeaccumulator
Datainthedatamemory(oneofthedatamemories)andtheaccumulatorperformabitwiselogical_ORoperation.Theresultisstoredinthedatamemory.[m]¬ACC²OR²[m]
Rev.1.7033April22,2004
元器件交易网www.cecb2b.comHT82K96ERETDescriptionOperationAffectedflag(s)
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RETA,xDescriptionOperationAffectedflag(s)
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RETIDescriptionOperationAffectedflag(s)
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RL[m]DescriptionOperationAffectedflag(s)
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RLA[m]DescriptionOperationAffectedflag(s)
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Returnfromsubroutine
Theprogramcounterisrestoredfromthestack.Thisisa2-cycleinstruction.PC¬Stack
Returnandplaceimmediatedataintheaccumulator
Theprogramcounterisrestoredfromthestackandtheaccumulatorloadedwiththespeci-fied8-bitimmediatedata.PC¬StackACC¬x
Returnfrominterrupt
Theprogramcounterisrestoredfromthestack,andinterruptsareenabledbysettingtheEMIbit.EMIistheenablemaster(global)interruptbit.PC¬StackEMI¬1
Rotatedatamemoryleft
Thecontentsofthespecifieddatamemoryarerotated1bitleftwithbit7rotatedintobit0.[m].(i+1)¬[m].i;[m].i:bitiofthedatamemory(i=0~6)[m].0¬[m].7
Rotatedatamemoryleftandplaceresultintheaccumulator
Datainthespecifieddatamemoryisrotated1bitleftwithbit7rotatedintobit0,leavingtherotatedresultintheaccumulator.Thecontentsofthedatamemoryremainunchanged.ACC.(i+1)¬[m].i;[m].i:bitiofthedatamemory(i=0~6)ACC.0¬[m].7
Rev.1.7034April22,2004
元器件交易网www.cecb2b.comHT82K96ERLC[m]DescriptionOperation
Rotatedatamemoryleftthroughcarry
Thecontentsofthespecifieddatamemoryandthecarryflagarerotated1bitleft.Bit7re-placesthecarrybit;theoriginalcarryflagisrotatedintothebit0position.[m].(i+1)¬[m].i;[m].i:bitiofthedatamemory(i=0~6)[m].0¬CC¬[m].7
Affectedflag(s)
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RLCA[m]Description
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Rotateleftthroughcarryandplaceresultintheaccumulator
Datainthespecifieddatamemoryandthecarryflagarerotated1bitleft.Bit7replacesthecarrybitandtheoriginalcarryflagisrotatedintobit0position.Therotatedresultisstoredintheaccumulatorbutthecontentsofthedatamemoryremainunchanged.ACC.(i+1)¬[m].i;[m].i:bitiofthedatamemory(i=0~6)ACC.0¬CC¬[m].7
Operation
Affectedflag(s)
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RR[m]DescriptionOperationAffectedflag(s)
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RRA[m]DescriptionOperationAffectedflag(s)
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RRC[m]DescriptionOperation
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Rotatedatamemoryright
Thecontentsofthespecifieddatamemoryarerotated1bitrightwithbit0rotatedtobit7.[m].i¬[m].(i+1);[m].i:bitiofthedatamemory(i=0~6)[m].7¬[m].0
Rotaterightandplaceresultintheaccumulator
Datainthespecifieddatamemoryisrotated1bitrightwithbit0rotatedintobit7,leavingtherotatedresultintheaccumulator.Thecontentsofthedatamemoryremainunchanged.ACC.(i)¬[m].(i+1);[m].i:bitiofthedatamemory(i=0~6)ACC.7¬[m].0
Rotatedatamemoryrightthroughcarry
Thecontentsofthespecifieddatamemoryandthecarryflagaretogetherrotated1bitright.Bit0replacesthecarrybit;theoriginalcarryflagisrotatedintothebit7position.[m].i¬[m].(i+1);[m].i:bitiofthedatamemory(i=0~6)[m].7¬CC¬[m].0
Affectedflag(s)
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Rev.1.70
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April22,2004
元器件交易网www.cecb2b.comHT82K96ERRCA[m]Description
Rotaterightthroughcarryandplaceresultintheaccumulator
Dataofthespecifieddatamemoryandthecarryflagarerotated1bitright.Bit0replacesthecarrybitandtheoriginalcarryflagisrotatedintothebit7position.Therotatedresultisstoredintheaccumulator.Thecontentsofthedatamemoryremainunchanged.ACC.i¬[m].(i+1);[m].i:bitiofthedatamemory(i=0~6)ACC.7¬CC¬[m].0
Operation
Affectedflag(s)
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SBCA,[m]DescriptionOperationAffectedflag(s)
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SBCMA,[m]DescriptionOperationAffectedflag(s)
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SDZ[m]Description
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Subtractdatamemoryandcarryfromtheaccumulator
Thecontentsofthespecifieddatamemoryandthecomplementofthecarryflagaresub-tractedfromtheaccumulator,leavingtheresultintheaccumulator.ACC¬ACC+[m]+C
Subtractdatamemoryandcarryfromtheaccumulator
Thecontentsofthespecifieddatamemoryandthecomplementofthecarryflagaresub-tractedfromtheaccumulator,leavingtheresultinthedatamemory.[m]¬ACC+[m]+C
Skipifdecrementdatamemoryis0
Thecontentsofthespecifieddatamemoryaredecrementedby1.Iftheresultis0,thenextinstructionisskipped.Iftheresultis0,thefollowinginstruction,fetchedduringthecurrentinstructionexecution,isdiscardedandadummycycleisreplacedtogettheproperinstruc-tion(2cycles).Otherwiseproceedwiththenextinstruction(1cycle).Skipif([m]-1)=0,[m]¬([m]-1)
OperationAffectedflag(s)
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SDZA[m]Description
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DecrementdatamemoryandplaceresultinACC,skipif0
Thecontentsofthespecifieddatamemoryaredecrementedby1.Iftheresultis0,thenextinstructionisskipped.Theresultisstoredintheaccumulatorbutthedatamemoryremainsunchanged.Iftheresultis0,thefollowinginstruction,fetchedduringthecurrentinstructionexecution,isdiscardedandadummycycleisreplacedtogettheproperinstruction(2cy-cles).Otherwiseproceedwiththenextinstruction(1cycle).Skipif([m]-1)=0,ACC¬([m]-1)
OperationAffectedflag(s)
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Rev.1.7036April22,2004
元器件交易网www.cecb2b.comHT82K96ESET[m]DescriptionOperationAffectedflag(s)
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SET[m].iDescriptionOperationAffectedflag(s)
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SIZ[m]Description
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Setdatamemory
Eachbitofthespecifieddatamemoryissetto1.[m]¬FFH
Setbitofdatamemory
Bitiofthespecifieddatamemoryissetto1.[m].i¬1
Skipifincrementdatamemoryis0
Thecontentsofthespecifieddatamemoryareincrementedby1.Iftheresultis0,thefol-lowinginstruction,fetchedduringthecurrentinstructionexecution,isdiscardedandadummycycleisreplacedtogettheproperinstruction(2cycles).Otherwiseproceedwiththenextinstruction(1cycle).Skipif([m]+1)=0,[m]¬([m]+1)
OperationAffectedflag(s)
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SIZA[m]Description
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IncrementdatamemoryandplaceresultinACC,skipif0
Thecontentsofthespecifieddatamemoryareincrementedby1.Iftheresultis0,thenextinstructionisskippedandtheresultisstoredintheaccumulator.Thedatamemoryre-mainsunchanged.Iftheresultis0,thefollowinginstruction,fetchedduringthecurrentin-structionexecution,isdiscardedandadummycycleisreplacedtogettheproperinstruction(2cycles).Otherwiseproceedwiththenextinstruction(1cycle).Skipif([m]+1)=0,ACC¬([m]+1)
OperationAffectedflag(s)
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SNZ[m].iDescription
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Skipifbitiofthedatamemoryisnot0
Ifbitiofthespecifieddatamemoryisnot0,thenextinstructionisskipped.Ifbitiofthedatamemoryisnot0,thefollowinginstruction,fetchedduringthecurrentinstructionexecution,isdiscardedandadummycycleisreplacedtogettheproperinstruction(2cycles).Other-wiseproceedwiththenextinstruction(1cycle).Skipif[m].i¹0
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Rev.1.7037April22,2004
元器件交易网www.cecb2b.comHT82K96ESUBA,[m]DescriptionOperationAffectedflag(s)
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SUBMA,[m]DescriptionOperationAffectedflag(s)
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SUBA,xDescriptionOperationAffectedflag(s)
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SWAP[m]DescriptionOperationAffectedflag(s)
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SWAPA[m]DescriptionOperationAffectedflag(s)
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Subtractdatamemoryfromtheaccumulator
Thespecifieddatamemoryissubtractedfromthecontentsoftheaccumulator,leavingtheresultintheaccumulator.ACC¬ACC+[m]+1
Subtractdatamemoryfromtheaccumulator
Thespecifieddatamemoryissubtractedfromthecontentsoftheaccumulator,leavingtheresultinthedatamemory.[m]¬ACC+[m]+1
Subtractimmediatedatafromtheaccumulator
Theimmediatedataspecifiedbythecodeissubtractedfromthecontentsoftheaccumula-tor,leavingtheresultintheaccumulator.ACC¬ACC+x+1
Swapnibbleswithinthedatamemory
Thelow-orderandhigh-ordernibblesofthespecifieddatamemory(1ofthedatamemo-ries)areinterchanged.[m].3~[m].0«[m].7~[m].4
Swapdatamemoryandplaceresultintheaccumulator
Thelow-orderandhigh-ordernibblesofthespecifieddatamemoryareinterchanged,writ-ingtheresulttotheaccumulator.Thecontentsofthedatamemoryremainunchanged.ACC.3~ACC.0¬[m].7~[m].4ACC.7~ACC.4¬[m].3~[m].0
Rev.1.7038April22,2004
元器件交易网www.cecb2b.comHT82K96ESZ[m]Description
Skipifdatamemoryis0
Ifthecontentsofthespecifieddatamemoryare0,thefollowinginstruction,fetchedduringthecurrentinstructionexecution,isdiscardedandadummycycleisreplacedtogettheproperinstruction(2cycles).Otherwiseproceedwiththenextinstruction(1cycle).Skipif[m]=0
OperationAffectedflag(s)
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SZA[m]Description
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MovedatamemorytoACC,skipif0
Thecontentsofthespecifieddatamemoryarecopiedtotheaccumulator.Ifthecontentsis0,thefollowinginstruction,fetchedduringthecurrentinstructionexecution,isdiscardedandadummycycleisreplacedtogettheproperinstruction(2cycles).Otherwiseproceedwiththenextinstruction(1cycle).Skipif[m]=0
OperationAffectedflag(s)
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SZ[m].iDescription
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Skipifbitiofthedatamemoryis0
Ifbitiofthespecifieddatamemoryis0,thefollowinginstruction,fetchedduringthecurrentinstructionexecution,isdiscardedandadummycycleisreplacedtogettheproperinstruc-tion(2cycles).Otherwiseproceedwiththenextinstruction(1cycle).Skipif[m].i=0
OperationAffectedflag(s)
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TABRDC[m]DescriptionOperationAffectedflag(s)
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TABRDL[m]DescriptionOperationAffectedflag(s)
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MovetheROMcode(currentpage)toTBLHanddatamemory
ThelowbyteofROMcode(currentpage)addressedbythetablepointer(TBLP)ismovedtothespecifieddatamemoryandthehighbytetransferredtoTBLHdirectly.[m]¬ROMcode(lowbyte)TBLH¬ROMcode(highbyte)
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MovetheROMcode(lastpage)toTBLHanddatamemory
ThelowbyteofROMcode(lastpage)addressedbythetablepointer(TBLP)ismovedtothedatamemoryandthehighbytetransferredtoTBLHdirectly.[m]¬ROMcode(lowbyte)TBLH¬ROMcode(highbyte)
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Rev.1.7039April22,2004
元器件交易网www.cecb2b.comHT82K96EXORA,[m]DescriptionOperationAffectedflag(s)
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XORMA,[m]DescriptionOperationAffectedflag(s)
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XORA,xDescriptionOperationAffectedflag(s)
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LogicalXORaccumulatorwithdatamemory
DataintheaccumulatorandtheindicateddatamemoryperformabitwiselogicalExclu-sive_ORoperationandtheresultisstoredintheaccumulator.ACC¬ACC²XOR²[m]
LogicalXORdatamemorywiththeaccumulator
DataintheindicateddatamemoryandtheaccumulatorperformabitwiselogicalExclu-sive_ORoperation.Theresultisstoredinthedatamemory.The0flagisaffected.[m]¬ACC²XOR²[m]
LogicalXORimmediatedatatotheaccumulator
DataintheaccumulatorandthespecifieddataperformabitwiselogicalExclusive_ORop-eration.Theresultisstoredintheaccumulator.The0flagisaffected.ACC¬ACC²XOR²x
Rev.1.7040April22,2004
元器件交易网www.cecb2b.comHT82K96EPackageInformation
20-pinSOP(300mil)OutlineDimensions
SymbolABCC¢DEFGHa
Dimensionsinmil
Min.3942901449092¾43240°
Nom.¾¾¾¾¾50¾¾¾¾
Max.41930020510104¾¾381210°
Rev.1.7041April22,2004
元器件交易网www.cecb2b.comHT82K96E48-pinSSOP(300mil)OutlineDimensions
SymbolABCC¢DEFGHa
Dimensionsinmil
Min.395291861385¾42540°
Nom.¾¾¾¾¾25¾¾¾¾
Max.4202991263799¾1035128°
Rev.1.7042April22,2004
元器件交易网www.cecb2b.comHT82K96EProductTapeandReelSpecifications
ReelDimensions
SOP28W(300mil)
SymbolABCDT1T2
SSOP48W
SymbolABCDT1T2
Description
ReelOuterDiameterReelInnerDiameterSpindleHoleDiameterKeySlitWidth
SpaceBetweenFlangeReelThickness
Dimensionsinmm
330±1.0100±0.113.0+0.5
-0.22.0±0.532.2+0.3
-0.238.2±0.2
Description
ReelOuterDiameterReelInnerDiameterSpindleHoleDiameterKeySlitWidth
SpaceBetweenFlangeReelThickness
Dimensionsinmm
330±1.062±1.513.0+0.5
-0.22.0±0.524.8+0.3
-0.230.2±0.2
Rev.1.7043April22,2004
元器件交易网www.cecb2b.comHT82K96ECarrierTapeDimensions
SOP28W(300mil)
SymbolWPEFDD1P0P1A0B0K0tC
Description
CarrierTapeWidthCavityPitchPerforationPosition
CavitytoPerforation(WidthDirection)PerforationDiameterCavityHoleDiameterPerforationPitch
CavitytoPerforation(LengthDirection)CavityLengthCavityWidthCavityDepth
CarrierTapeThicknessCoverTapeWidth
Dimensionsinmm
24.0±0.312.0±0.11.75±0.111.5±0.11.5+0.11.5+0.254.0±0.12.0±0.110.85±0.118.34±0.12.97±0.10.35±0.0121.3
Rev.1.7044April22,2004
元器件交易网www.cecb2b.comHT82K96ESSOP48W
SymbolWPEFDD1P0P1A0B0K1K2tC
Description
CarrierTapeWidthCavityPitchPerforationPosition
CavitytoPerforation(WidthDirection)PerforationDiameterCavityHoleDiameterPerforationPitch
CavitytoPerforation(LengthDirection)CavityLengthCavityWidthCavityDepthCavityDepth
CarrierTapeThicknessCoverTapeWidth
Dimensionsinmm
32.0±0.316.0±0.11.75±0.114.2±0.12.0Min.1.5+0.254.0±0.12.0±0.112.0±0.116.20±0.12.4±0.13.2±0.10.35±0.0525.5
Rev.1.7045April22,2004
元器件交易网www.cecb2b.comHT82K96EHoltekSemiconductorInc.(Headquarters)
No.3,CreationRd.II,SciencePark,Hsinchu,TaiwanTel:886-3-563-1999Fax:886-3-563-1189http://www.holtek.com.tw
HoltekSemiconductorInc.(TaipeiSalesOffice)
4F-2,No.3-2,YuanQuSt.,NankangSoftwarePark,Taipei115,TaiwanTel:886-2-2655-7070Fax:886-2-2655-7373
Fax:886-2-2655-7383(Internationalsaleshotline)
HoltekSemiconductorInc.(ShanghaiSalesOffice)
7thFloor,Building2,No.889,YiShanRd.,Shanghai,China200233Tel:021-6485-5560Fax:021-6485-0313
http://www.holtek.com.cn
HoltekSemiconductorInc.(ShenzhenSalesOffice)
43F,SEGPlaza,ShenNanZhongRoad,Shenzhen,China518031Tel: 0755-8346-5589Fax: 0755-8346-5590ISDN: 0755-8346-5591
HoltekSemiconductorInc.(BeijingSalesOffice)
Suite1721,JinyuTower,A129WestXuanWuMenStreet,XichengDistrict,Beijing,China100031Tel: 010-6641-0030, 6641-7751, 6641-7752Fax: 010-6641-0125HolmateSemiconductor,Inc.(NorthAmericaSalesOffice)46712FremontBlvd.,Fremont,CA94538Tel:510-252-9880Fax:510-252-9885
http://www.holmate.com
CopyrightÓ2004byHOLTEKSEMICONDUCTORINC.
TheinformationappearinginthisDataSheetisbelievedtobeaccurateatthetimeofpublication.However,Holtekas-sumesnoresponsibilityarisingfromtheuseofthespecificationsdescribed.TheapplicationsmentionedhereinareusedsolelyforthepurposeofillustrationandHoltekmakesnowarrantyorrepresentationthatsuchapplicationswillbesuitablewithoutfurthermodification,norrecommendstheuseofitsproductsforapplicationthatmaypresentarisktohumanlifeduetomalfunctionorotherwise.Holtek¢sproductsarenotauthorizedforuseascriticalcomponentsinlifesupportdevicesorsystems.Holtekreservestherighttoalteritsproductswithoutpriornotification.Forthemostup-to-dateinformation,pleasevisitourwebsiteathttp://www.holtek.com.tw.
Rev.1.7046April22,2004
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