一、实验目的
1．了解四位并行乘法器的原理。
2．了解四位并行乘法器的设计思想和流水线的实现方法。 3．掌握用VHDL 语言实现基本二进制运算的方法。
二、实验内容与要求
通过开关和键盘输入两组4BIT的二进制数据，按照二进制加法器原理进行加和，求出和及进位，并通过LED显示灯输出显示，完成编译、综合、适配、仿真、实验箱上的硬件测试。
三、实验原理
流水线结构的并行乘法器的最大有点就是速度快，尤其实在连续输入的乘法器中，可以达到近乎单周期的运算速度。
流水线乘法器是组合逻辑电路实现无符号数乘法的方法上发展而来的。其关键是在组合逻辑电路的基础上插入寄存器。
假如有被乘数A 和乘数B，首先用A 与B 的最低位相乘得到S1，然后再把A 左移1 位与B 的第2 位相乘得到S2，再将A 左移3 位与B 的第三位相乘得到S3，依此类推，直到把B 的所有位都乘完为止，然后再把乘得的结果S1、S2、S3……相加即得到相乘的结果。 需要注意的是，具体实现乘法器是，并不是真正的去乘，而是利用简单的判断去实现，举个简单的例子。假如A 左移n 位后与B 的第n 位相乘， 如果B 的这位为‘1’， 那么相乘的中间结果就是A 左移n 位后的结果，否则如果B 的这位为‘0’，那么就直接让相乘的中间结果为0 即可。带B 的所有位相乘结束后，把所有的中间结果相加即得到A 与B 相乘的结果。在此基础上插入寄存器即可实现流水线乘法器。
四、实验平台
（1）硬件：计算机、GX-SOC/SOPC-DEV-LAB
CycloneII EP2C35F672C8核心板
（2）软件：Quartus II软件
五、引脚分配 芯片引脚 PIN_P25 PIN_E25 PIN_F24，F23 PIN_J21 PIN_J20 PIN_F25，F26 PIN_N18 PIN_AC10 PIN_W11，W12 PIN_AE8 设计端口 CLK AIN[0] AIN[1]，[2] AIN[3] BIN[0] BIN[1]，[2] BIN[3] DATAOUT[0] DATAOUT[1]，[2] DATAOUT[3] 开发平台 F1 F1 F1 F2 F2 F2 LED0 LED1，2 LED3 PIN_AF8 PIN_AE7 PIN_AF7 PIN_AA11 PIN_AE21 PIN_AB20 PIN_AC20 PIN_AF20 PIN_AE20 PIN_AD19 PIN_AC19 PIN_AA17 PIN_AA18 PIN_W17 PIN_V17 PIN_AB18 六、仿真截图
DATAOUT[4] DATAOUT[5] DATAOUT[6] DATAOUT[7] BCD[0] BCD[1] BCD[2] BCD[3] BCD[4] BCD[5] BCD[6] BCD[7] BCD[8] BCD[9] BCD[10] BCD[11] LED4 LED5 LED6 LED7 数码管DP4B 数码管DP5B 数码管DP6B
七、硬件实现
八、程序代码 1---clkgen.vhd
library IEEE;-- 1HZ
use IEEE.std_logic_1164.all; use ieee.std_logic_unsigned.all;
entity clkgen is port (
CLK : in std_logic; CLK1HZ: out std_logic ); end entity;
architecture clk_arch of clkgen is
signal COUNT : integer range 0 to 50000000; --50MHZ -->1hz
begin -- 50M/1=50000000 PROCESS(CLK) BEGIN
if clk'event and clk='1' then
IF COUNT= 50000000 then COUNT<=0;
ELSE COUNT<=COUNT+1; END IF; END IF; END PROCESS;
PROCESS(COUNT) BEGIN
IF COUNT= 5000000 THEN -- 1HZ CLK1HZ<='1';
ELSE CLK1HZ<='0'; END IF; END PROCESS;
end architecture;
2—BCD
-- 输出控制模块，把乘法器的输出转换成BCD码在数码管上显示、 -- SCKZ.VHD
library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity BIN2BCD is
port ( DIN: in std_logic_vector(7 downto 0); ---The input 8bit binary BCDOUT: out std_logic_vector(11 downto 0) --输出显示, 已转换成BCD码 ); end entity;
architecture arch of BIN2BCD is
signal data2,data3,data4 :std_logic_vector(9 downto 0);-- 输出数据缓存 signal hundred,ten,unit:std_logic_vector(3 downto 0);-- signal bcdbuffer:std_logic_vector(11 downto 0); ---2'1111_1001_11=999 begin
BCDOUT<= bcdbuffer;
bcdbuffer(11 downto 8)<=hundred; bcdbuffer(7 downto 4)<=ten; bcdbuffer(3 downto 0)<=unit;
get_hundred_value:process(data2) begin
DATA2<=\"00\"&DIN; ---get hundred value if data2>=900 then
hundred<=\"1001\";--9 data3<=data2-900; elsif data2>=800 then hundred<=\"1000\";--8 data3<=data2-500; elsif data2>=700 then hundred<=\"0111\";--7 data3<=data2-700; elsif data2>=600 then
hundred<=\"0110\";--6 data3<=data2-600;
elsif data2>=500 then hundred<=\"0101\";--5 data3<=data2-500; elsif data2>=400 then hundred<=\"0100\";--4 data3<=data2-400; elsif data2>=300 then hundred<=\"0011\";--3 data3<=data2-300; elsif data2>=200 then hundred<=\"0010\";--2 data3<=data2-200; elsif data2>=100 then hundred<=\"0001\";--1 data3<=data2-100; else data3<=data2;
hundred<=\"0000\";
end if;
end process; ---get_thousand_value
get_tens_value:process(data3) begin
---get tens place if data3>=90 then
ten<=\"1001\";--9 data4<=data3-90; elsif data3>=80 then ten<=\"1000\";--8 data4<=data3-50; elsif data3>=70 then ten<=\"0111\";--7 data4<=data3-70; elsif data3>=60 then ten<=\"0110\";--6 data4<=data3-60; elsif data3>=50 then ten<=\"0101\";--5 data4<=data3-50; elsif data3>=40 then ten<=\"0100\";--4 data4<=data3-40; elsif data3>=30 then ten<=\"0011\";--3
data4<=data3-30; elsif data3>=20 then ten<=\"0010\";--2 data4<=data3-20; elsif data3>=10 then ten<=\"0001\";--1 data4<=data3-10; else data4<=data3; ten<=\"0000\";
end if;
end process; ---get_ten_value
get_unit_value:process(data4) begin
--unit's order if (data4>0) then
unit<=data4(3 downto 0); else unit<=\"0000\"; end if;
end process;
end arch;
3 multi4b --------------------------------------------------------------------------------/ -- DESCRIPTION : Signed mulitplier: -- AIN (A) input width : 4 -- BIN (B) input width : 4
-- Q (data_out) output width : 8 -- 并行流水乘法器
--------------------------------------------------------------------------------/ --10 × 9 = 90
-- 1 0 1 0 -- 1 0 0 1 = -- ------------- -- 1 0 1 0
-- 0 0 0 0 --partial products -- 0 0 0 0 -- 1 0 1 0
-- ------------------
-- 1 0 1 1 0 1 0
--parallel : process all the inputs at the same time
--pipeline : use several stages with registers to implement it
----关键思想，插入寄存器 library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity multi4b is
port ( CLK: in STD_LOGIC; ---system clock
AIN: in STD_LOGIC_VECTOR (3 downto 0); ---one input BIN: in STD_LOGIC_VECTOR (3 downto 0);-- the other input data_out: out STD_LOGIC_VECTOR (7 downto 0)---the result ---make sure the biggest value ,i,e. 1111x1111=1110_0001 can be held in the register ); end multi4b;
architecture multi_arch of multi4b is
signal A,B :std_logic_vector(3 downto 0); --input register
---registers to hold the result of the first processing ---registers added to make use of pipeline, the 1st stage
signal A_MULT_B0: STD_LOGIC_VECTOR (3 downto 0); signal A_MULT_B1: STD_LOGIC_VECTOR (3 downto 0); signal A_MULT_B2: STD_LOGIC_VECTOR (3 downto 0); signal A_MULT_B3: STD_LOGIC_VECTOR (3 downto 0);
---register to hold the result of the multiplier
signal C_TEMP : STD_LOGIC_VECTOR (7 downto 0); begin
PROCESS(CLK,AIN,BIN) begin
if CLK'EVENT AND CLK='1' THEN
-- multiplier operand inputs are registered A<= AIN; B<= BIN;
-----------------Fist stage of the multiplier---------------
---here we get the axb(0),axb(1),axb(2)，axb(3),i.e.partial products ---put them into the responding registers
A_MULT_B0(0) <= A (0) and B (0);
----- multi 1 , get the a(0) and b(0), & put it into the register A_MULT_B0(0)
A_MULT_B0(1) <= A (1) and B (0); A_MULT_B0(2) <= A (2) and B (0);
A_MULT_B0(3) <= A (3) and B (0);
--10 × 9 = 90
-- 1 0 1 0 -- 1 0 0 1 = -- ------------- -- 0 0 0 0 1 0 1 0
-- 0 0 0 0 0 0 0 0 --partial products -- 0 0 0 0 -- 1 0 1 0
-- ------------------
-- 1 0 1 1 0 1 0
A_MULT_B1(0) <= A (0) and B (1); A_MULT_B1(1) <= A (1) and B (1); A_MULT_B1(2) <= A (2) and B (1); A_MULT_B1(3) <= A (3) and B (1);
A_MULT_B2(0) <= A (0) and B (2); A_MULT_B2(1) <= A (1) and B (2); A_MULT_B2(2) <= A (2) and B (2); A_MULT_B2(3) <= A (3) and B (2);
A_MULT_B3(0) <= A (0) and B (3); A_MULT_B3(1) <= A (1) and B (3); A_MULT_B3(2) <= A (2) and B (3); A_MULT_B3(3) <= A (3) and B (3); end if;
end process;
--------------------Second stage of the multiplier-------------
--add the all the partial products ,then get the result of the multiplier C_TEMP<=
( \"0000\" & A_MULT_B0 )+ ( \"000\"& A_MULT_B1 &'0' )+ ( \"00\" & A_MULT_B2 & \"00\" )+ ( '0'&A_MULT_B3 & \"000\" ); --build a signal register output ---输出寄存，利于实现流水
data_out <= C_TEMP; --output register end multi_arch;
九、实验总结
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