Features
•High-performance, Low-power AVR® 8-bit Microcontroller•Advanced RISC Architecture
–131 Powerful Instructions – Most Single-clock Cycle Execution–32 x 8 General Purpose Working Registers–Fully Static Operation
–Up to 20 MIPS Throughput at 20 MHz–On-chip 2-cycle Multiplier
•
Nonvolatile Program and Data Memories
–16/32/64K Bytes of In-System Self-Programmable Flash
Endurance: 10,000 Write/Erase Cycles
–Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot ProgramTrue Read-While-Write Operation–512B/1K/2K Bytes EEPROM
Endurance: 100,000 Write/Erase Cycles–1/2/4K Bytes Internal SRAM
–Programming Lock for Software Security•
JTAG (IEEE std. 1149.1 Compliant) Interface
–Boundary-scan Capabilities According to the JTAG Standard–Extensive On-chip Debug Support
–Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface•
Peripheral Features
–Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
–One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode
–Real Time Counter with Separate Oscillator–Six PWM Channels–8-channel, 10-bit ADC
Differential mode with selectable gain at 1x, 10x or 200x–Byte-oriented Two-wire Serial Interface–Two Programmable Serial USART–Master/Slave SPI Serial Interface
–Programmable Watchdog Timer with Separate On-chip Oscillator–On-chip Analog Comparator
–Interrupt and Wake-up on Pin Change•
Special Microcontroller Features
–Power-on Reset and Programmable Brown-out Detection–Internal Calibrated RC Oscillator
–External and Internal Interrupt Sources
–Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby and Extended Standby•I/O and Packages
–32 Programmable I/O Lines
–40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF•Operating Voltages
–1.8 - 5.5V for ATmega164P/324P/644PV–2.7 - 5.5V for ATmega164P/324P/644P•Speed Grades
–ATmega164P/324P/644PV: 0 - 4MHz @ 1.8 - 5.5V, 0 - 10MHz @ 2.7 - 5.5V–ATmega164P/324P/644P: 0 - 10MHz @ 2.7 - 5.5V, 0 - 20MHz @ 4.5 - 5.5V•
Power Consumption at 1 MHz, 1.8V, 25°C for ATmega164P/324P/644P–Active: 338/398/TBD µA
–Power-down Mode:0.035 /0.027/TBD µA
–Power-save Mode:0.5 /0.5/TBD µA (Including 32 kHz RTC)
8-bit Microcontroller with 16/32/64K Bytes In-SystemProgrammable FlashATmega164P/VATmega324P/VATmega644P/VAdvance InformationSummary 8011DS–AVR–02/07元器件交易网www.cecb2b.com
1.Pin Configurations
Figure 1-1.
Pinout ATmega164P/324P/644P
PDIP(PCINT8/XCK0/T0) PB0(PCINT9/CLKO/T1) PB1(PCINT10/INT2/AIN0) PB2(PCINT11/OC0A/AIN1) PB3(PCINT12/OC0B/SS) PB4(PCINT13/MOSI) PB5(PCINT14/MISO) PB6(PCINT15/SCK) PB7RESETVCCGNDXTAL2XTAL1(PCINT24/RXD0) PD0(PCINT25/TXD0) PD1(PCINT26/RXD1/INT0) PD2(PCINT27/TXD1/INT1) PD3(PCINT28/XCK1/OC1B) PD4(PCINT29/OC1A) PD5(PCINT30/OC2B/ICP) PD6PA0 (ADC0/PCINT0)PA1 (ADC1/PCINT1)PA2 (ADC2/PCINT2)PA3 (ADC3/PCINT3)PA4 (ADC4/PCINT4)PA5 (ADC5/PCINT5)PA6 (ADC6/PCINT6)PA7 (ADC7/PCINT7)AREFGNDAVCCPC7 (TOSC2/PCINT23)PC6 (TOSC1/PCINT22)PC5 (TDI/PCINT21)PC4 (TDO/PCINT20)PC3 (TMS/PCINT19)PC2 (TCK/PCINT18)PC1 (SDA/PCINT17)PC0 (SCL/PCINT16)PD7 (OC2A/PCINT31)TQFP/QFN/MLFPB4 (SS/OC0B/PCINT12)PB3 (AIN1/OC0A/PCINT11)PB2 (AIN0/INT2/PCINT10)PB1 (T1/CLKO/PCINT9)PB0 (XCK0/T0/PCINT8)GNDVCCPA0 (ADC0/PCINT0)PA1 (ADC1/PCINT1)PA2 (ADC2/PCINT2)PA3 (ADC3/PCINT3)(PCINT13/MOSI) PB5(PCINT14/MISO) PB6(PCINT15/SCK) PB7RESETVCCGNDXTAL2XTAL1(PCINT24/RXD0) PD0(PCINT25/TXD0) PD1(PCINT26/RXD1/INT0) PD2PA4 (ADC4/PCINT4)PA5 (ADC5/PCINT5)PA6 (ADC6/PCINT6)PA7 (ADC7/PCINT7)AREFGNDAVCCPC7 (TOSC2/PCINT23)PC6 (TOSC1/PCINT22)PC5 (TDI/PCINT21)PC4 (TDO/PCINT20)Note:
The large center pad underneath the QFN/MLF package should be soldered to ground on the board to ensure good mechanical stability.
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(PCINT27/TXD1/INT1) PD3(PCINT28/XCK1/OC1B) PD4(PCINT29/OC1A) PD5(PCINT30/OC2B/ICP) PD6(PCINT31/OC2A) PD7VCCGND(PCINT16/SCL) PC0(PCINT17/SDA) PC1(PCINT18/TCK) PC2(PCINT19/TMS) PC3元器件交易网www.cecb2b.com
ATmega164P/324P/644P
1.1
Disclaimer
Typical values contained in this datasheet are based on simulations and characterization ofother AVR microcontrollers manufactured on the same process technology. Min and Max valueswill be available after the device is characterized.
8011DS–AVR–02/07
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2.Overview
The ATmega164P/324P/644P is a low-power CMOS 8-bit microcontroller based on the AVRenhanced RISC architecture. By executing powerful instructions in a single clock cycle, theATmega164P/324P/644P achieves throughputs approaching 1 MIPS per MHz allowing the sys-tem designer to optimize power consumption versus processing speed.
2.1Block Diagram
Block Diagram
Figure 2-1.
PA7..0VCCPB7..0RESETPowerSupervisionPOR / BOD &RESETPORT A (8)PORT B (8)GNDWatchdogTimerWatchdogOscillatorA/DConverterAnalog ComparatorUSART 0XTAL1OscillatorCircuits /ClockGenerationEEPROMInternal Bandgap referenceSPIXTAL28bit T/C 0 CPUJTAG/OCD16bit T/C 1TWIFLASHSRAM8bit T/C 2USART 1PORT C (8)PORT D (8)TOSC2/PC7TOSC1/PC6PC5..0PD7..0The AVR core combines a rich instruction set with 32 general purpose working registers. All the32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independentregisters to be accessed in one single instruction executed in one clock cycle. The resultingarchitecture is more code efficient while achieving throughputs up to ten times faster than con-ventional CISC microcontrollers.
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ATmega164P/324P/644P
The ATmega164P/324P/644P provides the following features: 16/32/64K bytes of In-SystemProgrammable Flash with Read-While-Write capabilities, 512B/1K/2K bytes EEPROM, 1/2/4Kbytes SRAM, 32 general purpose I/O lines, 32 general purpose working registers, Real TimeCounter (RTC), three flexible Timer/Counters with compare modes and PWM, 2 USARTs, a byteoriented 2-wire Serial Interface, a 8-channel, 10-bit ADC with optional differential input stagewith programmable gain, programmable Watchdog Timer with Internal Oscillator, an SPI serialport, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chipDebug system and programming and six software selectable power saving modes. The Idlemode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt systemto continue functioning. The Power-down mode saves the register contents but freezes theOscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer basewhile the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and allI/O modules except Asynchronous Timer and ADC, to minimize switching noise during ADCconversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of thedevice is sleeping. This allows very fast start-up combined with low power consumption. InExtended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run.The device is manufactured using Atmel’s high-density nonvolatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serialinterface, by a conventional nonvolatile memory programmer, or by an On-chip Boot programrunning on the AVR core. The boot program can use any interface to download the applicationprogram in the application Flash memory. Software in the Boot Flash section will continue to runwhile the Application Flash section is updated, providing true Read-While-Write operation. Bycombining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip,the Atmel ATmega164P/324P/644P is a powerful microcontroller that provides a highly flexibleand cost effective solution to many embedded control applications.
The ATmega164P/324P/644P AVR is supported with a full suite of program and system devel-opment tools including: C compilers, macro assemblers, program debugger/simulators, in-circuitemulators, and evaluation kits.
2.2Comparison Between ATmega164P, ATmega324P and ATmega644P
Table 2-1.
DeviceATmega164PATmega324PATmega644P
Differences between ATmega164P and ATmega644P
Flash16 Kbyte32 Kbyte64 Kbyte
EEPROM512 Bytes1 Kbyte2 Kbyte
RAM1 Kbyte2 Kbyte4 Kbyte
2.3
2.3.1
Pin Descriptions
VCC
Digital supply voltage.
2.3.2GND
Ground.
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2.3.3Port A (PA7:PA0)
Port A serves as analog inputs to the Analog-to-digital Converter.
Port A also serves as an 8-bit bi-directional I/O port with internal pull-up resistors (selected foreach bit). The Port A output buffers have symmetrical drive characteristics with both high sinkand source capability. As inputs, Port A pins that are externally pulled low will source current ifthe pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomesactive, even if the clock is not running.
Port A also serves the functions of various special features of the ATmega164P/324P/644P aslisted on page 79.
2.3.4Port B (PB7:PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). ThePort B output buffers have symmetrical drive characteristics with both high sink and sourcecapability. As inputs, Port B pins that are externally pulled low will source current if the pull-upresistors are activated. The Port B pins are tri-stated when a reset condition becomes active,even if the clock is not running.
Port B also serves the functions of various special features of the ATmega164P/324P/644P aslisted on page 81.
2.3.5Port C (PC7:PC0)
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). ThePort C output buffers have symmetrical drive characteristics with both high sink and sourcecapability. As inputs, Port C pins that are externally pulled low will source current if the pull-upresistors are activated. The Port C pins are tri-stated when a reset condition becomes active,even if the clock is not running.
Port C also serves the functions of the JTAG interface, along with special features of theATmega164P/324P/644P as listed on page 84.
2.3.6Port D (PD7:PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). ThePort D output buffers have symmetrical drive characteristics with both high sink and sourcecapability. As inputs, Port D pins that are externally pulled low will source current if the pull-upresistors are activated. The Port D pins are tri-stated when a reset condition becomes active,even if the clock is not running.
Port D also serves the functions of various special features of the ATmega164P/324P/644P aslisted on page 86.
2.3.7RESETReset input. A low level on this pin for longer than the minimum pulse length will generate areset, even if the clock is not running. The minimum pulse length is given in Table 9-1 on page50. Shorter pulses are not guaranteed to generate a reset.
2.3.8XTAL1
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
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ATmega164P/324P/644P
2.3.9
XTAL2
Output from the inverting Oscillator amplifier.
2.3.10
AVCC
AVCC is the supply voltage pin for Port F and the Analog-to-digital Converter. It should be exter-nally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connectedto VCC through a low-pass filter.
2.3.11
AREF
This is the analog reference pin for the Analog-to-digital Converter.
3.Resources
A comprehensive set of development tools, application notes and datasheetsare available fordownload on http://www.atmel.com/avr.
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4.Register Summary
Address
(0xFF)(0xFE)(0xFD)(0xFC)(0xFB)(0xFA)(0xF9)(0xF8)(0xF7)(0xF6)(0xF5)(0xF4)(0xF3)(0xF2)(0xF1)(0xF0)(0xEF)(0xEE)(0xED)(0xEC)(0xEB)(0xEA)(0xE9)(0xE8)(0xE7)(0xE6)(0xE5)(0xE4)(0xE3)(0xE2)(0xE1)(0xE0)(0xDF)(0xDE)(0xDD)(0xDC)(0xDB)(0xDA)(0xD9)(0xD8)(0xD7)(0xD6)(0xD5)(0xD4)(0xD3)(0xD2)(0xD1)(0xD0)(0xCF)(0xCE)(0xCD)(0xCC)(0xCB)(0xCA)(0xC9)(0xC8)(0xC7)(0xC6)(0xC5)(0xC4)(0xC3)(0xC2)(0xC1)(0xC0)
Name
ReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedUDR1UBRR1HUBRR1LReservedUCSR1CUCSR1BUCSR1AReservedUDR0UBRR0HUBRR0LReservedUCSR0CUCSR0BUCSR0A
Bit 7
---------------------------------------------------UMSEL11RXCIE1RXC1---UMSEL01RXCIE0RXC0
Bit 6
---------------------------------------------------UMSEL10TXCIE1TXC1---UMSEL00TXCIE0TXC0
Bit 5
---------------------------------------------------UPM11UDRIE1UDRE1
---UPM01UDRIE0UDRE0
Bit 4
---------------------------------------------------UPM10RXEN1FE1---UPM00RXEN0FE0
Bit 3
---------------------
Bit 2
--------------------------------
Bit 1
-------------------------------------------------
Bit 0
-------------------------------------------------
Page
----------------
-----------------
USART1 I/O Data Register
USART1 Baud Rate Register High Byte
-USBS1TXEN1DOR1--UCSZ11UCSZ12UPE1--UCSZ10RXB81U2X1--UCPOL1TXB81MPCM1
- USART1 Baud Rate Register Low Byte
184189/201189/201187/200186/200185/199184
USART0 Baud Rate Register High Byte
189/201189/201
-UCSZ01UCSZ02UPE0
-UCSZ00RXB80U2X0
-UCPOL0TXB80MPCM0
187/200186/200185/199
USART0 I/O Data Register USART0 Baud Rate Register Low Byte
-USBS0TXEN0DOR0
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ATmega164P/324P/644P
Address
(0xBF)(0xBE)(0xBD)(0xBC)(0xBB)(0xBA)(0xB9)(0xB8)(0xB7)(0xB6)(0xB5)(0xB4)(0xB3)(0xB2)(0xB1)(0xB0)(0xAF)(0xAE)(0xAD)(0xAC)(0xAB)(0xAA)(0xA9)(0xA8)(0xA7)(0xA6)(0xA5)(0xA4)(0xA3)(0xA2)(0xA1)(0xA0)(0x9F)(0x9E)(0x9D)(0x9C)(0x9B)(0x9A)(0x99)(0x98)(0x97)(0x96)(0x95)(0x94)(0x93)(0x92)(0x91)(0x90)(0x8F)(0x8E)(0x8D)(0x8C)(0x8B) (0x8A)(0x89)(0x88)(0x87)(0x86)(0x85)(0x84)(0x83)(0x82)(0x81)(0x80)(0x7F)(0x7E)
Name
ReservedReservedTWAMRTWCRTWDRTWARTWSRTWBRReservedASSRReservedOCR2BOCR2ATCNT2TCCR2BTCCR2AReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedOCR1BHOCR1BLOCR1AHOCR1ALICR1HICR1LTCNT1HTCNT1LReservedTCCR1CTCCR1BTCCR1ADIDR1DIDR0
Bit 7
--TWAM6TWINTTWA6TWS7---
Bit 6
--TWAM5TWEATWA5TWS6-EXCLK-
Bit 5
--TWAM4TWSTATWA4TWS5-AS2-
Bit 4
--TWAM3TWSTOTWA3TWS4-TCN2UB
-
Bit 3
--TWAM2TWWCTWA2TWS3-OCR2AUB
-
Bit 2
--TWAM1TWENTWA1--OCR2BUB
-
Bit 1
--TWAM0
-TWA0TWPS1
-TCR2AUB
-
Bit 0
---TWIETWGCETWPS0
-TCR2BUB
-
Page
232228230232230228153152152152
2-wire Serial Interface Data Register
2-wire Serial Interface Bit Rate Register
Timer/Counter2 Output Compare Register B Timer/Counter2 Output Compare Register A
Timer/Counter2 (8 Bit)
FOC2ACOM2A1
------------------------------------FOC2BCOM2A0
-------------------------------------COM2B1
-------------------------------------COM2B0
------------------------------------WGM22
-------------------------------------CS22-------------------------------------CS21WGM21
------------------------------------CS20WGM20
------------------------------------
151148
Timer/Counter1 - Output Compare Register B High ByteTimer/Counter1 - Output Compare Register B Low ByteTimer/Counter1 - Output Compare Register A High ByteTimer/Counter1 - Output Compare Register A Low ByteTimer/Counter1 - Input Capture Register High ByteTimer/Counter1 - Input Capture Register Low ByteTimer/Counter1 - Counter Register High ByteTimer/Counter1 - Counter Register Low Byte
-FOC1AICNC1COM1A1
-ADC7D
-FOC1BICES1COM1A0
-ADC6D
---COM1B1
-ADC5D
--WGM13COM1B0
-ADC4D
--WGM12
--ADC3D
--CS12--ADC2D
--CS11WGM11AIN1DADC1D
--CS10WGM10AIN0DADC0D
134134134134135135134134133132130235255
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Address
(0x7D)(0x7C)(0x7B)(0x7A)(0x79)(0x78)(0x77)(0x76)(0x75)(0x74)(0x73)(0x72)(0x71)(0x70)(0x6F)(0x6E)(0x6D)(0x6C)(0x6B)(0x6A)(0x69)(0x68)(0x67)(0x66)(0x65)(0x64)(0x63)(0x62)(0x61)(0x60)0x3F (0x5F)0x3E (0x5E)0x3D (0x5D)0x3C (0x5C)0x3B (0x5B)0x3A (0x5A)0x39 (0x59)0x38 (0x58)0x37 (0x57)0x36 (0x56)0x35 (0x55)0x34 (0x54)0x33 (0x53)0x32 (0x52)0x31 (0x51)0x30 (0x50)0x2F (0x4F)0x2E (0x4E)0x2D (0x4D)0x2C (0x4C)0x2B (0x4B)0x2A (0x4A)0x29 (0x49)0x28 (0x48)0x27 (0x47)0x26 (0x46)0x25 (0x45)0x24 (0x44)0x23 (0x43)0x22 (0x42)0x21 (0x41)0x20 (0x40)0x1F (0x3F)0x1E (0x3E)0x1D (0x3D)0x1C (0x3C)
Name
ReservedADMUXADCSRBADCSRAADCHADCLReservedReservedReservedReservedPCMSK3ReservedReservedTIMSK2TIMSK1TIMSK0PCMSK2PCMSK1PCMSK0ReservedEICRAPCICRReservedOSCCALReservedPRRReservedReservedCLKPRWDTCSRSREGSPHSPLReservedRAMPZReservedReservedReservedSPMCSRReservedMCUCRMCUSRSMCRReservedOCDRACSRReservedSPDRSPSRSPCRGPIOR2GPIOR1ReservedOCR0BOCR0ATCNT0TCCR0BTCCR0AGTCCREEARHEEARLEEDREECRGPIOR0EIMSKEIFR
Bit 7
-REFS1-ADEN
Bit 6
-REFS0ACMEADSC
Bit 5
-ADLAR-ADATE
Bit 4
-MUX4-ADIF
Bit 3
-MUX3-ADIE
Bit 2
-MUX2ADTS2ADPS2
Bit 1
-MUX1ADTS1ADPS1
Bit 0
-MUX0ADTS0ADPS0
Page
251233252254254
ADC Data Register High byteADC Data Register Low byte
----PCINT31
-----PCINT23PCINT15PCINT7
-----PRTWI--CLKPCEWDIFISP15SP7-----SPMIE-JTD---ACD-SPIF0SPIE0
----PCINT30
-----PCINT22PCINT14PCINT6
-----PRTIM2
---WDIETSP14SP6-----RWWSB
-BODS---ACBG-WCOL0SPE0
----PCINT29
---ICIE1-PCINT21PCINT13PCINT5
-ISC21---PRTIM0
---WDP3HSP13SP5-----SIGRD-BODSE
---ACO--DORD0
----PCINT28
-----PCINT20PCINT12PCINT4
-ISC20---PRUSART1
---WDCESSP12SP4-----RWWSRE
-PUDJTRF--ACI--MSTR0
----PCINT27
-----PCINT19PCINT11PCINT3
-ISC11PCIE3--PRTIM1
--CLKPS3WDEVSP11SP3-----BLBSET
--WDRFSM2-ACIE--CPOL0
----PCINT26
--OCIE2BOCIE1BOCIE0BPCINT18PCINT10PCINT2
-ISC10PCIE2--PRSPI--CLKPS2WDP2NSP10SP2-----PGWRT
--BORFSM1-ACIC--CPHA0
----PCINT25
--OCIE2AOCIE1AOCIE0APCINT17PCINT9PCINT1
-ISC01PCIE1--PRUSART0
--CLKPS1WDP1ZSP9SP1-----PGERS
-IVSELEXTRFSM0-ACIS1--SPR01
----PCINT24
--TOIE2TOIE1TOIE0PCINT16PCINT8PCINT0
-ISC00PCIE0-
69
155135107696970666839
Oscillator Calibration Register
-PRADC
--CLKPS0WDP0CSP8SP0-RAMPZ0
---SPMEN
-IVCEPORFSE-
47
395812121215
27778/26553/26646261
On-Chip Debug Register
ACIS0-
252165
SPI 0 Data Register
SPI2X0SPR00
1651632727
General Purpose I/O Register 2General Purpose I/O Register 1
-------- Timer/Counter0 Output Compare Register B Timer/Counter0 Output Compare Register A
Timer/Counter0 (8 Bit)
FOC0ACOM0A1TSM-FOC0BCOM0A0
---COM0B1
---COM0B0
--EEPROM Data Register
------EEPM1
--EEPM0
--EERIE--EEMWEINT2INTF2
EEWEINT1INTF1
EEREINT0INTF0
General Purpose I/O Register 0
WGM02
--CS02--CS01WGM01PSR2
CS00WGM00PSR54310
10710710710610715722222223286767
EEPROM Address Register High Byte
EEPROM Address Register Low Byte
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ATmega164P/324P/644P
Address
0x1B (0x3B)0x1A (0x3A)0x19 (0x39)0x18 (0x38)0x17 (0x37)0x16 (0x36)0x15 (0x35)0x14 (0x34)0x13 (0x33)0x12 (0x32)0x11 (0x31)0x10 (0x30)0x0F (0x2F)0x0E (0x2E)0x0D (0x2D)0x0C (0x2C)0x0B (0x2B)0x0A (0x2A)0x09 (0x29)0x08 (0x28)0x07 (0x27)0x06 (0x26)0x05 (0x25)0x04 (0x24)0x03 (0x23)0x02 (0x22)0x01 (0x21)0x00 (0x20)
Name
PCIFRReservedReservedReservedTIFR2TIFR1TIFR0ReservedReservedReservedReservedReservedReservedReservedReservedReservedPORTDDDRDPINDPORTCDDRCPINCPORTBDDRBPINBPORTADDRAPINA
Bit 7
----------------PORTD7DDD7PIND7PORTC7DDC7PINC7PORTB7DDB7PINB7PORTA7DDA7PINA7
Bit 6
----------------PORTD6DDD6PIND6PORTC6DDC6PINC6PORTB6DDB6PINB6PORTA6DDA6PINA6
Bit 5
-----ICF1----------PORTD5DDD5PIND5PORTC5DDC5PINC5PORTB5DDB5PINB5PORTA5DDA5PINA5
Bit 4
----------------PORTD4DDD4PIND4PORTC4DDC4PINC4PORTB4DDB4PINB4PORTA4DDA4PINA4
Bit 3
PCIF3---------------PORTD3DDD3PIND3PORTC3DDC3PINC3PORTB3DDB3PINB3PORTA3DDA3PINA3
Bit 2
PCIF2---OCF2bOCF1BOCF0B---------PORTD2DDD2PIND2PORTC2DDC2PINC2PORTB2DDB2PINB2PORTA2DDA2PINA2
Bit 1
PCIF1---OCF2AOCF1AOCF0A---------PORTD1DDD1PIND1PORTC1DDC1PINC1PORTB1DDB1PINB1PORTA1DDA1PINA1
Bit 0
PCIF0---TOV2TOV1TOV0---------PORTD0DDD0PIND0PORTC0DDC0PINC0PORTB0DDB0PINB0PORTA0DDA0PINA0
Page
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156136108
919191909091909090909090
Notes:
1.For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2.I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these reg-isters, the value of single bits can be checked by using the SBIS and SBIC instructions.
3.Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on
all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers 0x00 to 0x1F only.
4.When using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O regis-ters as data space using LD and ST instructions, $20 must be added to these addresses. The ATmega164P/324P/644P is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from $60 - $FF, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
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5.Instruction Set Summary
Mnemonics
ADDADCADIWSUBSUBISBCSBCISBIWANDANDIORORIEORCOMNEGSBRCBRINCDECTSTCLRSERMULMULSMULSUFMULFMULSFMULSURJMPIJMPJMPRCALLICALLCALLRETRETICPSECPCPCCPISBRCSBRSSBICSBISBRBSBRBCBREQBRNEBRCSBRCCBRSHBRLOBRMIBRPLBRGEBRLTBRHSBRHCBRTSBRTCBRVS
Rd,RrRd,RrRd,RrRd,KRr, bRr, bP, bP, bs, ks, k k k k k k k k k k k k k k k kkkk
Operands
Rd, RrRd, RrRdl,KRd, RrRd, KRd, RrRd, KRdl,KRd, RrRd, KRd, RrRd, KRd, RrRdRdRd,KRd,KRdRdRdRdRdRd, RrRd, RrRd, RrRd, RrRd, RrRd, Rrk
Add two Registers
Description
Rd ← Rd + Rr
OperationFlags
Z,C,N,V,HZ,C,N,V,HZ,C,N,V,SZ,C,N,V,HZ,C,N,V,HZ,C,N,V,HZ,C,N,V,HZ,C,N,V,SZ,N,VZ,N,VZ,N,VZ,N,VZ,N,VZ,C,N,VZ,C,N,V,HZ,N,VZ,N,VZ,N,VZ,N,VZ,N,VZ,N,VNoneZ,CZ,CZ,CZ,CZ,CZ,CNoneNoneNoneNoneNoneNoneNoneINoneZ, N,V,C,HZ, N,V,C,HZ, N,V,C,HNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNone
#Clocks
1121111211111111111111222222223445551/2/31 111/2/31/2/31/2/31/2/31/21/21/21/21/21/21/21/21/21/21/21/21/21/21/21/21/2
ARITHMETIC AND LOGIC INSTRUCTIONS
Add with Carry two RegistersAdd Immediate to WordSubtract two Registers
Rd ← Rd + Rr + CRdh:Rdl ← Rdh:Rdl + KRd ← Rd - Rr
Subtract Constant from Register Rd ← Rd - K
Subtract with Carry two RegistersRd ← Rd - Rr - C
Subtract with Carry Constant from Reg.Rd ← Rd - K - C
Subtract Immediate from WordRdh:Rdl ← Rdh:Rdl - KLogical AND Registers
Logical AND Register and ConstantLogical OR Registers
Logical OR Register and ConstantExclusive OR RegistersOne’s ComplementTwo’s ComplementSet Bit(s) in RegisterClear Bit(s) in RegisterIncrementDecrement
Test for Zero or MinusClear RegisterSet RegisterMultiply UnsignedMultiply Signed
Multiply Signed with UnsignedFractional Multiply UnsignedFractional Multiply Signed
Fractional Multiply Signed with UnsignedRelative JumpIndirect Jump to (Z)Direct Jump
Relative Subroutine Call Indirect Call to (Z)Direct Subroutine Call Subroutine ReturnInterrupt ReturnCompare, Skip if EqualCompare
Compare with Carry
Compare Register with ImmediateSkip if Bit in Register ClearedSkip if Bit in Register is SetSkip if Bit in I/O Register ClearedSkip if Bit in I/O Register is SetBranch if Status Flag SetBranch if Status Flag ClearedBranch if Equal Branch if Not EqualBranch if Carry SetBranch if Carry ClearedBranch if Same or Higher Branch if LowerBranch if MinusBranch if Plus
Branch if Greater or Equal, SignedBranch if Less Than Zero, SignedBranch if Half Carry Flag SetBranch if Half Carry Flag ClearedBranch if T Flag SetBranch if T Flag ClearedBranch if Overflow Flag is Set
Rd ← Rd • RrRd ← Rd • KRd ← Rd v RrRd ← Rd v KRd ← Rd ⊕ RrRd ← 0xFF − RdRd ← 0x00 − RdRd ← Rd v KRd ← Rd • (0xFF - K)Rd ← Rd + 1Rd ← Rd − 1 Rd ← Rd • Rd Rd ← Rd ⊕ RdRd ← 0xFFR1:R0 ← Rd x RrR1:R0 ← Rd x RrR1:R0 ← Rd x RrR1:R0 ← (Rd x Rr) << 1R1:R0 ← (Rd x Rr) << 1PC ← PC + k + 1PC ← Z PC ←k
PC ← PC + k + 1PC ←ZPC ←kPC ← STACKPC ← STACK
if (Rd = Rr) PC ← PC + 2 or 3Rd − RrRd − Rr − CRd − K
if (Rr(b)=0) PC ← PC + 2 or 3 if (Rr(b)=1) PC ← PC + 2 or 3if (P(b)=0) PC ← PC + 2 or 3 if (P(b)=1) PC ← PC + 2 or 3if (SREG(s) = 1) then PC←PC+k + 1if (SREG(s) = 0) then PC←PC+k + 1if (Z = 1) then PC ← PC + k + 1if (Z = 0) then PC ← PC + k + 1if (C = 1) then PC ← PC + k + 1if (C = 0) then PC ← PC + k + 1if (C = 0) then PC ← PC + k + 1if (C = 1) then PC ← PC + k + 1if (N = 1) then PC ← PC + k + 1if (N = 0) then PC ← PC + k + 1if (N ⊕ V= 0) then PC ← PC + k + 1if (N ⊕ V= 1) then PC ← PC + k + 1if (H = 1) then PC ← PC + k + 1if (H = 0) then PC ← PC + k + 1if (T = 1) then PC ← PC + k + 1if (T = 0) then PC ← PC + k + 1if (V = 1) then PC ← PC + k + 1R1:R0 ← (Rd x Rr) << 1BRANCH INSTRUCTIONS
12
ATmega164P/324P/644P
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ATmega164P/324P/644P
Mnemonics
BRVCBRIEBRIDSBICBILSLLSRROLRORASRSWAPBSETBCLRBSTBLDSECCLCSENCLNSEZCLZSEICLISESCLSSEVCLVSETCLTSEHCLH
DATA TRANSFER INSTRUCTIONSMOVMOVWLDILDLDLDLDLDLDLDDLDLDLDLDDLDSSTSTSTSTSTSTSTDSTSTSTSTDSTSLPMLPMLPMELPMELPMELPM
Rd, ZRd, Z+Rd, ZRd, Z+Rd, RrRd, RrRd, KRd, XRd, X+Rd, - XRd, YRd, Y+Rd, - YRd,Y+qRd, ZRd, Z+Rd, -ZRd, Z+qRd, kX, RrX+, Rr- X, RrY, RrY+, Rr- Y, RrY+q,RrZ, RrZ+, Rr-Z, RrZ+q,Rrk, Rr
Move Between RegistersCopy Register WordLoad ImmediateLoad Indirect
Load Indirect and Post-Inc.Load Indirect and Pre-Dec.Load Indirect
Load Indirect and Post-Inc.Load Indirect and Pre-Dec.Load Indirect with DisplacementLoad Indirect
Load Indirect and Post-Inc.Load Indirect and Pre-Dec.Load Indirect with DisplacementLoad Direct from SRAMStore Indirect
Store Indirect and Post-Inc.Store Indirect and Pre-Dec.Store Indirect
Store Indirect and Post-Inc.Store Indirect and Pre-Dec.Store Indirect with DisplacementStore Indirect
Store Indirect and Post-Inc.Store Indirect and Pre-Dec.Store Indirect with DisplacementStore Direct to SRAMLoad Program MemoryLoad Program Memory
Load Program Memory and Post-IncExtended Load Program MemoryExtended Load Program MemoryExtended Load Program Memory
Rd ← Rr
Rd+1:Rd ← Rr+1:RrRd ←KRd ← (X)
Rd ← (X), X ← X + 1X ← X - 1, Rd ← (X)Rd ← (Y)
Rd ← (Y), Y ← Y + 1Y ← Y - 1, Rd ← (Y)Rd ← (Y + q)Rd ← (Z)
Rd ← (Z), Z ← Z+1Z ← Z - 1, Rd ← (Z)Rd ← (Z + q)Rd ← (k)(X) ← Rr
(X) ← Rr, X ← X + 1X ← X - 1, (X) ← Rr(Y) ← Rr
(Y) ← Rr, Y ← Y + 1Y ← Y - 1, (Y) ← Rr(Y + q) ← Rr(Z) ← Rr
(Z) ← Rr, Z ← Z + 1Z ← Z - 1, (Z) ← Rr(Z + q) ← Rr(k) ← RrR0 ← (Z)Rd ← (Z)
Rd ← (Z), Z ← Z+1R0 ← (RAMPZ:Z)Rd ← (Z)
Rd ← (RAMPZ:Z), RAMPZ:Z ←RAMPZ:Z+1
NoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNone
111222222222222222222222222333333
k k kP,bP,bRdRdRdRdRdRdssRr, bRd, b
OperandsDescription
Branch if Overflow Flag is ClearedBranch if Interrupt EnabledBranch if Interrupt DisabledSet Bit in I/O RegisterClear Bit in I/O RegisterLogical Shift LeftLogical Shift RightRotate Left Through CarryRotate Right Through CarryArithmetic Shift RightSwap NibblesFlag Set
Operation
if (V = 0) then PC ← PC + k + 1if ( I = 1) then PC ← PC + k + 1if ( I = 0) then PC ← PC + k + 1I/O(P,b) ←1I/O(P,b) ←0
Rd(n+1) ← Rd(n), Rd(0) ← 0Rd(n) ← Rd(n+1), Rd(7) ← 0Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)
Flags
NoneNoneNoneNoneNoneZ,C,N,VZ,C,N,VZ,C,N,VZ,C,N,VZ,C,N,VNoneSREG(s)SREG(s)TNoneCCNNZZIISSVVTTHH
#Clocks
1/21/21/22211111111111111111111111111
BIT AND BIT-TEST INSTRUCTIONS
Rd(n) ← Rd(n+1), n=0..6
Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)
SREG(s) ← 1
Flag ClearSREG(s) ← 0 Bit Store from Register to T T ← Rr(b)Bit load from T to RegisterSet CarryClear CarrySet Negative FlagClear Negative FlagSet Zero FlagClear Zero FlagGlobal Interrupt EnableGlobal Interrupt DisableSet Signed Test FlagClear Signed Test Flag
Set Twos Complement Overflow.Clear Twos Complement OverflowSet T in SREGClear T in SREG
Set Half Carry Flag in SREGClear Half Carry Flag in SREG
Rd(b) ←T C ←1
C ← 0
N ←1N ← 0 Z ←1
Z ← 0
I ←1I ← 0 S ←1
S ← 0 V ←1V ← 0 T ←1T ← 0
H ←1
H ← 0 13
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Mnemonics
SPMINOUTPUSHPOPNOPSLEEPWDRBREAK
Operands
Store Program Memory
Rd, PP, RrRrRd
In PortOut Port
Push Register on Stack
Description
(Z) ← R1:R0Rd ←PP ← RrSTACK ← RrRd ← STACK
OperationFlags
NoneNoneNoneNoneNoneNone
#Clocks
-1122111N/A
Pop Register from StackNo OperationSleep
Watchdog ResetBreak
MCU CONTROL INSTRUCTIONS
(see specific descr. for Sleep function)(see specific descr. for WDR/timer)For On-chip Debug Only
NoneNoneNone
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ATmega164P/324P/644P
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ATmega164P/324P/644P
6.Ordering Information
6.1
ATmega164P
Power Supply1.8 - 5.5V
Ordering CodeATmega164PV-10AU(2)ATmega164PV-10PU(2)ATmega164PV-10MU(2)ATmega164P-20AU(2)ATmega164P-20PU(2)ATmega164P-20MU(2)
Package(1)44A40P644M144A40P644M1
Operational RangeIndustrial(-40oC to 85oC)Industrial(-40oC to 85oC)
Speed (MHz)(3)
10
202.7 - 5.5V
Notes:
1.This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2.Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3.For Speed vs. VCC see ”Maximum speed vs. VCC” on page 323.
Package Type
44A40P644M1
44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)40-pin, 0.600” Wide, Plastic Dual Inline Package (PDIP)
44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
15
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6.2ATmega324P
Power Supply1.8 - 5.5V
Ordering CodeATmega324PV-10AU(2)ATmega324PV-10PU(2)ATmega324PV-10MU(2)ATmega324P-20AU(2)ATmega324P-20PU(2)ATmega324P-20MU(2)
Package(1)44A40P644M144A40P644M1
Operational RangeIndustrial(-40oC to 85oC)Industrial(-40oC to 85oC)
Speed (MHz)(3)
10
202.7 - 5.5V
Notes:
1.This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2.Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3.For Speed vs. VCC see ”Maximum speed vs. VCC” on page 323.
Package Type
44A40P644M1
44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)40-pin, 0.600” Wide, Plastic Dual Inline Package (PDIP)
44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
16
ATmega164P/324P/644P
8011DS–AVR–02/07
元器件交易网www.cecb2b.com
ATmega164P/324P/644P
6.3
ATmega644P
Power Supply1.8 - 5.5V
Ordering CodeATmega644PV-10AU(2)ATmega644PV-10PU(2)ATmega644PV-10MU(2)ATmega644P-20AU(2)ATmega644P-20PU(2)ATmega644P-20MU(2)
Package(1)44A40P644M144A40P644M1
Operational RangeIndustrial(-40oC to 85oC)Industrial(-40oC to 85oC)
Speed (MHz)(3)
10
202.7 - 5.5V
Notes:
1.This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2.Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3.For Speed vs. VCC see ”Maximum speed vs. VCC” on page 323.
Package Type
44A40P644M1
44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)40-pin, 0.600” Wide, Plastic Dual Inline Package (PDIP)
44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
17
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7.Packaging Information
7.1
44A
PIN 1 BPIN 1 IDENTIFIEReE1ED1DC0˚~7˚A1A2ACOMMON DIMENSIONS(Unit of Measure = mm)SYMBOLAA1A2DD1Notes:1.This package conforms to JEDEC reference MS-026, Variation ACB. 2.Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch.3. Lead coplanarity is 0.10 mm maximum.EE1MIN–0.05 0.9511.759.9011.759.90NOM––1.0012.0010.0012.0010.00–––0.80 TYPMAX1.200.151.0512.2510.1012.2510.100.450.20 0.75Note 2Note 2 NOTELB 0.30CLe0.090.4510/5/2001 2325 Orchard Parkway San Jose, CA 95131TITLE44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness,0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) DRAWING NO.44AREV. BR18
ATmega164P/324P/644P
8011DS–AVR–02/07
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ATmega164P/324P/644P
7.2
40P6
DPIN1E1ASEATING PLANELB1eE0º ~ 15º REFBA1CeBCOMMON DIMENSIONS(Unit of Measure = mm)SYMBOLAA1DEE1BMIN–0.38152.07015.24013.4620.3561.0413.0480.20315.494NOM––––––––––2.540 TYPMAX4.826–52.57815.87513.9700.5591.6513.556 0.381 17.526Note 2Note 2NOTENotes:1.This package conforms to JEDEC reference MS-011, Variation AC. 2.Dimensions D and E1 do not include mold Flash or Protrusion.Mold Flash or Protrusion shall not exceed 0.25 mm (0.010\").B1LCeBe09/28/01 2325 Orchard Parkway San Jose, CA 95131TITLE40P6, 40-lead (0.600\"/15.24 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO.40P6REV. BR19
8011DS–AVR–02/07
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7.344M1
DMarked Pin# 1 IDESEATING PLANETOP VIEWA1A3KLD2Pin #1 CornerASIDE VIEW123Option APin #1 TriangleCOMMON DIMENSIONS(Unit of Measure = mm)SYMBOLOption BPin #1 Chamfer(C 0.30)E2MIN0.80 – 0.18 6.905.006.905.00 0.59 0.20NOM0.90 0.02 0.25 REF0.237.005.207.005.200.50 BSC0.64 0.26MAX1.000.05NOTE A A1 A3 b 0.307.105.407.105.40KbeOption C D Pin #1 Notch(0.20 R) D2 E E2 e BOTTOM VIEWNote: JEDEC Standard MO-220, Fig. 1 (SAW Singulation) VKKD-3. L K0.690.415/27/06 2325 Orchard Parkway San Jose, CA 95131TITLE44M1, 44-pad, 7 x 7 x 1.0 mm Body, Lead Pitch 0.50 mm, 5.20 mm Exposed Pad, Micro Lead Frame Package (MLF) DRAWING NO.44M1REV. GR20
ATmega164P/324P/644P
8011DS–AVR–02/07
元器件交易网www.cecb2b.com
8.Errata
8.1
ATmega164P Rev. A
No known Errata.
8.2ATmega324P Rev. A
No known Errata.
8.3ATmega644P Rev. A
No known Errata.
8011DS–AVR–02/07
ATmega164P/324P/644P
21
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9.Datasheet Revision History
Please note that the referring page numbers in this section are referred to this document. Thereferring revision in this section are referring to the document revision.
9.1Rev. 8011D - 02/07
1.2.3.4.5.6.7.8.9.10.Updated ”Pinout ATmega164P/324P/644P” on page 2.Updated ”Power-down Mode” on page 44.Updated note in Table 11-1 on page 67.Updated Table 23-1 on page 270.
Updated ”Boot Size Configuration(1)” on page 287.
Updated VOL limits in ”DC Characteristics” on page 323.Updated note 3 and 4 in ”DC Characteristics” on page 323.Added note to ”ATmega164P DC Characteristics” on page 325.Added note to ”ATmega324P DC Characteristics” on page 325.Updated Figure 27-13 on page 343 and Figure 27-60 on page 368.
9.2Rev. 8011C - 10/06
1.Updated ”DC Characteristics” on page 323.
9.3Rev. 8011B - 09/06
1.Updated ”DC Characteristics” on page 323.
9.4Rev. 8011A - 08/06
1.Initial revision.
22
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8011DS–AVR–02/07
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