•400 MHz ARM926EJ-S™ ARM® Thumb® Processor–32 KBytes Data Cache, 32 KBytes Instruction Cache, MMU•
Memories
–Dual External Bus Interface supporting 4-bank DDR2/LPDDR, SDRAM/LPSDR, Static Memories, CompactFlash, SLC NAND Flash with ECC
–One 64-kbyte internal SRAM, single-cycle access at system speed or processor speed through TCM interface
–One 64-kbyte internal ROM, embedding bootstrap routine•
Peripherals
–LCD Controller supporting STN and TFT displays up to 1280*860–ITU-R BT. 601/656 Image Sensor Interface
–USB Device High Speed, USB Host High Speed and USB Host Full Speed with On-Chip Transceiver
–10/100 Mbps Ethernet MAC Controller
–Two High Speed Memory Card Hosts (SDIO, SDCard, MMC)–AC'97 controller
–Two Master/Slave Serial Peripheral Interfaces–Two Three-channel 32-bit Timer/Counters
–Two Synchronous Serial Controllers (I2S mode)–Four-channel 16-bit PWM Controller–Two Two-wire Interfaces
–Four USARTs with ISO7816, IrDA, Manchester and SPI modes–8-channel 10-bit ADC with 4-wire Touch Screen support•
System
–133 MHz twelve 32-bit layer AHB Bus Matrix–37 DMA Channels
–Boot from NAND Flash, SDCard, DataFlash® or serial DataFlash –Reset Controller with on-chip Power-on Reset
–Selectable 32768 Hz Low-power and 12 MHz Crystal Oscillators–Internal Low-power 32 kHz RC Oscillator
–One PLL for the system and one 480 MHz PLL optimized for USB High Speed–Two Programmable External Clock Signals–Advanced Interrupt Controller and Debug Unit
–Periodic Interval Timer, Watchdog Timer, Real Time Timer and Real Time Clock•
I/O
–Five 32-bit Parallel Input/Output Controllers
–160 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os with Schmitt trigger input•
Package
–324-ball LFBGA, pitch 0.8 mm
AT91 ARM Thumb-based MicrocontrollersAT91SAM9G45PreliminarySummaryNOTE: This is a summary document. The complete document is available on the Atmel website at www.atmel.com. 6438BS–ATARM–13-Aug-091.Description
The ARM926EJ-S based AT91SAM9G45 features the frequently demanded combination of userinterface functionality and high data rate connectivity, including LCD Controller, resistive touch-screen, camera interface, audio, Ethernet 10/100 and high speed USB and SDIO. With the pro-cessor running at 400MHz and multiple 100+ Mbps data rate peripherals, the AT91SAM9G45has the performance and bandwidth to the network or local storage media to provide an ade-quate user experience.
The AT91SAM9G45 supports the latest generation of DDR2 and NAND Flash memory inter-faces for program and data storage. An internal 133 MHz multi-layer bus architecture associatedwith 37 DMA channels, a dual external bus interface and distributed memory including a 64-Kbyte SRAM which can be configured as a tightly coupled memory (TCM) sustains the highbandwidth required by the processor and the high speed peripherals.
The I/Os support 1.8V or 3.3V operation, which are independently configurable for the memoryinterface and peripheral I/Os. This feature completely eliminates the need for any external levelshifters. In addition it supports 0.8 ball pitch package for low cost PCB manufacturing.
The AT91SAM9G45 power management controller features efficient clock gating and a batterybackup section minimizing power consumption in active and standby modes.
2
AT91SAM9G45
6438BS–ATARM–13-Aug-09
Figure 2-1.
2.Block Diagram
AT91SAM9G45 Block Diagram
LKAS1KEAT91SAM9G45
35CACE11_CBDWADR____]1]2S DRR.1DRR,..K0N2SDD0.DDR#DD DW8SC13A01CDDF[0[,, N1AE1SNSSWECD--EMSES,/00RQQSKLKAE002ACDSD]]B ,]CCNFN DSADVDDCCCRWAB5SS,01AS1.1WSBNE13.RCA/3.4FF___________15AAS# .NN3ORRRRRRRRRRRDBB1/,C ,.0. E[0//01NNABB1K,//R0DDT22CCF-1NI[A//45C-E/23DDDDDDDDDDD--67SCSWM[SDRR0//01211CDADQQRWWWSCNA6AM-SS/CSS1WQ91CC52FCCDDDDDDDDDDDDAAAAANSRSDDNNNNNNDNDANNACNNrhr/srye2R/aelllcrlRDI2RMeliBRDAloFoCtolo DDEDDRrtDrtCFarttmDPDPDnNnECSenMo LLSoCAoNCCNABPADNNAAGFnEDOICeDeDRD7V3DrCHAVXCDMEAcDC tSVD3P-i8BhXXTE-0M0cPYPD3GAM-4STYDADAPRRXE1uGE-E-0XTE HAToM2RLOCREXRCXDA-MKEE8DP1DXACXR0XTERE--SEE-NRGIDAKECCXERXTTTECACKEAXDMMDC7D9XTACNCNYM_IER7PCA79STYSV_SI9CSAOlIarKFD1SHIreO1PlC7C9AMDelD__IKCPISISIhAo17CSI-_IIASpMrtK9CCA_irIMDn1CDeoCNCL ,ODSCIDR_IPCC01FR-A101RSBYDCCD-K0RSMS PSS xSS1,_BDHCL,WPSDICi0MSDCKCTNEDLrCDH3t1DR-FT0R-SH2L,CNODDLa0DRF/DlSHMDA/DDSDMSCYVCLCMMa1FTSrDHLDK- eeT0DTSDBhg-FF,LB-0DDDpdi,PBDDCLCHirrO0TPSLDHAeBPISSHF/PrSIKTM_He /DrPSvC011iIII DHSDSeSBAFyeDPPPDHcs0KOCMPnHSMUDaaPSSS1S ,ATrLGSCS_-0IiNAMGBt2CPPMDVlRDSSHuMO3SPNSFH,IHrPSCN,APeBITCPAPDvCSPNiPDS eHOASHS3455NFHHHcsEHM nCCCaSBDTTT5BTrPAHSSU5AOITMKOI-3BB0122LT-3OIBCCCCOTLesEShetDTTT2I-T3AKOITTGATJnceA-0LBCaabyca2OcCK fKIOITSro D2rILT-TeHMC0K tS3tTCTya-nC-WI 4P3-Al0OIrJKRausMKdmEUuWLTSCTnE6MBPC-Tu t2MiOMTou9s30BceM0123DMWrMtID iCDT/Reh CbyTCRTRTRTRT3XPTG-KDMBMBDAAAAXT-nAcaTIC AKSI2MR4OKPSSSSR43D0-DRTA36UUUUKR0XTTNJCS6T3CXI3SS-0DTR-KSR0Cr01II1T-SSeWWKClC0TSRloUCCRTTT1rDCCDEDWTTtCGnIPMTI4BTW-CPPPTTOOIIT0GRRSRPP-KoABD0CC1DWI7 IAmDWTTeAMMKOCOILT2T2CFMD/IK_tLU13RRABC DF0SATA /IEC1Is_CyPDCLCCHOOOOOCDCSLSWRSPPIIIPPPMSA1PIOPOOSDIM-07CCA_MAD1,K_1IDI_CCM_C0,0IIMCAM-DCMT1ANT220CSKQQDDICI33NPUTEA_D0ITCFRXXIRXUONTDUBSR_CPRTIHKDR0LIM-DDLXXUOOSWDNCC0PXVDMKCDPV6438BS–ATARM–13-Aug-09
3
3.Signal Description
Table 3-1 gives details on the signal names classified by peripheral.
Table 3-1.
Signal Name
Signal Description List
Function
TypePower Supplies
Active Level
Reference Voltage
Comments
VDDIOM0VDDIOM1VDDIOP0VDDIOP1VDDIOP2VDDBUVDDANAVDDPLLAVDDPLLUTMIVDDOSCVDDCOREVDDUTMICVDDUTMIIGNDIOMGNDIOPGNDCOREGNDOSCGNDBUGNDUTMIGNDANA
DDR2 I/O Lines Power SupplyEBI I/O Lines Power SupplyPeripherals I/O Lines Power SupplyPeripherals I/O Lines Power SupplyISI I/O Lines Power SupplyBackup I/O Lines Power SupplyAnalog Power SupplyPLLA Power SupplyPLLUTMI Power SupplyOscillator Power SupplyCore Chip Power Supply
UDPHS and UHPHS UTMI+ Core Power Supply
UDPHS and UHPHS UTMI+ interface Power Supply
DDR2 and EBI I/O Lines GroundPeripherals and ISI I/O lines GroundCore Chip Ground
PLLA, PLLUTMI and Oscillator GroundBackup Ground
UDPHS and UHPHS UTMI+ Core and interface GroundAnalog Ground
PowerPowerPowerPowerPowerPowerPowerPowerPowerPowerPowerPowerPowerGroundGroundGroundGroundGroundGroundGround
Clocks, Oscillators and PLLs
1.65V to 1.95V
1.65V to 1.95V or 3.0V to3.6V1.65V to 3.6V1.65V to 3.6V1.65V to 3.6V1.8V to 3.6V3.0V to 3.6V0.9V to 1.1V0.9V to 1.1V1.65V to 3.6V0.9V to 1.1V0.9V to 1.1V3.0V to 3.6V
XINXOUTXIN32XOUT32VBGPCK0 - PCK1
Main Oscillator InputMain Oscillator OutputSlow Clock Oscillator InputSlow Clock Oscillator OutputBias Voltage Reference for USBProgrammable Clock Output
InputOutputInputOutputAnalogOutput
(1)
4
AT91SAM9G45
6438BS–ATARM–13-Aug-09
AT91SAM9G45
Table 3-1.Signal NameSignal Description List (Continued)FunctionTypeActive LevelReference VoltageCommentsShutdown, Wakeup LogicDriven at 0V only. 0: The device is in backup mode1: The device is running (not in backup mode).Accept between 0V and VDDBU.SHDNShut-Down ControlOutputVDDBUWKUPWake-Up InputInputICE and JTAGVDDBUTCKTDITDOTMSJTAGSELRTCKTest ClockTest Data InTest Data OutTest Mode SelectJTAG SelectionReturn Test Clock InputInputOutputInputInputOutputReset/TestVDDIOP0VDDIOP0VDDIOP0VDDIOP0VDDBUVDDIOP0No pull-up resistor, Schmitt triggerNo pull-up resistor, Schmitt triggerNo pull-up resistor, Schmitt triggerPull-down resistor (15 kΩ).NRSTMicrocontroller Reset(2)I/OLowVDDIOP0Open-drain output,Pull-Up resistor (100 kΩ), Schmitt triggerPull-down resistor (15 kΩ), Schmitt triggerPull-Up resistor (100 kΩ),Schmitt triggermust be connected to GND or VDDIOP.TSTNTRSTBMSTest Mode SelectTest Reset SignalBoot Mode SelectInputInputInputDebug Unit - DBGUVDDBUVDDIOP0VDDIOP0DRXDDTXDDebug Receive DataDebug Transmit DataInputOutputAdvanced Interrupt Controller - AIC(1)(1)IRQFIQExternal Interrupt InputFast Interrupt InputInputInput(1)(1)PIO Controller - PIOA- PIOB - PIOC - PIOD - PIOEPA0 - PA31PB0 - PB31Parallel IO Controller AParallel IO Controller BI/OI/O(1)Pulled-up input at reset (100kΩ)(3), Schmitt triggerPulled-up input at reset (100kΩ)(3), Schmitt trigger(1)5
6438BS–ATARM–13-Aug-09
Table 3-1.Signal NamePC0 - PC31PD0 - PD31PE0 - PE31Signal Description List (Continued)FunctionParallel IO Controller CParallel IO Controller DParallel IO Controller ETypeI/OI/OI/OActive LevelReference Voltage(1)CommentsPulled-up input at reset (100kΩ)(3), Schmitt triggerPulled-up input at reset (100kΩ)(3), Schmitt triggerPulled-up input at reset (100kΩ)(3), Schmitt trigger(1)(1)DDR Memory Interface- DDR2/SDRAM/LPDDR ControllerDDR_D0 - DDR_D15DDR_A0 - DDR_A13DDR_CLK-#DDR_CLKDDR_CKEDDR_CSDDR_WEDDR_RAS-DDR_CASDDR_DQM[0..1]DDR_DQS[0..1]DDR_BA0 - DDR_BA1DDR_VREFData BusAddress BusDDR differential clock inputDDR Clock EnableDDR Chip SelectDDR Write EnableRow and Column SignalWrite Data MaskData StrobeBank SelectReference VoltageI/OOutputOutputOutputOutputOutputOutputOutputOutputOutputInputExternal Bus Interface - EBID0 -D31A0 - A25NWAITData BusAddress BusExternal Wait SignalI/OOutputInputLowVDDIOM1VDDIOM1VDDIOM1Pulled-up input at reset0 at resetHighLowLowLowVDDIOM0VDDIOM0VDDIOM0VDDIOM0VDDIOM0VDDIOM0VDDIOM0VDDIOM0VDDIOM0VDDIOM0VDDIOM0Pulled-up input at reset0 at resetStatic Memory Controller - SMCNCS0 - NCS5NWR0 - NWR3NRDNWENBS0 - NBS3Chip Select LinesWrite SignalRead SignalWrite EnableByte Mask SignalOutputOutputOutputOutputOutputLowLowLowLowLowVDDIOM1VDDIOM1VDDIOM1VDDIOM1VDDIOM1CompactFlash SupportCFCE1 - CFCE2CFOECFWECFIORCompactFlash Chip EnableCompactFlash Output EnableCompactFlash Write EnableCompactFlash IO Read OutputOutputOutputOutputLowLowLowLowVDDIOM1VDDIOM1VDDIOM1VDDIOM16
AT91SAM9G45
6438BS–ATARM–13-Aug-09
AT91SAM9G45
Table 3-1.Signal NameCFIOWCFRNWCFCS0 -CFCS1Signal Description List (Continued)FunctionCompactFlash IO WriteCompactFlash Read Not WriteCompactFlash Chip Select LinesTypeOutputOutputOutputLowActive LevelLowReference VoltageVDDIOM1VDDIOM1VDDIOM1CommentsNAND Flash SupportNANDCSNANDOENANDWENAND Flash Chip SelectNAND Flash Output EnableNAND Flash Write EnableOutputOutputOutputLowLowLowVDDIOM1VDDIOM1VDDIOM1DDR2/SDRAM/LPDDR ControllerSDCK,#SDCKSDCKESDCSBA0 - BA1SDWERAS - CASSDA10DQS[0..1]DQM[0..3]DDR2/SDRAM differential clockDDR2/SDRAM Clock EnableDDR2/SDRAM Controller Chip SelectBank SelectDDR2/SDRAM Write EnableRow and Column SignalSDRAM Address 10 LineData StrobeWrite Data MaskOutputOutputOutputOutputOutputOutputOutputOutputOutputLowLowHighLowVDDIOM1VDDIOM1VDDIOM1VDDIOM1VDDIOM1VDDIOM1VDDIOM1VDDIOM1VDDIOM1 High Speed Multimedia Card Interface - HSMCIxMCIx_CKMCIx_CDAMCIx_DA0 - MCIx_DA7Multimedia Card ClockMultimedia Card Slot A CommandMultimedia Card Slot A DataI/OI/OI/O(1)(1)(1)Universal Synchronous Asynchronous Receiver Transmitter - USARTxSCKxTXDxRXDxRTSxCTSxUSARTx Serial ClockUSARTx Transmit DataUSARTx Receive DataUSARTx Request To SendUSARTx Clear To Send I/OOutputInputOutputInputSynchronous Serial Controller - SSCxTDxRDxTKxRKxTFxRFxSSC Transmit DataSSC Receive DataSSC Transmit ClockSSC Receive ClockSSC Transmit Frame SyncSSC Receive Frame SyncOutputInputI/OI/OI/OI/O(1)(1)(1)(1)(1)(1)(1)(1)(1)(1)(1)7
6438BS–ATARM–13-Aug-09
Table 3-1.Signal NameSignal Description List (Continued)FunctionTypeActive LevelReference VoltageCommentsAC97 Controller - AC97CAC97RXAC97TXAC97FSAC97CKAC97 Receive SignalAC97 Transmit SignalAC97 Frame Synchronization SignalAC97 Clock signalInputOutputOutputInputTime Counter - TCxTCLKxTIOAxTIOBxTC Channel x External Clock InputTC Channel x I/O Line ATC Channel x I/O Line BInputI/OI/O(1)(1)(1)(1)(1)(1)(1)Pulse Width Modulation Controller - PWMPWMxPulse Width Modulation Output Output(1)Serial Peripheral Interface - SPIx_SPIx_MISOSPIx_MOSISPIx_SPCKSPIx_NPCS0SPIx_NPCS1-SPIx_NPCS3Master In Slave OutMaster Out Slave InSPI Serial ClockSPI Peripheral Chip Select 0SPI Peripheral Chip SelectI/OI/OI/OI/OOutputLowLow(1)(1)(1)(1)(1)Two-Wire InterfaceTWDxTWCKxTwo-wire Serial Data Two-wire Serial ClockI/OI/OUSB Host High Speed Port - UHPHSHFSDPAHFSDMAHHSDPAHHSDMAHFSDPBHFSDMBHHSDPBHHSDMBUSB Host Port A Full Speed Data +USB Host Port A Full Speed Data -USB Host Port A High Speed Data +USB Host Port A High Speed Data -USB Host Port B Full Speed Data +USB Host Port B Full Speed Data -USB Host Port B High Speed Data +USB Host Port B High Speed Data -AnalogAnalogAnalogAnalogAnalogAnalogAnalogAnalogVDDUTMIIVDDUTMIIVDDUTMIIVDDUTMIIVDDUTMIIVDDUTMIIVDDUTMIIVDDUTMIIMultiplexed with DFSDPMultiplexed with DFSDMMultiplexed with DHSDPMultiplexed with DHSDM(1)(1)USB Device High Speed Port - UDPHSDFSDMDFSDPDHSDMDHSDPUSB Device Full Speed Data -USB Device Full Speed Data +USB Device High Speed Data -USB Device High Speed Data +AnalogAnalogAnalogAnalogVDDUTMIIVDDUTMIIVDDUTMIIVDDUTMII8
AT91SAM9G45
6438BS–ATARM–13-Aug-09
AT91SAM9G45
Table 3-1.Signal NameSignal Description List (Continued)FunctionTypeEthernet 10/100 Active LevelReference VoltageCommentsETXCKERXCKETXENETX0-ETX3ETXERERXDVERX0-ERX3ERXERECRSECOLEMDCEMDIOTransmit Clock or Reference ClockReceive ClockTransmit EnableTransmit DataTransmit Coding ErrorReceive Data ValidReceive DataReceive ErrorCarrier Sense and Data ValidCollision DetectManagement Data ClockManagement Data Input/OutputInputInputOutputOutputOutputInputInputInputInputInputOutputI/O(1)(1)(1)(1)(1)(1)(1)(1)(1)(1)(1)(1)MII only, REFCK in RMIIMII onlyETX0-ETX1 only in RMIIMII onlyRXDV in MII, CRSDV in RMIIERX0-ERX1 only in RMIIMII onlyMII onlyImage Sensor InterfaceISI_D0-ISI_D11 ISI_MCKISI_HSYNCISI_VSYNCISI_PCK Image Sensor Data Image sensor Reference clockImage Sensor Horizontal SynchroImage Sensor Vertical SynchroImage Sensor Data clockInputoutputinputinputinputLCD Controller - LCDCLCDD0 - LCDD23LCDVSYNCLCDHSYNCLCDDOTCKLCDDENLCDCCLCDPWRLCDMODLCD Data BusLCD Vertical SynchronizationLCD Horizontal SynchronizationLCD Dot ClockLCD Data EnableLCD Contrast ControlLCD panel Power enable control LCD Modulation signalOutputOutputOutputOutputOutputOutputOutputOutputVDDIOP1VDDIOP1VDDIOP1VDDIOP1VDDIOP1VDDIOP1VDDIOP1VDDIOP1VDDIOP2VDDIOP2VDDIOP2VDDIOP2VDDIOP2Touch Screen Analog-to-Digital ConverterAD0XPAD1XMAD2YPAD3YMTouch Panel Right sideTouch Panel Left sideTouch Panel Top sideTouch Panel Bottom sideAnalogAnalogAnalogAnalogVDDANAVDDANAVDDANAVDDANAMultiplexed with AD0Multiplexed with AD1Multiplexed with AD2Multiplexed with AD39
6438BS–ATARM–13-Aug-09
Table 3-1.
Signal Name
Signal Description List (Continued)
Function
Analog InputsADC TriggerADC Reference
TypeAnalogInputAnalog
Active Level
Reference VoltageVDDANAVDDANAVDDANA
Comments
GPAD4-GPAD7TSADTRGTSADVREFNotes:
1.Refer to peripheral multiplexing tables in Section 9.4 “Peripheral Signals Multiplexing on I/O Lines” for these signals.2.When configured as an input, the NRST pin enables asynchronous reset of the device when asserted low. This allows con-nection of a simple push button on the NRST pin as a system-user reset.3.Programming of this pull-up resistor is performed independently for each I/O line through the PIO Controllers. After reset, all
the I/O lines default as inputs with pull-up resistors enabled, except those which are multiplexed with the External Bus Inter-face signals that require to be enabled as Peripheral at reset. This is explicitly indicated in the column “Reset State” of the peripheral multiplexing tables.
10
AT91SAM9G45
6438BS–ATARM–13-Aug-09
AT91SAM9G45
4.Package and Pinout
The AT91SAM9G45 is delivered in a 324-ball LFBGA package. 4.1Mechanical Overview of the 324-ball LFBGA Package
Figure 4-1 shows the orientation of the 324-ball LFBGA PackageFigure 4-1.
Orientation of the 324-ball LFBGA Package
Bottom VIEWVUTRPNMLKJHGFEDCBA1234567891011121314151617186438BS–ATARM–13-Aug-09
11
4.2324-ball TFBGA Package Pinout
AT91SAM9G45 Pinout for 324-ball BGA PackagePinE10E11E12E13E14E15E16E17E18F1F2F3F4F5F6F7F8F9F10F11F12F13F14F15F16F17F18G1G2G3G4G5G6G7G8G9G10G11G12G13G14G15G16G17G18H1H2H3Signal NameNANDWEDQS1D13D11A4A8A9A7VDDCOREPD22PD24SHDNPE1PE3VDDIOM1PC19PC14PC4NCS1/SDCSNRDSDWEA0/NBS0A1/NBS2/NWR2A3A6A5A2PD25PD23PE6PE0PE2PE8PE4PE11GNDCOREVDDIOM1VDDIOM1VDDCOREVDDCOREDDR_DQM0DDR_DQS1DDR_BA1DDR_BA0DDR_DQS0PD26PD27VDDIOP1PinK1K2K3K4K5K6K7K8K9K10K11K12K13K14K15K16K17K18L1L2L3L4L5L6L7L8L9L10L11L12L13L14L15L16L17L18M1M2M3M4M5M6M7M8M9M10M11M12Signal NamePE21PE23PE26PE22PE24PE25PE27PE28VDDIOP0VDDIOP0GNDIOMGNDIOMVDDIOM0DDR_A7DDR_A8DDR_A9DDR_A11DDR_A10PA0PE30PE29PE31PA2PA4PA8PD2PD13PD29PD31VDDIOM0VDDIOM0DDR_A1DDR_A3DDR_A4DDR_A6DDR_A5PA1PA5PA6PA7PA10PA14PB14PD4PD15NRSTPB11PB25PinP10P11P12P13P14P15P16P17P18R1R2R3R4R5R6R7R8R9R10R11R12R13R14R15R16R17R18T1T2T3T4T5T6T7T8T9T10T11T12T13T14T15T16T17T18U1U2U3Signal NameTMSVDDPLLAPB20PB31DDR_D7DDR_D3DDR_D4DDR_D5DDR_D10PA18PA20PA24PA30PB4PB13PD0PD9PD18TDIRTCKPB22PB29DDR_D6DDR_D1DDR_D0HHSDMAHFSDMAPA22PA25PA26PB0PB6PB16PD1PD11PD19PD30BMSPB8PB30DDR_D2PB21PB23HHSDPAHFSDPAPA27PA29PA28Table 4-1.PinA1A2A3A4A5A6A7A8A9A10A11A12A13A14A15A16A17A18B1B2B3B4B5B6B7B8B9B10B11B12B13B14B15B16B17B18C1C2C3C4C5C6C7C8C9C10C11C12PC27PC28PC25PC20PC12PC7PC5PC0Signal NameNWR3/NBS3NCS0DQS0RASSDCKNSDCKD7DDR_VREFD0A14PC31PC29PC30PC22PC17PC10PC11PC2SDA10A17/BA1DQM0SDCKED12D8D4D3A15A13XIN32GNDANAWKUPPC26PC21PC15PC9PC3NWR0/NWEA16/BA0CASD1512
AT91SAM9G45
6438BS–ATARM–13-Aug-09
Table 4-1.
AT91SAM9G45 Pinout for 324-ball BGA PackagePinSignal NamePinSignal NamePinSignal NameC13D10H4PE13M13PB27C14D6H5PE5M14VDDIOM0C15D2H6PE7M15DDR_D14C16GNDIOMH7PE9M16DDR_D15C17A18H8PE10M17DDR_A0C18A12H9GNDCOREM18DDR_A2D1XOUT32H10GNDIOPN1PA3D2PD20H11VDDCOREN2PA9D3GNDBUH12GNDIOMN3PA12D4VDDBUH13GNDIOMN4PA15D5PC24H14DDR_CSN5PA16D6PC18H15DDR_WEN6PA17D7PC13H16DDR_DQM1N7PB18D8PC6H17DDR_CASN8PD6D9NWR1/NBS1H18DDR_NCLKN9PD16D10NANDOEJ1PE19N10NTRSTD11DQM1J2PE16N11PB9D12D14J3PE14N12PB24D13D9J4PE15N13PB28D14D5J5PE12N14DDR_D13D15D1J6PE17N15DDR_D8D16VDDIOM1J7PE18N16DDR_D9D17A11J8PE20N17DDR_D11D18A10J9GNDCOREN18DDR_D12E1PD21J10GNDCOREP1PA11E2TSADVREFJ11GNDIOPP2PA13E3VDDANAJ12GNDIOMP3PA19E4JTAGSELJ13GNDIOMP4PA21E5TSTJ14DDR_A12P5PA23E6PC23J15DDR_A13P6PB12E7PC16J16DDR_CKEP7PB19E8PC8J17DDR_RASP8PD8E9PC1J18DDR_CLKP9PD286438BS–ATARM–13-Aug-09
AT91SAM9G45
PinSignal NameU4PB3U5PB7U6PB17U7PD7U8PD10U9PD14U10TCKU11VDDOSCU12GNDOSCU13PB10U14PB26U15HHSDPB/DHSDPU16HHSDMB/DHSDMU17GNDUTMIU18VDDUTMICV1PA31V2PB1V3PB2V4PB5V5PB15V6PD3V7PD5V8PD12V9PD17V10TDOV11XOUTV12XINV13VDDPLLUTMIV14VDDIOP2V15HFSDPB/DFSDPV16HFSDMB/DFSDMV17VDDUTMIIV18VBG13
5.Power Considerations
5.1
Power Supplies
The AT91SAM9G45 has several types of power supply pins:
•VDDCORE pins: Power the core, including the processor, the embedded memories and the peripherals; voltage ranges from 0.9V to 1.1V, 1.0V nominal.
•VDDIOM0 pins: Power the DDR2/LPDDR I/O lines; voltage ranges between 1.65V and 1.95V (1.8V typical).
•VDDIOM1 pins: Power the External Bus Interface 1 I/O lines; voltage ranges between 1.65V and 1.95V (1.8V typical) or between 3.0V and 3.6V (3.3V nominal).
•VDDIOP0, VDDIOP1, VDDIOP2 pins: Power the Peripherals I/O lines; voltage ranges from 1.65V to 3.6V.
•VDDBU pin: Powers the Slow Clock oscillator, the internal RC oscillator and a part of the System Controller; voltage ranges from 1.8V to 3.6V.
•VDDPLLUTMI Powers the PLLUTMI cell; voltage range from 0.9V to 1.1V.
•VDDUTMIC pin: Powers the USB device and host UTMI+ core; voltage range from 0.9V to 1.1V, 1.0V nominal.
•VDDUTMII pin: Powers the USB device and host UTMI+ interface; voltage range from 3.0V to 3.6V, 3.3V nominal.
•VDDPLLA pin: Powers the PLLA cell; voltage ranges from 0.9V to 1.1V.
•VDDOSC pin: Powers the Main Oscillator cells; voltage ranges from 1.65V to 3.6V
•VDDANA pin: Powers the Analog to Digital Converter; voltage ranges from 3.0V to 3.6V, 3.3V nominal.
Ground pins GND are common to VDDCORE, VDDIOM0, VDDIOM1, VDDIOP0, VDDIOP1 andVDDIOP2 power supplies. Separated ground pins are provided for VDDUTMIC, VDDUTMII,VDDBU, VDDOSC, VDDPLLA, VDDPLLUTMI and VDDANA. These ground pins are respec-tively GNDUTMIC, GNDUTMII, GNDBU, GNDOSC, GNDPLLA, GNDPLLUTMI and GNDANA.
14
AT91SAM9G45
6438BS–ATARM–13-Aug-09
AT91SAM9G45
6.Processor and Architecture
6.1
ARM926EJ-S Processor
•RISC Processor Based on ARM v5TEJ Architecture with Jazelle technology for Java acceleration•Two Instruction Sets
–ARM High-performance 32-bit Instruction Set–Thumb High Code Density 16-bit Instruction Set•DSP Instruction Extensions•5-Stage Pipeline Architecture:
–Instruction Fetch (F)–Instruction Decode (D)–Execute (E)–Data Memory (M)–Register Write (W)
•32-KByte Data Cache, 32-KByte Instruction Cache–Virtually-addressed 4-way Associative Cache–Eight words per line
–Write-through and Write-back Operation–Pseudo-random or Round-robin Replacement•Write Buffer
–Main Write Buffer with 16-word Data Buffer and 4-address Buffer
–DCache Write-back Buffer with 8-word Entries and a Single Address Entry–Software Control Drain
•Standard ARM v4 and v5 Memory Management Unit (MMU)
–Access Permission for Sections
–Access Permission for large pages and small pages can be specified separately for each quarter of the page –16 embedded domains•Bus Interface Unit (BIU)
–Arbitrates and Schedules AHB Requests
–Separate Masters for both instruction and data access providing complete Matrix system flexibility
–Separate Address and Data Buses for both the 32-bit instruction interface and the 32-bit data interface
–On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit (Words)•TCM Interface
6438BS–ATARM–13-Aug-09
15
6.2Bus Matrix
•11-layer Matrix, handling requests from 11 masters•Programmable Arbitration strategy
–Fixed-priority Arbitration
–Round-Robin Arbitration, either with no default master, last accessed default master or fixed default master•Burst Management
–Breaking with Slot Cycle Limit Support–Undefined Burst Length Support•One Address Decoder provided per Master
–Three different slaves may be assigned to each decoded memory area: one for internal ROM boot, one for internal flash boot, one after remap•Boot Mode Select
–Non-volatile Boot Memory can be internal ROM or external memory on EBI_NCS0–Selection is made by General purpose NVM bit sampled at reset•Remap Command
–Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory (ROM or External Flash)
–Allows Handling of Dynamic Exception Vectors
6.2.1Matrix Masters
The Bus Matrix of the AT91SAM9G45 manages Masters, thus each master can perform anaccess concurrently with others, depending on whether the slave it accesses is available.Each Master has its own decoder, which can be defined specifically for each master. In order tosimplify the addressing, all the masters have the same decodings.Table 6-1.
Master 0Master 1Master 2Master 3Master 4Master 5Master 6Master 7Master 8Master 9Master 10
List of Bus Matrix Masters
ARM926™ InstructionARM926 Data
Peripheral DMA Controller (PDC)USB HOST OHCI DMA DMA
ISI Controller DMALCD DMA
Ethernet MAC DMA
USB Device High Speed DMA USB Host High Speed EHCI DMA
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6.2.2
Matrix Slaves
Each Slave has its own arbiter, thus allowing a different arbitration per Slave to be programmed. Table 6-2.
Slave 0
List of Bus Matrix Slaves
Internal SRAM Internal ROMUSB OHCI
Slave 1USB EHCI
UDP High Speed RAMLCD User Interface
Slave 2Slave 3Slave 4Slave 5Slave 6Slave 7
DDR Port 0
DDR Port 1DDR Port 2DDR Port 3
External Bus InterfaceInternal Peripherals
6.2.3
Masters to Slaves Access
All the Masters can normally access all the Slaves. However, some paths do not make sense,such as allowing access from the Ethernet MAC to the internal peripherals. Thus, these pathsare forbidden or simply not wired, and shown “-” in the following tables.
Table 6-3.AT91SAM9G45 Masters to Slaves Access
Master
0ARM926 Instr.
1ARM926 DataXXXXXX-X--XX
PDCXX------XXXX2
3USB Host OHCIX-------XXX-4&5
6ISI
DMAX-------XXXX
DMAX-------XXX-7LCDDMA---------XX-8Ethernet MAC
X-------XXX-9USB Device HSXX------XXX-10USB Host EHCIX-------XXX-
Slave
0
InternalSRAM0Internal ROMUHPOHCIUHPEHCILCDUserInt.
1234567
UDPHSRAMDDRPort0DDRPort1DDR Port 2DDRPort3
EBI Internal Periph.
XXXXXXX---XX
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Table 6-4 summarizes the Slave Memory Mapping for each connected Master, depending onthe Remap status (RCBx bit in Bus Matrix Master Remap Control Register MATRIX_MRCR) andthe BMS state at reset.Table 6-4.
Internal Memory Mapping
Master
SlaveBase Address0x0000 0000
RCBx = 0
RCBx = 1Internal SRAM
BMS = 1
Internal ROM
BMS = 0
EBI NCS0
6.3Peripheral DMA Controller (PDC)
•Acting as one AHB Bus Matrix Master •Allows data transfers from/to peripheral to/from any memory space without any intervention of the processor.
•Next Pointer support, prevents strong real-time constraints on buffer management.
The Peripheral DMA Controller handles transfer requests from the channel according to the fol-lowing priorities (Low to High priorities):Table 6-5.
DBGUUSART3USART2USART1USART0AC97SPI1SPI0SSC1SSC0TSDACDBGUUSART3USART2USART1USART0AC97SPI1SPI0SSC1SSC0
Peripheral DMA Controller
Channel T/RTransmitTransmitTransmitTransmitTransmitTransmitTransmitTransmitTransmitTransmitReceiveReceiveReceiveReceiveReceiveReceiveReceiveReceiveReceiveReceiveReceive
Instance name
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6.4
USB
The AT91SAM9G45 features USB communication ports as follows:•2 Ports USB Host full speed OHCI and High speed EHCI•1 Device High speed
USB Host Port A is directly connected to the first UTMI transceiver.
The Host Port B is multiplexed with the USB device High speed and connected to the secondUTMI port. The selection between Host Port B and USB device high speed is controlled by a thebit UDPHS enable bit located in the UDPHS_CTRL control register.Figure 6-1.
USB Selection
HS TransceiverHS Transceiver
PAHS EHCIFS OHCIDMAEN_UDPHS0PBHSUSB DMA16.5DMA Controller
•TwoMasters•Embeds 8 channels
•64 bytes/FIFO for Channel Buffering
•Linked List support with Status Write Back operation at End of Transfer•Word, HalfWord, Byte transfer support.•memory to memory transfer•Peripheral to memory•Memory to peripheral
The DMA controller can handle the transfer between peripherals and memory and so receivesthe triggers from the peripherals below. The hardware interface numbers are also given below inTable Table 6-6.
DMA Channel Definition
T/RTX/RX
DMA Channel HW interface Number 0
Instance NameMCI0
SPI0 TX 1SPI0SPI1SPI1SSC0
RXTXRXTX
2345
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Table 6-6.DMA Channel Definition
T/R
DMA Channel HW interface Number 67891013
Instance Name
SSC0 RXSSC1SSC1AC97AC97MCI1
TXRXTXRXTX/RX
6.6Debug and Test Features
•ARM926 Real-time In-circuit Emulator
–Two real-time Watchpoint Units
–Two Independent Registers: Debug Control Register and Debug Status Register
–Test Access Port Accessible through JTAG Protocol–Debug Communications Channel•Debug Unit
–Two-pinUART
–Debug Communication Channel Interrupt Handling–Chip ID Register
•IEEE1149.1 JTAG Boundary-scan on All Digital Pins.
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7.Memories
Figure 7-1.
AT91SAM9G45 Memory Mapping
0x00000000Address Memory Space0x00000000Internal Memories0xFFFF0000System ControllerInternal MemoriesBoot Memory0x00100000ITCM0xFFFFE400Reserved0x100000000x00200000EBI Chip Select 0DTCM0xFFFFE600DDRSDRC10x00300000SRAM0xFFFFE800DDRSDRC00x200000000x00400000EBI Chip Select 1ROM0xFFFFEA00SMCDDR2-LPDDR-SDRAM0x00500000LCDC0xFFFFEC00MATRIX0x300000000x006000002321EBI Chip Select 2UDPHS (DMA)0xFFFFEE00DMAC0x00700000UHP OHCI0xFFFFF000DBGU0x400000000x008000000;31EBI Chip Select 3UHP EHCI0xFFFFF200AIC2NANDFlash0x00900000Reserved0xFFFFF400PIOA0x500000000x00A000003EBI Chip Select 4Undefined (Abort)0xFFFFF600PIOBCompact Flash Slot 00x0FFFFFFF0xFFFFF800PIOC40x600000000xF0000000Internal PeripheralsPIOD+5Reserved0xFFFFFA00EBI Chip Select 5PIOECompact Flash Slot 10xFFF78000+5UDPHS0xFFFFFC000x700000000xFFF7C000PMCTC0270xFFFFFD00SYSCDDR2-LPDDRTC0+0x40RSTCTC0+18+0x10SYSC1TC10x80000000Chip Select+0x80SHDWCTC0+18+0x20SYSC1Undefined (Abort)TC20xFFF80000+0x30RTTSYSC1HSMCI00xF00000000xFFF8400011+0x40PITSYSC1Internal PeripheralsTWI00xFFF8800012+0x50WDTSYSC1TWI10xFFFFFFFF0xFFF8C00013+0x60SCKCRSYSC1USART00xFFF900007+0x70GPBR1USART1SYSCoffsetReservedblock0xFFF940008USART20xFFFFFDB0peripheralRTC(+ : wired-or)ID0xFFF980009USART30xFFFFFDC0Reserved0xFFF9C00010SSC00xFFFFFFFF0xFFFA000016SSC10xFFFA400017SPI00xFFFA800014SPI10xFFFAC00015AC97C0xFFFB000024TSADCC0xFFFB400020ISI0xFFFB800026PWM0xFFFBC00019EMAC0xFFFC000025Reserved0xFFFC4000Reserved0xFFFC8000Reserved0xFFFCC000TRNG0xFFFD00006HSMCI10xFFFD4000TC129TC3+0x40TC1TC4+0x80TC1TC50xFFFD8000Reserved0xFFFFC000System controller0xFFFFFFFF6438BS–ATARM–13-Aug-09
21
7.1Memory Mapping
A first level of address decoding is performed by the AHB Bus Matrix, i.e., the implementation ofthe Advanced High performance Bus (AHB) for its Master and Slave interfaces with additionalfeatures.
Decoding breaks up the 4 Gbytes of address space into 16 banks of 256 Mbytes. The banks 1 to6 are directed to the EBI that associates these banks to the external chip selects NCS0 toNCS5.
The bank 7 is directed to the DDRLPDDR that associates this bank to DDR_NCS chip selectand so dedicated to the 4-port DDR2/ LPDDR controller.
The bank 0 is reserved for the addressing of the internal memories, and a second level ofdecoding provides 1 Mbyte of internal memory area. The bank 15 is reserved for the peripheralsand provides access to the Advanced Peripheral Bus (APB).
Other areas are unused and performing an access within them provides an abort to the masterrequesting such an access.
7.2
7.2.1
Embedded Memories
Internal SRAM
The AT91SAM9G45 product embeds a total of 64 Kbytes high-speed SRAM split in 4 blocks of16 KBytes connected to one slave of the matrix. After reset and until the Remap Command isperformed, the four SRAM blocks are contiguous and only accessible at address 0x00300000.After Remap, the SRAM also becomes available at address 0x0.Figure 7-2.
Internal SRAM Reset
RAMRAMRemap64K64K 0x003000000x00000000The AT91SAM9G45 device embeds two memory features. The processor Tightly Coupled Mem-ory Interface (TCM) that allows the processor to access the memory up to processor speed(PCK) and the interface on the AHB side allowing masters to access the memory at AHB speed(MCK).
A wait state is necessary to access the TCM at 400 MHz. Setting the bit NWS_TCM in the busMatrix TCM Configuration Register of the matrix inserts a wait state on the ITCM and DTCMaccesses.
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7.2.2
TCM Interface
On the processor side, this Internal SRAM can be allocated to two areas.
•Internal SRAM A is the ARM926EJ-S Instruction TCM. The user can map this SRAM block anywhere in the ARM926 instruction memory space using CP15 instructions and the TCR configuration register located in the Chip Configuration User Interface. This SRAM block is also accessible by the ARM926 Masters and by the AHB Masters through the AHB bus •Internal SRAM B is the ARM926EJ-S Data TCM. The user can map this SRAM block
anywhere in the ARM926 data memory space using CP15 instructions. This SRAM block is also accessible by the ARM926 Data Master and by the AHB Masters through the AHB bus.•Internal SRAM C is only accessible by all the AHB Masters. After reset and until the Remap Command is performed, this SRAM block is accessible through the AHB bus at address 0x0030 0000 by all the AHB Masters. After Remap, this SRAM block also becomes
accessible through the AHB bus at address 0x0 by the ARM926 Instruction and the ARM926 Data Masters.Figure 7-3.
RAM Mapping
Processor Side(through TCM interface)RAMAHB Side(Multi-slave mode)16KDTCM @ 0x00200000(32K)16K0x0030000016K16KITCM @ 0x00100000(32K)0Within the 64 Kbyte SRAM size available, the amount of memory assigned to each block is soft-ware programmable according to Table 7-1.
Table 7-1.ITCM and DTCM Memory Configuration
SRAM B DTCM size (KBytes)
06432
SRAMC AHB (KBytes)
6400
SRAM A ITCM size (KBytes)
0032
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7.2.3Internal ROM
The AT91SAM9G45 embeds an Internal ROM, which contains the bootrom and SAM-BAprogram.
At any time, the ROM is mapped at address 0x0050 0000. It is also accessible at address 0x0(BMS =1) after the reset and before the Remap Command.
7.2.4
Boot Strategies
The system always boots at address 0x0. To ensure maximum boot possibilities the memorylayout can be changed with two parameters.
REMAP allows the user to layout the internal SRAM bank to 0x0 to ease the development. Thisis done by software once the system has boot.
BMS allows the user to lay out to 0x0, when convenient, the ROM or an external memory. This isdone by a hardware way at reset.
Note: All the memory blocks can always be seen at their specified base addresses that are notconcerned by these parameters.
The AT91SAM9G45 Bus Matrix manages a boot memory that depends on the level on the pinBMS at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF isreserved to this effect.
If BMS is detected at 1, the boot memory is the embedded ROM.
If BMS is detected at 0, the boot memory is the memory connected on the Chip Select 0 of theExternal Bus Interface.
7.2.4.1
BMS = 1, boot on embedded ROM
The system boots on Boot Program.
•Boot on on-chip RC
•Enable the 32768 Hz oscillator•Auto baudrate detection
•Downloads and runs an application from external storage media into internal SRAM•Downloaded code size depends on embedded SRAM size•Automatic detection of valid application•Bootloader on a non-volatile memory
–SPI DataFlash/SerialFlash connected on NPCS0 of the SPI0–SDCard–NandFlash
–EEPROM connected on TWI0
•SAM-BA Boot in case no valid program is detected in external NVM, supporting
–Serial communication on a DBGU–USB Device HS Port
7.2.4.2BMS = 0, boot on external memory
•Boot on on-chip RC
•Boot with the default configuration for the Static Memory Controller, byte select mode, 16-bit data bus, Read/Write controlled by Chip Select, allows boot on 16-bit non-volatile memory.
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For optimization purpose, nothing else is done. To speed up the boot sequence user pro-grammed software should perform a complete configuration:•Enable the 32768 Hz oscillator if best accuracy needed•Program the PMC (main oscillator enable or bypass mode)•Program and Start the PLL
•Reprogram the SMC setup, cycle, hold, mode timings registers for EBI CS0 to adapt them to the new clock
•Switch the main clock to the new value
7.3External Memories
The AT91SAM9G45 features an External Bus Interface to interface to a wide range of externalmemories and to any parallel peripheral.
7.3.1DDR2/LPDDR Interface
•Integrates 4-ports DDR2/LPDDR controller that support:
–16-bit DDR2 memories–16-bit LPDDR memories
7.3.2External Bus Interface
•Integrates Three External Memory Controllers:
–Static Memory Controller–DDR2/SDRAM Controller–SLC Nand Flash ECC Controller
•Additional logic for NAND Flash and CompactFlashTM•Optional Full 32-bit External Data Bus
•Up to 26-bit Address Bus (up to 64MBytes linear per chip select)•Up to 6 chip selects, Configurable Assignment:
–Static Memory Controller on NCS0
–DDR2/SDRAM Controller (SDCS) or Static Memory Controller on NCS1–Static Memory Controller on NCS2
–Static Memory Controller on NCS3, Optional NAND Flash support
–Static Memory Controller on NCS4 - NCS5, Optional CompactFlashM support
7.3.3
DDR2/LPDDR Controller
Four AHB Interfaces, Management of All Accesses Maximizes Memory Bandwidth and Mini-mizes Transaction Latency.
•Supports AHB Transfers:
–Word, Half Word, Byte Access.•Supports DDR-SDRAM 2, LPDDR•Numerous Configurations Supported
–2K, 4K, 8K, 16K Row Address Memory Parts–DDR2 with Four Internal Banks–DDR2/LPDDR with 16-bit Data Path
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–One Chip Select for DDR2/LPDDR Device (256 Mbytes Address Space)•Programming Facilities
–Multibank Ping-pong Access (Up to 4 Banks Opened at Same Time = Reduces Average Latency of Transactions)–Timing Parameters Specified by Software
–Automatic Refresh Operation, Refresh Rate is Programmable–Automatic Update of DS, TCR and PASR Parameters•Energy-saving Capabilities
–Self-refresh, Power-down and Deep Power Modes Supported•Power-up Initialization by Software•CAS Latency of 2, 3 Supported•Reset function supported (DDR2)•Auto Precharge Command Not Used•On Die Termination not supported•OCD mode not supported
7.3.4
Static Memory Controller
•8-, 16- or 32-bit Data Bus•Multiple Access Modes supported
–Byte Write or Byte Select Lines
–Asynchronous read in Page Mode supported (4- up to 32-byte page size)•Multiple device adaptability
–Control signals programmable setup, pulse and hold time for each Memory Bank•Multiple Wait State Management
–Programmable Wait State Generation–External Wait Request–Programmable Data Float Time•Slow Clock mode supported
7.3.5
DDR2/SDR Controller
•Supports DDR2/LPDDR2, SDR-SDRAM and LPSDR•Numerous Configurations Supported
–2K, 4K, 8K, 16K Row Address Memory Parts–SDRAM with Four Internal Banks
–SDR-SDRAM with 16- or 32- bit Data Path–DDR2/LPDDR with 16- bit Data Path
–One Chip Select for SDRAM Device (256 Mbyte Address Space)•Programming Facilities
–Multibank Ping-pong Access (Up to 4 Banks Opened at Same Time = Reduces Average Latency of Transactions)–Timing Parameters Specified by Software
–Automatic Refresh Operation, Refresh Rate is Programmable
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–Automatic Update of DS, TCR and PASR Parameters (LPSDR)•Energy-saving Capabilities
–Self-refresh, Power-down and Deep Power Modes Supported•SDRAM Power-up Initialization by Software•CAS Latency of 2, 3 Supported•Auto Precharge Command Not Used
•SDR-SDRAM with 16-bit Datapath and Eight Columns Not Supported
–Clock Frequency Change in Precharge Power-down Mode Not Supported
7.3.6
NAND Flash Error Corrected Code Controller
•Tracking the accesses to a NAND Flash device by triggering on the corresponding chip select•Single bit error correction and 2-bit Random detection.•Automatic Hamming Code Calculation while writing
–ECC value available in a register
•Automatic Hamming Code Calculation while reading
–Error Report, including error flag, correctable error flag and word address being detected erroneous
–Support 8- or 16-bit NAND Flash devices with 512-, 1024-, 2048- or 4096-bytes pages
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8.System Controller
The System Controller is a set of peripherals that allows handling of key elements of the system,such as power, resets, clocks, time, interrupts, watchdog, etc.
The System Controller User Interface also embeds the registers that configure the Matrix and aset of registers for the chip configuration. The chip configuration registers configure the EBI chipselect assignment and voltage range for external memories.
8.1System Controller Mapping
The System Controller’s peripherals are all mapped within the highest 16 KBytes of addressspace, between addresses 0xFFFF E800 and 0xFFFF FFFF.
However, all the registers of the System Controller are mapped on the top of the address space.All the registers of the System Controller can be addressed from a single pointer by using thestandard ARM instruction set, as the Load/Store instruction have an indexing mode of ±4 KB.Figure 8-1 on page 29 shows the System Controller block diagram.
Figure 7-1 on page 21 shows the mapping of the User Interfaces of the System Controllerperipherals.
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8.2
System Controller Block Diagram
Figure 8-1.
AT91SAM9G45 System Controller Block Diagram
System ControllerVDDCORE Poweredirq0-irq2nirqfiqAdvanced nfiqperiph_irq[2..24]Interrupt Controllerpit_irqrtt_irqintwdt_irqdbgu_irqpor_ntrstntrstARM926EJ-Spmc_irqrstc_irqperiph_nresetMCKDebug dbgu_irqproc_nresetdbgu_rxdUnitdbgu_txdPCKdebugdebugMCKPeriodic Interval pit_irqperiph_nresetTimerjtag_nresetBoundary Scan debugSLCKWatchdog wdt_irqTAP Controllerproc_nresetidleTimerMCKwdt_faultWDRPROCperiph_nresetBus MatrixNRSTrstc_irqVDDCOREpor_ntrstperiph_nresetPORjtag_nresetReset proc_nresetControllerbackup_nresetVDDBUVDDBUVDDBU PoweredPORUPLLCKSLCKUHP48MSLCKReal-Time rtc_irqbackup_nresetClockrtc_alarmUHP12MUSB High SpeedReal-Time rtt_irqperiph_nresetHost PortSLCKbackup_nresetTimerrtt_alarmperiph_irq[25]SLCKSHDNWKUPShut-DownUPLLCKbackup_nresetControllerRC rtt0_alarmUSB High SpeedOSC4 General-purposeperiph_nresetDevice PortXIN32SLOWBackup Registersperiph_irq[24]XOUT32CLOCKOSCSCKCRSLCKperiph_clk[2..30]pck[0-1]XINint12MHzMAINCKUHP48MUHP12MXOUTMAIN OSCPower PCKMCKUPLLUPLLCKManagementControllerDDR sysclkpmc_irqPLLAPLLACKidleperiph_clk[6..30]periph_nresetperiph_nresetperiph_nresetperiph_irq[2..6]Embeddedperiph_clk[2..6]irqPeripheralsdbgu_rxdPIO fiqPA0-PA31periph_irq[6..30]Controllersdbgu_txdPB0-PB31inPC0-PC31outPD0-PD31enablePE0-PE316438BS–ATARM–13-Aug-09
29
8.3Reset Controller
The Reset Controller is based on two Power-on-Reset cells, one on VDDBU and one onVDDCORE.
The Reset Controller is capable to return to the software the source of the last reset, either ageneral reset (VDDBU rising), a wake-up reset (VDDCORE rising), a software reset, a userreset or a watchdog reset.
The Reset Controller controls the internal resets of the system and the NRST pin output. It iscapable to shape a reset signal for the external devices, simplifying to a minimum connection ofa push-button on the NRST pin to implement a manual reset.
The configuration of the Reset Controller is saved as supplied on VDDBU.
8.4Shut Down Controller
The Shut Down Controller is supplied on VDDBU and allows a software-controllable shut downof the system through the pin SHDN. An input change of the WKUP pin or an alarm releases theSHDN pin, and thus wakes up the system power supply.
8.5Clock Generator
The Clock Generator is made up of:
•One Low Power 32768 Hz Slow Clock Oscillator with bypass mode•One Low-Power RC oscillator
•One 12 MHz Main Oscillator, which can be bypassed
•One 400 to 800 MHz programmable PLLA, capable to provide the clock MCK to the processor and to the peripherals. This PLL has an input divider to offer a wider range of
output frequencies from the 12 MHz input, the only limitation being the lowest input frequency shall be higher or equal to 2 MHz.
The USB Device and Host HS Clocks are provided by a the dedicated UTMI PLL (UPLL)embedded in the UTMI macro.
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Figure 8-2.
Clock Generator Block Diagram
Clock GeneratorRCENOn Chip RC OSCXIN32XOUT32Slow ClockOscillatorSlow Clock SLCKOSCSELOSC32ENOSC32BYPXINXOUT12M Main OscillatorMain ClockMAINCKUPLLUPLLCKPLLA and DividerStatusControlPLLA ClockPLLACKPower Management Controller8.6Slow Clock Selection
The AT91SAM9G45 slow clock can be generated either by an external 32768Hz crystal or theon-chip RC oscillator. The 32768 Hz crystal oscillator can be bypassed, by setting the bitOSC32BYP, to accept an external slow clock on XIN32.
The internal RC oscillator and the 32768 Hz oscillator can be enabled by setting to 1 respec-tively RCEN bit and OSC32EN bit in the system controller user interface. OSCSEL commandselects the slow clock source.
RCEN, OSC32EN,OSCSEL and OSC32BYP bits are located in the slow clock control register(SCKCR) located at address 0xFFFFFD50 in the backup part of the system controller and so arepreserved while VDDBU is present.
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Figure 8-3.Slow Clock
Clock GeneratorRCENOn Chip RC OSCSlow Clock SLCKXIN32XOUT32Slow ClockOscillatorOSCSELOSC32ENOSC32BYPAfter a VDDBU power on reset, the default configuration is RCEN = 1, OSC32EN = 0 and OSC-SEL = 0 allowing the system to start on the internal RC oscillator.
The programmer controls by software the slow clock switching and so must take precautionsduring the switching phase.
8.6.1
Switch from Internal RC Oscillator to the 32768 Hz Crystal
To switch from internal RC oscillator to the 32768 Hz crystal, the programmer must execute thefollowing sequence:
•Switch the master clock to a source different from slow clock (PLLA or PLLB or Main Oscillator) through the Power Management Controller.•Enable the 32768 Hz oscillator by setting the bit OSCEN to 1.•Wait 32768 Hz startup time for clock stabilization (software loop).•Switch from internal RC to 32768 Hz by setting the bit OSCSEL to 1.•Wait 5 slow clock cycles for internal resynchronization.•Disable the RC oscillator by setting the bit RCEN to 0.
8.6.2
Bypass the 32768 Hz Oscillator
The following step must be added to bypass the 32768 Hz Oscillator.
•An external clock must be connected on XIN32.•Enable the bypass path OSC32BYP bit set to 1.
•Disable the 32768 Hz oscillator by setting the bit OSC32EN to 0.
8.6.3
Switch from 32768 Hz Crystal to the Internal RC Oscillator
The same procedure must be followed to switch from 32768 Hz crystal to the internal RCoscillator.
•Switch the master clock to a source different from slow clock (PLLA or PLLB or Main Oscillator).
•Enable the internal RC oscillator by setting the bit RCEN to 1.•Wait internal RC Startup Time for clock stabilization (software loop).
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•Switch from 32768 Hz oscillator to internal RC oscilllator by setting the bit OSCSEL to 0.•Wait 5 slow clock cycles for internal resynchronization.
•Disable the 32768Hz oscillator by setting the bit OSC32EN to 0.
8.7Power Management Controller
The Power Management Controller provides all the clock signals to the system.PMC input clocks:
•UPLLCK: From UTMI PLL•PLLACK From PLLA
•SLCK: slow clock from OSC32K or internal RC OSC•MAINCK: from 12 MHz external oscillatorPMC output clocks•Processor Clock PCK
•Master Clock MCK, in particular to the Matrix and the memory interfaces. The divider can be 1,2,3 or 4
•DDR system clock equal to 2xMCK
Note:
DDR system clock is not available when Master Clock (MCK) equals Processor Clock (PCK).
•USB Host EHCI High speed clock (UPLLCK)•USB OHCI clocks (UHP48M and UHP12M)
•Independent peripheral clocks, typically at the frequency of MCK•Two programmable clock outputs: PCK0 and PCK1
This allows the software control of five flexible operating modes:
•Normal Mode, processor and peripherals running at a programmable frequency•Idle Mode, processor stopped waiting for an interrupt
•Slow Clock Mode, processor and peripherals running at low frequency
•Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency, processor stopped waiting for an interrupt
•Backup Mode, Main Power Supplies off, VDDBU powered by a battery
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Figure 8-4.
PLLACKAT91SAM9G45 Power Management Controller Block Diagram
USBSUSBDIV+1/4UHP48MUHP12MUSB OHCIUSB EHCI/1,/2UPLLCKProcessorClock ControllerDividerX /1 /1.5 /2PCKintSysClk DDRMCK PeripheralsClock ControllerON/OFFperiph_clk[..]MAINCKSLCKPrescaler/1,/2,/4,.../64/1 /2 /3 /4Master Clock Controller SLCKMAINCKUPLLCKPrescaler/1,/2,/4,...,/64ON/OFFpck[..]Programmable Clock Controller 8.7.1
Main Application Modes
The Power Management Controller provides 3 main application modes.Normal Mode
•PLLA and UPLL are running respectively at 400 MHz and 480 MHz•USB Device High Speed and Host EHCI High Speed operations are allowed•Full Speed OHCI input clock is UPLLCK, USBDIV is 9 (division by 10)•System Input clock is PLLACK, PCK is 400 MHz•MDIV is ‘11’, MCK is 133 MHz•DDR2 can be used at up to 133 MHz
8.7.1.1
8.7.1.2USB HS and LP-DDR Mode
•Only UPLL is running at 480 MHz, PLLA power consumption is saved•USB Device High Speed and Host EHCI High Speed operations are allowed•Full Speed OHCI input clock is UPLLCK, USBDIV is 9 (division by 10)•System Input clock is UPLLCK, Prescaler is 2, PCK is 240 MHz•MDIV is ‘01’, MCK is 120 MHz
•Only LP-DDR can be used at up to 120 MHz
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8.7.1.3
No UDP HS, UHP FS and DDR2 Mode
•Only PLLA is running at 384 MHz, UPLL power consumption is saved
•USB Device High Speed and Host EHCI High Speed operations are NOT allowed•Full Speed OHCI input clock is PLLACK, USBDIV is 7 (division by 8)•System Input clock is PLLACK, PCK is 384 MHz•MDIV is ‘11’, MCK is 128 MHz•DDR2 can be used at up to 128 MHz
8.8Periodic Interval Timer
•Includes a 20-bit Periodic Counter, with less than 1µs accuracy•Includes a 12-bit Interval Overlay Counter
•Real Time OS or Linux/WinCE compliant tick generator
8.9Watchdog Timer
•16-bit key-protected only-once-Programmable Counter
•Windowed, prevents the processor to be in a dead-lock on the watchdog access
8.10Real-Time Timer
•Real-Time Timer, allowing backup of time with different accuracies
–32-bit Free-running back-up Counter
–Integrates a 16-bit programmable prescaler running on slow clock
–Alarm Register capable to generate a wake-up of the system through the Shut Down Controller
8.11Real Time Clock
•Low power consumption •Full asynchronous design•Two hundred year calendar•Programmable Periodic Interrupt •Alarm and update parallel load
•Control of alarm and update Time/Calendar Data In
8.12General-Purpose Backup Registers
•Four 32-bit backup general-purpose registers
8.13Advanced Interrupt Controller
•Controls the interrupt lines (nIRQ and nFIQ) of the ARM Processor•Thirty-two individually maskable and vectored interrupt sources
–Source 0 is reserved for the Fast Interrupt Input (FIQ)
–Source 1 is reserved for system peripherals (PIT, RTT, PMC, DBGU, etc.)–Programmable Edge-triggered or Level-sensitive Internal Sources
–Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive
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6438BS–ATARM–13-Aug-09
•One External Sources plus the Fast Interrupt signal•8-level Priority Controller
–Drives the Normal Interrupt of the processor–Handles priority of the interrupt sources 1 to 31
–Higher priority interrupts can be served during service of lower priority interrupt•Vectoring
–Optimizes Interrupt Service Routine Branch and Execution–One 32-bit Vector Register per interrupt source
–Interrupt Vector Register reads the corresponding current Interrupt Vector•ProtectMode
–Easy debugging by preventing automatic operations when protect modes are enabled•FastForcing
–Permits redirecting any normal interrupt source on the Fast Interrupt of the
processor
8.14Debug Unit
•Composed of two functions
–Two-pinUART
–Debug Communication Channel (DCC) support
•Two-pinUART
–Implemented features are 100% compatible with the standard Atmel USART–Independent receiver and transmitter with a common programmable Baud Rate Generator
–Even, Odd, Mark or Space Parity Generation–Parity, Framing and Overrun Error Detection
–Automatic Echo, Local Loopback and Remote Loopback Channel Modes–Support for two PDC channels with connection to receiver and transmitter•Debug Communication Channel Support
–Offers visibility of and interrupt trigger from COMMRX and COMMTX signals from the ARM Processor’s ICE Interface
8.15Chip Identification
The AT91SAM9G45 Chip ID is defined in the Debug Unit Chip ID Register and Debug Unit ChipID Extension Register.•Chip ID: 0x819B05A2•Ext ID: 0x00000004•JTAG ID: 05B2_703F•ARM926 TAP ID: 0x0792603F
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6438BS–ATARM–13-Aug-09
AT91SAM9G45
8.16
PIO Controllers
•5 PIO Controllers, PIOA, PIOB, PIOC, PIOD and PIOE, controlling a maximum of 160 I/O Lines
•Each PIO Controller controls up to 32 programmable I/O Lines
–PIOA has 32 I/O Lines–PIOB has 32 I/O Lines–PIOC has 32 I/O Lines–PIOD has 32 I/O Lines–PIOE has 32 I/O Lines
•Fully programmable through Set/Clear Registers•Multiplexing of two peripheral functions per I/O Line
•For each I/O Line (whether assigned to a peripheral or used as general purpose I/O)
–Input change interrupt–Glitch filter
–Multi-drive option enables driving in open drain–Programmable pull up on each I/O line
–Pin data status register, supplies visibility of the level on the pin at any time•Synchronous output, provides Set and Clear of several I/O lines in a single write
6438BS–ATARM–13-Aug-09
37
9.Peripherals
9.1
Peripheral Mapping
As shown in Figure 7-1, the Peripherals are mapped in the upper 256 Mbytes of the addressspace between the addresses 0xFFF7 8000 and 0xFFFC FFFF. Each User Peripheral is allocated 16K bytes of address space.
9.2Peripheral Identifiers
Table 9-1 defines the Peripheral Identifiers of the AT91SAM9G45. A peripheral identifier isrequired for the control of the peripheral interrupt with the Advanced Interrupt Controller and forthe control of the peripheral clock with the Power Management Controller.
Table 9-1.0123456789101112131415161718192021222324252627293031AT91SAM9G45 Peripheral IdentifiersPeripheral MnemonicAICSYSCPIOAPIOBPIOCPIOD/PIOERNGUS0US1US2US3MCI0TWI0TWI1SPI0SPI1SSC0SSC1TC0..TC5 PWMCTSADCCDMAUHPHSLCDCAC97EMACISIUDPHSMCI1ReservedAICAdvanced Interrupt ControllerIRQPeripheral NameAdvanced Interrupt ControllerSystem Controller InterruptParallel I/O Controller A,Parallel I/O Controller BParallel I/O Controller CParallel I/O Controller D/ETrue Random Number Generator USART 0USART 1USART 2USART 3High Speed Multimedia Card Interface 0Two-Wire Interface 0Two-Wire Interface 1Serial Peripheral InterfaceSerial Peripheral InterfaceSynchronous Serial Controller 0Synchronous Serial Controller 1Timer Counter 0,1,2,3,4,5Pulse Width Modulation ControllerTouch Screen ADC ControllerDMA ControllerUSB Host High Speed LCD ControllerAC97 ControllerEthernet MACImage Sensor InterfaceUSB Device High Speed High Speed Multimedia Card Interface 1External InterruptFIQPeripheral ID38AT91SAM9G456438BS–ATARM–13-Aug-09AT91SAM9G45
9.3
9.3.1
Peripheral Interrupts and Clock Control
System Interrupt
The System Interrupt in Source 1 is the wired-OR of the interrupt signals coming from:
•the DDR2/LPDDR Controller•the Debug Unit
•the Periodic Interval Timer•the Real-Time Timer•the Real-Time Clock•the Watchdog Timer•the Reset Controller
•the Power Management Controller
The clock of these peripherals cannot be deactivated and Peripheral ID 1 can only be usedwithin the Advanced Interrupt Controller.
9.3.2
External Interrupts
All external interrupt signals, i.e., the Fast Interrupt signal FIQ or the Interrupt signal IRQ, use adedicated Peripheral ID. However, there is no clock control associated with these peripheral IDs.9.4Peripheral Signals Multiplexing on I/O Lines
The AT91SAM9G45 features 5 PIO controllers, PIOA, PIOB, PIOC, PIOD and PIOE, which mul-tiplexes the I/O lines of the peripheral set.
Each PIO Controller controls up to 32 lines. Each line can be assigned to one of two peripheralfunctions, A or B. The multiplexing tables in the following paragraphs define how the I/O lines ofthe peripherals A and B are multiplexed on the PIO Controllers. The two columns “Function” and“Comments” have been inserted in this table for the user’s own comments; they may be used totrack how pins are defined in an application.
Note that some peripheral function which are output only, might be duplicated within the bothtables.
The column “Reset State” indicates whether the PIO Line resets in I/O mode or in peripheralmode. If I/O is mentioned, the PIO Line resets in input with the pull-up enabled, so that thedevice is maintained in a static state as soon as the reset is released. As a result, the bit corre-sponding to the PIO Line in the register PIO_PSR (Peripheral Status Register) resets low.If a signal name is mentioned in the “Reset State” column, the PIO Line is assigned to this func-tion and the corresponding bit in PIO_PSR resets high. This is the case of pins controllingmemories, in particular the address lines, which require the pin to be driven as soon as the resetis released. Note that the pull-up resistor is also enabled in this case.
To amend EMC, programmable delay has been inserted on PIO lines able to run at high speed.
39
6438BS–ATARM–13-Aug-09
9.4.1Table 9-2.I/O LinePA0PA1PA2PA3PA4PA5PA6PA7PA8PA9PA10PA11PA12PA13PA14PA15PA16PA17PA18PA19PA20PA21PA22PA23PA24PA25PA26PA27PA28PA29PA30PA31PIO Controller A Multiplexing
Multiplexing on PIO Controller A (PIOA)Peripheral AMCI0_CKMCI0_CDAMCI0_DA0MCI0_DA1MCI0_DA2MCI0_DA3MCI0_DA4MCI0_DA5MCI0_DA6MCI0_DA7ETX0ETX1ERX0ERX1ETXENERXDVERXERETXCKEMDCEMDIOTWD0TWCK0MCI1_CDAMCI1_DA0MCI1_DA1MCI1_DA2MCI1_DA3MCI1_DA4MCI1_DA5MCI1_DA6MCI1_DA7MCI1_CKSCK3RTS3CTS3PWM3TIOB2ETXERERXCKECRSECOLPCK0Peripheral BTCLK3TIOA3TIOB3TCKL4TIOA4TIOB4ETX2ETX3ERX2ERX3Reset StateI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OPower SupplyVDDIOP0VDDIOP0VDDIOP0VDDIOP0VDDIOP0VDDIOP0VDDIOP0VDDIOP0VDDIOP0VDDIOP0VDDIOP0VDDIOP0VDDIOP0VDDIOP0VDDIOP0VDDIOP0VDDIOP0VDDIOP0VDDIOP0VDDIOP0VDDIOP0VDDIOP0VDDIOP0VDDIOP0VDDIOP0VDDIOP0VDDIOP0VDDIOP0VDDIOP0VDDIOP0VDDIOP0VDDIOP0FunctionComments40
AT91SAM9G45
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AT91SAM9G45
9.4.2Table 9-3.
I/O LinePB0PB1PB2PB3PB4PB5PB6PB7PB8PB9PB10PB11PB12PB13PB14PB15PB16PB17PB18PB19PB20PB21PB22PB23PB24PB25PB26PB27PB28PB29PB30PB31
PIO Controller B Multiplexing
Multiplexing on PIO Controller B (PIOB)
Peripheral ASPI0_MISOSPI0_MOSISPI0_SPCKSPI0_NPCS0
TXD1RXD1TXD2RXD2TXD3RXD3TWD1TWCK1DRXDDTXDSPI1_MISOSPI1_MOSISPI1_SPCKSPI1_NPCS0
RXD0TXD0ISI_D0ISI_D1ISI_D2ISI_D3ISI_D4ISI_D5ISI_D6ISI_D7ISI_PCKISI_VSYNCISI_HSYNCISI_MCK
PCK1CTS0SCK0RTS0SPI0_NPCS1SPI0_NPCS2
ISI_D8ISI_D9ISI_D10ISI_D11Peripheral B
Reset StateI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/O
Power SupplyVDDIOP0VDDIOP0VDDIOP0VDDIOP0VDDIOP0VDDIOP0VDDIOP0VDDIOP0VDDIOP2VDDIOP2VDDIOP2VDDIOP2VDDIOP0VDDIOP0VDDIOP0VDDIOP0VDDIOP0VDDIOP0VDDIOP0VDDIOP0VDDIOP2VDDIOP2VDDIOP2VDDIOP2VDDIOP2VDDIOP2VDDIOP2VDDIOP2VDDIOP2VDDIOP2VDDIOP2VDDIOP2
Function
Comments
41
6438BS–ATARM–13-Aug-09
9.4.3Table 9-4.
I/O LinePC0PC1PC2PC3PC4PC5PC6PC7PC8PC9PC10PC11PC12PC13PC14PC15PC16PC17PC18PC19PC20PC21PC22PC23PC24PC25PC26PC27PC28PC29PC30PC31
PIO Controller C Multiplexing
Multiplexing on PIO Controller C (PIOC)
Peripheral ADQM2DQM3A19A20A21/NANDALEA22/NANDCLE
A23A24CFCE1CFCE2NCS4/CFCS0NCS5/CFCS1A25/CFRNW
NCS2NCS3/NANDCS
NWAITD16D17D18D19D20D21D22D23D24D25D26D27D28D29D30D31
RTS2TCLK2CTS2Peripheral B
Reset StateDQM2DQM3A19A20A21A22A23A24I/OI/OI/OI/OA25I/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/O
Power SupplyVDDIOM1VDDIOM1VDDIOM1VDDIOM1VDDIOM1VDDIOM1VDDIOM1VDDIOM1VDDIOM1VDDIOM1VDDIOM1VDDIOM1VDDIOM1VDDIOM1VDDIOM1VDDIOM1VDDIOM1VDDIOM1VDDIOM1VDDIOM1VDDIOM1VDDIOM1VDDIOM1VDDIOM1VDDIOM1VDDIOM1VDDIOM1VDDIOM1VDDIOM1VDDIOM1VDDIOM1VDDIOM1
Function
Comments
42
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6438BS–ATARM–13-Aug-09
AT91SAM9G45
9.4.4Table 9-5.
I/O LinePD0PD1PD2PD3PD4PD5PD6PD7PD8PD9PD10PD11PD12PD13PD14PD15PD16PD17PD18PD19PD20PD21PD22PD23PD24PD25PD26PD27PD28PD29PD30PD31
PIO Controller D Multiplexing
Multiplexing on PIO Controller D (PIOD)
Peripheral A
TK0TF0TD0RD0RK0RF0AC97RXAC97TXAC97FSAC97CKTD1RD1TK1RK1TF1RF1RTS1CTS1SPI1_NPCS2SPI1_NPCS3
TIOA0TIOA1TIOA2TCLK0SPI0_NPCS1SPI0_NPCS2
PCK0PCK1TSADTRGTCLK1TIOB0TIOB1
PWM0PWM1PWM2SPI0_NPCS3SPI1_NPCS1
SCK1SCK2PWM1IRQFIQPCK0TIOA5TIOB5TCLK5Peripheral BPWM3
Reset StateI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/O
Power SupplyVDDIOP0VDDIOP0VDDIOP0VDDIOP0VDDIOP0VDDIOP0VDDIOP0VDDIOP0VDDIOP0VDDIOP0VDDIOP0VDDIOP0VDDIOP0VDDIOP0VDDIOP0VDDIOP0VDDIOP0VDDIOP0VDDIOP0VDDIOP0VDDANAVDDANAVDDANAVDDANAVDDANAVDDANAVDDANAVDDANAVDDIOP0VDDIOP0VDDIOP0VDDIOP0
TSAD0TSAD1TSAD2TSAD3GPAD4GPAD5GPAD6GPAD7
Function
Comments
43
6438BS–ATARM–13-Aug-09
9.4.5Table 9-6.
I/O LinePE0PE1PE2PE3PE4PE5PE6PE7PE8PE9PE10PE11PE12PE13PE14PE15PE16PE17PE18PE19PE20PE21PE22PE23PE24PE25PE26PE27PE28PE29PE30PE31
PIO Controller E Multiplexing
Multiplexing on PIO Controller E (PIOE)
Peripheral ALCDPWRLCDMODLCDCCLCDVSYNCLCDHSYNCLCDDOTCKLCDDENLCDD0LCDD1LCDD2LCDD3LCDD4LCDD5LCDD6LCDD7LCDD8LCDD9LCDD10LCDD11LCDD12LCDD13LCDD14LCDD15LCDD16LCDD17LCDD18LCDD19LCDD20LCDD21LCDD22LCDD23PWM2
PCK1LCDD2LCDD3LCDD4LCDD5LCDD6LCDD7LCDD10LCDD11LCDD12LCDD13LCDD14LCDD15LCDD18LCDD19LCDD20LCDD21LCDD22LCDD23Peripheral B
PCK0
Reset StateI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/O
Power SupplyVDDIOP1VDDIOP1VDDIOP1VDDIOP1VDDIOP1VDDIOP1VDDIOP1VDDIOP1VDDIOP1VDDIOP1VDDIOP1VDDIOP1VDDIOP1VDDIOP1VDDIOP1VDDIOP1VDDIOP1VDDIOP1VDDIOP1VDDIOP1VDDIOP1VDDIOP1VDDIOP1VDDIOP1VDDIOP1VDDIOP1VDDIOP1VDDIOP1VDDIOP1VDDIOP1VDDIOP1VDDIOP1
Function
Comments
44
AT91SAM9G45
6438BS–ATARM–13-Aug-09
AT91SAM9G45
10.Embedded Peripherals
10.1
Serial Peripheral Interface (SPI)
•Supports communication with serial external devices
–Four chip selects with external decoder support allow communication with up to 15 peripherals
–Serial memories, such as DataFlash and 3-wire EEPROMs
–Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors
–External co-processors
•Master or slave serial peripheral bus interface
–8- to 16-bit programmable data length per chip select–Programmable phase and polarity per chip select
–Programmable transfer delays between consecutive transfers and between clock and data per chip select
–Programmable delay between consecutive transfers–Selectable mode fault detection•Very fast transfers supported
–Transfers with baud rates up to MCK
–The chip select line may be left active to speed up transfers on the same device
10.2Two Wire Interface (TWI)
•Compatibility with standard two-wire serial memory•One, two or three bytes for slave address•Sequential read/write operations•Supports either master or slave modes
•Compatible with Standard Two-wire Serial Memories •Master, Multi-master and Slave Mode Operation •Bit Rate: Up to 400 Kbits
•General Call Supported in Slave mode
•Connection to Peripheral DMA Controller (PDC) Channel Capabilities Optimizes Data Transfers in Master Mode Only
–One Channel for the Receiver, One Channel for the Transmitter –Next Buffer Support
10.3Universal Synchronous Asynchronous Receiver Transmitter (USART)
•Programmable Baud Rate Generator
•5- to 9-bit full-duplex synchronous or asynchronous serial communications–1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode–Parity generation and error detection
–Framing error detection, overrun error detection–MSB- or LSB-first
45
6438BS–ATARM–13-Aug-09
–Optional break generation and detection–By 8 or by-16 over-sampling receiver frequency–Hardware handshaking RTS-CTS
–Receiver time-out and transmitter timeguard
–Optional Multi-drop Mode with address generation and detection–Optional Manchester Encoding•RS485 with driver control signal
•ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards
–NACK handling, error counter with repetition and iteration limit•IrDA modulation and demodulation
–Communication at up to 115.2 Kbps•Test Modes
–Remote Loopback, Local Loopback, Automatic Echo
10.4Serial Synchronous Controller (SSC)
•Provides serial synchronous communication links used in audio and telecom applications (with CODECs in Master or Slave Modes, I2S, TDM Buses, Magnetic Card Reader,...)•Contains an independent receiver and transmitter and a common clock divider•Offers a configurable frame sync and data length
•Receiver and transmitter can be programmed to start automatically or on detection of different event on the frame sync signal
•Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal
10.5AC97 Controller
•Compatible with AC97 Component Specification V2.2•Capable to Interface with a Single Analog Front end
•Three independent RX Channels and three independent TX Channels
–One RX and one TX channel dedicated to the AC97 Analog Front end control –One RX and one TX channel for data transfers, associated with a PDC–One RX and one TX channel for data transfers with no PDC•Time Slot Assigner allowing to assign up to 12 time slots to a channel•Channels support mono or stereo up to 20 bit sample length
–Variable sampling rate AC97 Codec Interface (48KHz and below)
10.6Timer Counter (TC)
•Three 16-bit Timer Counter Channels•Wide range of functions including:
–Frequency Measurement–Event Counting–Interval Measurement–Pulse Generation
46
AT91SAM9G45
6438BS–ATARM–13-Aug-09
AT91SAM9G45
–DelayTiming
–Pulse Width Modulation–Up/down Capabilities
•Each channel is user-configurable and contains:
–Three external clock inputs–Five internal clock inputs
–Two multi-purpose input/output signals
•Two global registers that act on all three TC Channels
10.7Pulse Width Modulation Controller (PWM)
•Four channels, one 16-bit counter per channel
•Common clock generator, providing Thirteen Different Clocks
–A Modulo n counter providing eleven clocks
–Two independent Linear Dividers working on modulo n counter outputs•Independent channel programming
–Independent Enable Disable Commands–Independent Clock Selection
–Independent Period and Duty Cycle, with Double Buffering–Programmable selection of the output waveform polarity–Programmable center or left aligned output waveform
10.8High Speed Multimedia Card Interface (MCI)
•Compatibility with MultiMedia Card Specification Version 4.3•Compatibility with SD Memory Card Specification Version 2.0•Compatibility with SDIO Specification Version V2.0.•Compatibility with Memory Stick PRO
•Compatibility with CE ATA
10.9USB High Speed Host Port (UHPHS)
•Compliant with Enhanced HCI Rev 1.0 Specification
–Compliant with USB V2.0 High-speed and Full-speed Specification–Supports Both High-speed 480Mbps and Full-speed 12 Mbps USB devices•Compliant with Open HCI Rev 1.0 Specification
–Compliant with USB V2.0 Full-speed and Low-speed Specification–Supports Both Low-speed 1.5 Mbps and Full-speed 12 Mbps USB devices•Root Hub Integrated with 2 Downstream USB Ports•Shared Embedded USB Transceivers
10.10USB High Speed Device Port (UDPHS)
•USB V2.0 high-speed compliant, 480 MBits per second
•Embedded USB V2.0 UTMI+ high-speed transceiver shared with UHP HS.
6438BS–ATARM–13-Aug-09
47
•Embedded 4-Kbyte dual-port RAM for endpoints•Embedded 6 channels DMA controller•Suspend/Resume logic
•Up to 2 or 3 banks for isochronous and bulk endpoints•Seven endpoints:
–Endpoint 0: 64 bytes, 1 bank mode
–Endpoint 1 & 2: 1024 bytes, 2 banks mode, High Bandwidth, DMA–Endpoint 3 & 4: 1024 bytes, 3 banks mode, DMA
–Endpoint 5 & 6: 1024 bytes, 3 banks mode, High Bandwidth, DMA
10.11LCD Controller (LCDC)•Single and Dual scan color and monochrome passive STN LCD panels supported•Single scan active TFT LCD panels supported.
•4-bit single scan, 8-bit single or dual scan, 16-bit dual scan STN interfaces supported•Up to 24-bit single scan TFT interfaces supported
•Up to 16 gray levels for mono STN and up to 4096 colors for color STN displays•1, 2 bits per pixel (palletized), 4 bits per pixel (non-palletized) for mono STN•1, 2, 4, 8 bits per pixel (palletized), 16 bits per pixel (non-palletized) for color STN•1, 2, 4, 8 bits per pixel (palletized), 16, 24 bits per pixel (non-palletized) for TFT•Single clock domain architecture•Resolution supported up to 2048 x 2048
10.12Touch Screen Analog-to-Digital Converter (TSADC)•8-channel ADC
•Support 4-wire resistive Touch Screen
•10-bit 384 Ksamples/sec. Successive Approximation Register ADC•-3/+3 LSB Integral Non Linearity, -2/+2 LSB Differential Non Linearity•Integrated 8-to-1 multiplexer, offering eight independent 3.3V analog inputs•External voltage reference for better accuracy on low voltage inputs•Individual enable and disable of each channel•Multiple trigger sources
–Hardware or software trigger–External trigger pin
•Sleep Mode and conversion sequencer
–Automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels
10.13Ethernet 10/100 MAC (EMAC)
•Compatibility with IEEE Standard 802.3
•10 and 100 MBits per second data throughput capability•Full- and half-duplex operations
48
AT91SAM9G45
6438BS–ATARM–13-Aug-09
AT91SAM9G45
•MII or RMII interface to the physical layer
•Register Interface to address, data, status and control registers•DMA Interface, operating as a master on the Memory Controller•Interrupt generation to signal receive and transmit completion•128-byte transmit and 128-byte receive FIFOs
•Automatic pad and CRC generation on transmitted frames•Address checking logic to recognize four 48-bit addresses
•Supports promiscuous mode where all valid frames are copied to memory•Supports physical layer management through MDIO interface
•Supports Wake On Lan. The receiver supports Wake on LAN by detecting the following events on incoming receive frames:
–Magic packet
–ARP request to the device IP address–Specific address 1 filter match–Multicast hash filter match
10.14Image Sensor Interface (ISI)
•ITU-R BT. 601/656 8-bit mode external interface support•Support for ITU-R BT.656-4 SAV and EAV synchronization•Vertical and horizontal resolutions up to 2048 x 2048•Preview Path up to 640*480
•Support for packed data formatting for YCbCr 4:2:2 formats•Preview scaler to generate smaller size image
10.158-channel DMA (DMA)
•Acting as two Matrix Masters
•Embeds 8 unidirectional channels with programmable priority•Address Generation
–Source/Destination address programming–Address increment, decrement or no change
–DMA chaining support for multiple non-contiguous data blocks through use of linked lists
–Scatter support for placing fields into a system memory area from a contiguous transfer. Writing a stream of data into non-contiguous fields in system memory–Gather support for extracting fields from a system memory area into a contiguous transfer
–User enabled auto-reloading of source, destination and control registers from initially programmed values at the end of a block transfer
–Auto-loading of source, destination and control registers from system memory at end of block transfer in block chaining mode
–Unaligned system address to data transfer width supported in hardware•Channel Buffering
49
6438BS–ATARM–13-Aug-09
–16-word FIFO
–Automatic packing/unpacking of data to fit FIFO width•Channel Control
–Programmable multiple transaction size for each channel–Support for cleanly disabling a channel without data loss–Suspend DMA operation
–Programmable DMA lock transfer support•Transfer Initiation
–Support for Software handshaking interface. Memory mapped registers can be used to control the flow of a DMA transfer in place of a hardware handshaking interface•Interrupt
–Programmable Interrupt generation on DMA Transfer completion Block Transfer completion, Single/Multiple transaction completion or Error condition
50
AT91SAM9G45
6438BS–ATARM–13-Aug-09
AT91SAM9G45
11.Mechanical Characteristics
11.1
Package Drawings
Figure 11-1.324-ball TFBGA Package Drawing
6438BS–ATARM–13-Aug-09
51
12.AT91SAM9G45 Ordering Information
Table 12-1.AT91SAM9G45 Ordering InformationPackageTFBGA324Package TypeGreenTemperature Operating Range Industrial-40°C to 85°COrdering CodeAT91SAM9G45-CU52
AT91SAM9G45
6438BS–ATARM–13-Aug-09
AT91SAM9G45
Revision History
Change Request Ref.
Doc. Rev6438AS6438BS
CommentsFirst issue
Section 3. “Signal Description”, Table 3-1 in “Reset/Test” description, NRST pin updated with note concerning NRST configuration.
Section 4. “Package and Pinout”, Table 4-1, updated.
66006669
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6438BS–ATARM–13-Aug-09
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6438BS–ATARM–13-Aug-09
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