CD4060BC

CD4020BC • CD4040BC • CD4060BC14-Stage Ripple Carry Binary Counters •12-Stage Ripple Carry Binary Counters •14-Stage Ripple Carry Binary Counters

General Description

The CD4020BC, CD4060BC are 14-stage ripple carrybinary counters, and the CD4040BC is a 12-stage ripplecarry binary counter. The counters are advanced one counton the negative transition of each clock pulse. Thecounters are reset to the zero state by a logical “1” at thereset input independent of clock.

Features

sWide supply voltage range:3.0V to 15VsHigh noise immunity:0.45 VDD (typ.)sLow power TTL compatibility:or 1 driving 74LSsSchmitt trigger clock input

Fan out of 2 driving 74L

sMedium speed operation:8 MHz typ. at VDD = 10V

Ordering Code:

Order NumberCD4020BCMCD4020BCNCD4040BCMCD4040BCSJCD4040BCNCD4060BCMCD4060BCN

Package Number

M16AN16EM16AM16DN16EM16AN16E

Package Description

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150\" Narrow16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300\" Wide16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150\" Narrow16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300\" Wide16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150\" Narrow16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300\" Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagrams

Pin Assignments for DIP and SOIC

CD4020BC

Pin Assignments for DIP, SOIC and SOP

CD4040BC

Top View

Top View

© 2001 Fairchild Semiconductor CorporationDS005953www.fairchildsemi.com

CD4020BC • CD4040BC • CD4060BCConnection Diagrams (Continued)

Pin Assignments for DIP and SOIC

CD4060BC

Top View

Schematic Diagrams

CD4020BC

CD4040BC

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CD4020BC • CD4040BC • CD4060BCSchematic Diagrams (Continued)

CD4060BC

CD4060B Typical Oscillator Connections

RC Oscillator

Crystal Oscillator

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CD4020BC • CD4040BC • CD4060BCAbsolute Maximum Ratings(Note 1)

(Note 2)

Supply Voltage (VDD)Input Voltage (VIN)

Storage Temperature Range (TS)Package Dissipation (PD)Dual-In-LineSmall OutlineLead Temperature (TL)(Soldering, 10 seconds)

260°C700 mW500 mW

Recommended OperatingConditions

Supply Voltage (VDD)Input Voltage (VIN)

Operating Temperature Range (TA)

−0.5V to +18V−0.5V to VDD +0.5V−65°C to +150°C

+3V to +15V0V to VDD

−40°C to +85°C

Note 1: “Absolute Maximum Ratings” are those values beyond which thesafety of the device cannot be guaranteed. They are not meant to implythat the devices should be operated at these limits. The tables of “Recom-mended Operating Conditions” and “Electrical Characteristics” provide con-ditions for actual device operation.

Note 2: VSS = 0V unless otherwise specified.

DC Electrical Characteristics (Note 2)

SymbolIDD

Parameter

Quiescent Device Current

Conditions

VDD = 5V, VIN = VDD or VSSVDD = 10V, VIN = VDD or VSSVDD = 15V, VIN = VDD or VSS

VOL

LOW Level Output Voltage

VDD = 5VVDD = 10VVDD = 15V

VOH

HIGH Level Output Voltage

VDD = 5VVDD = 10VVDD = 15V

VIL

LOW Level Input Voltage

VDD = 5V, VO = 0.5V or 4.5VVDD = 10V, VO = 1.0V or 9.0VVDD = 15V, VO = 1.5V or 13.5V

VIH

HIGH Level Input Voltage

VDD = 5V, VO = 0.5V or 4.5VVDD = 10V, VO = 1.0V or 9.0VVDD = 15V, VO = 1.5V or 13.5V

IOL

LOW Level Output Current(Note 3)

IOH

HIGH Level Output Current(Note 3)

IIN

Input Current

VDD = 5V, VO = 0.4VVDD = 10V, VO = 0.5VVDD = 15V, VO = 1.5VVDD = 5V, VO = 4.6VVDD = 10V, VO = 9.5VVDD = 15V, VO = 13.5VVDD = 15V, VIN = 0VVDD = 15V, VIN = 15V

3.57.011.00.521.33.6−0.52−1.3−3.6

−0.300.30

4.959.9514.95

1.53.04.0

3.57.011.00.441.13.0−0.44−1.1−3.0

−40°CMin

Max2040800.050.050.05

4.959.9514.95

000510152463690.882.258.8−0.88−2.25−8.8−10−510−5

−0.300.301.53.04.0

3.57.011.00.360.92.4−0.36−0.9−2.4

−1.01.0

µAmAmAV

Min

+25°CTyp

Max2040800.050.050.05

4.959.9514.95

1.53.04.0

VV

+85°CMin

Max1503006000.050.050.05

VµAUnits

Note 3: Data does not apply to oscillator points φ0 and φ0 of CD4060BC. IOH and IOL are tested one output at a time.

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CD4020BC • CD4040BC • CD4060BCAC Electrical Characteristics (Note 4)

CD4020BC, CD4040BC TA = 25°C, CL = 50 pF, RL = 200k, tr = tf = 20 ns, unless otherwise noted

SymboltPHL1, tPLH1

Parameter

Propagation Delay Time to Q1

VDD = 5VVDD = 10VVDD = 15V

tPHL, tPLH

Interstage Propagation Delay Timefrom Qn to Qn+1

tTHL, tTLH

Transition Time

VDD = 5VVDD = 10VVDD = 15VVDD = 5VVDD = 10VVDD = 15V

tWL, tWH

Minimum Clock Pulse Width

VDD = 5VVDD = 10VVDD = 15V

trCL, tfCL

Maximum Clock Rise and Fall TimeVDD = 5V

VDD = 10VVDD = 15V

fCL

Maximum Clock Frequency

VDD = 5VVDD = 10VVDD = 15V

tPHL(R)

Reset Propagation Delay

VDD = 5VVDD = 10VVDD = 15V

tWH(R)

Minimum Reset Pulse Width

VDD = 5VVDD = 10VVDD = 15V

CINCPD

Average Input CapacitancePower Dissipation Capacitance

Any Input

1.545

410122001008020010080550

4502101704502101707.5

pFpFnsnsMHz

Conditions

Min

Typ25010075150604510050401255040

Max5502101503301259020010080335125100No LimitNo LimitNo Limit

nsnsnsnsnsUnits

Note 4: AC Parameters are guaranteed by DC correlated testing.

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CD4020BC • CD4040BC • CD4060BCAC Electrical Characteristics (Note 5)

CD4060BC TA = 25°C, CL = 50 pF, RL = 200k, tr = tf = 20 ns, unless otherwise noted

SymboltPHL4, tPLH4

Parameter

Propagation Delay Time to Q4

VDD = 5VVDD = 10VVDD = 15V

tPHL, tPLH

Interstage Propagation Delay Timefrom Qn to Qn+1

tTHL, tTLH

Transition Time

VDD = 5VVDD = 10VVDD = 15VVDD = 5VVDD = 10VVDD = 15V

tWL, tWH

Minimum Clock Pulse Width

VDD = 5VVDD = 10VVDD = 15V

trCL, tfCL

Maximum Clock Rise and Fall TimeVDD = 5V

VDD = 10VVDD = 15V

fCL

Maximum Clock Frequency

VDD = 5VVDD = 10VVDD = 15V

tPHL(R)

Reset Propagation Delay

VDD = 5VVDD = 10VVDD = 15V

tWH(R)

Minimum Reset Pulse Width

VDD = 5VVDD = 10VVDD = 15V

CINCPD

Average Input CapacitancePower Dissipation Capacitance

Any Input

134

38102001008020010080550

4502101704502101707.5

pFpFnsnsMHz

Conditions

Min

Typ550250200150604510050401706550

Max13005254003301259020010080500170125No LimitNo LimitNo Limit

nsnsnsnsnsUnits

Note 5: AC Parameters are guaranteed by DC correlated testing.

RC Oscillator Notes:1.R2 = 2 R1 to 10 R1

2.RC Oscillator applications are not recommended at supply voltages below 7.0V for R1 < 50 kΩ3.f ≈

12.2 R1 CX

at VCC = 10V

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CD4020BC • CD4040BC • CD4060BCPhysical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150\" Narrow

Package Number M16A

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CD4020BC • CD4040BC • CD4060BCPhysical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M16D

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CD4020BC • CD4040BC • CD4060BC 14-Stage Ripple Carry Binary Counters • 12-Stage Ripple Carry Binary Counters • 14-Stage Ripple Carry Binary CountersPhysical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300\" Wide

Package Number N16E

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied andFairchild reserves the right at any time without notice to change said circuitry and specifications.LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILDSEMICONDUCTOR CORPORATION. As used herein:1.Life support devices or systems are devices or systemswhich, (a) are intended for surgical implant into thebody, or (b) support or sustain life, and (c) whose failureto perform when properly used in accordance withinstructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to theuser.

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2.A critical component in any component of a life supportdevice or system whose failure to perform can be rea-sonably expected to cause the failure of the life supportdevice or system, or to affect its safety or effectiveness.

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