专利名称：CLOCK SIGNAL GENERATOR发明人：GREHL, UDO,DALLMANN, ACHIM申请号：EP97921617.3申请日：19970417公开号：EP0897614B1公开日：20001108
摘要：The invention concerns a clock signal generator which can generate a firstoutput clock signal (PHI1) and/or a second output clock signal (PHI2) from an input clocksignal (CLK) by shifting its rising and/or falling flanks by means of time-delay modules(140; 240, 290). The clock signal generator according to the invention is characterized inthat a time-delay module comprises a plurality of time-delay elements (141 to 145; 241to 245, 291 to 295), which are interconnected in parallel and cause delays of differentlengths, and a selector device (145; 245, 295) which can determine which of the outputsignals of the time-delay elements should be output as the time-delay module outputsignal.
申请人：SIEMENS AKTIENGESELLSCHAFT,SIEMENS AG,SIEMENS AKTIENGESELLSCHAFT
地址：DE
国籍：DE
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