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Preliminary v0.4

Actel Fusion Mixed-Signal FPGAs

for the MicroBlade Advanced Mezzanine Card SolutionFeatures and Benefits

•Targeted to Advanced Mezzanine Card (AdvancedMC™)Designs

•Designed in Partnership with MicroBlade

•8051-Based Module Management Controller (MMC)

•Fully Compliant with PICMG AMC.0.R2.0 and IPMI v2.0Specifications

•AdvancedMC Reference Design and Starter Kit

•Crystal Oscillator Support (32 kHz to 20 MHz) •Programmable Real-Time Counter (RTC)

•6 Clock Conditioning Circuits (CCCs) with 1 or 2 IntegratedPLLs

–Phase Shift, Multiply/Divide, and Delay Capabilities–Frequency: Input 1.5–350 MHz, Output 0.75–350 MHz

Low Power Consumption

High-Performance Reprogrammable Flash Technology

••••

•Single 3.3 V Power Supply with On-Chip 1.5 V Regulator •Sleep and Standby Low Power Modes•Secure ISP with 128-Bit AES via JTAG•FlashLock® to Secure FPGA Contents

In-System Programming (ISP) and SecurityAdvanced Digital I/O

Advanced 130-nm, 7-Layer Metal, Flash-Based CMOS ProcessNonvolatile, Retains Program when Powered OffLive at Power-Up (LAPU) Single-Chip Solution350 MHz System Performance

Embedded Flash Memory

•User Flash Memory – 2 Mbits to 8 Mbits–Configurable 8-, 16-, or 32-Bit Datapath–10 ns Access in Read-Ahead Mode•1 kbit of Additional FlashROM••••••

Up to 12-Bit Resolution and up to 600 kspsInternal 2.56 V or External Reference VoltageADC: Up to 30 Scalable Analog Input ChannelsHigh-Voltage Input Tolerance: –10.5 V to +12 VCurrent Monitor and Temperature Monitor BlocksUp to 10 MOSFET Gate Driver Outputs

–P- and N-Channel Power MOSFET Support

–Programmable 1, 3, 10, 30 µA and 20 mA Drive Strengths•ADC Accuracy is Better than 1%

•Internal 100 MHz RC Oscillator (accurate to 1%)

Integrated A/D Converter (ADC) and Analog I/O

•1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation•Bank-Selectable I/O Voltages – Up to 5 Banks per Chip

•Single-Ended I/O Standards: LVTTL, LVCMOS3.3V/2.5V/1.8V/1.5V, 3.3VPCI / 3.3VPCI-X, andLVCMOS 2.5V/5.0V Input

•Differential I/O Standards: LVPECL, LVDS, BLVDS, and M-LVDS–Built-In I/O Registers

–700 Mbps DDR Operation•Hot-Swappable I/Os

•Programmable Output Slew Rate, Drive Strength, and WeakPull-Up/Down Resistor

•Pin-Compatible Packages across the Fusion Family

•Variable-Aspect-Ratio 4,608-Bit SRAM Blocks (×1, ×2, ×4, ×9,and ×18 organizations available)•True Dual-Port SRAM (except ×18)

•Programmable Embedded FIFO Control Logic

SRAMs and FIFOs

On-Chip Clocking Support

MicroBlade Fusion SolutionsFusion Devices

U1AFS25

System GatesTiles (D-flip-flops)

250,0006,144Yes11812 M1 k83661811424

U1AFS600600,00013,824Yes21824 M1 k24108103010517240

U1AFS15001,500,00038,400Yes21848 M1 k60270103010525240

General InformationSecure (AES) ISPPLLsGlobals

Flash Memory Blocks (2 Mbits)Total Flash Memory Bits

MemoryFlashROM Bits

RAM Blocks (4,608 bits)RAM kbits Analog Quads

Analog Input ChannelsGate Driver OutputsI/O Banks (+ JTAG)Maximum Digital I/OsAnalog I/Os

Analog and I/Os

Notes:

1.Refer to the CoreMP7 datasheet for more information.

2.Refer to the Cortex-M1 product brief for more information.

October 2008

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Actel Fusion Mixed-Signal FPGAs for the MicroBlade AdvancedMC Solution

Fusion Device Architecture Overview

Bank 0Bank 1CCCSRAM Block4,608-Bit Dual-Port SRAM or FIFO BlockOSCI/OsCCC/PLLVersaTileBank 2Bank 4ISP AESDecryptionUser NonvolatileFlashROMCharge PumpsSRAM Block4,608-Bit Dual-Port SRAM or FIFO BlockFlash Memory BlocksADCFlash Memory BlocksAnalog QuadAnalog QuadAnalog QuadAnalog QuadAnalog QuadAnalog QuadAnalog QuadAnalog Analog QuadQuadAnalog QuadCCCBank 3Figure 1-1 • Fusion Device Architecture Overview (U1AFS600)

Package I/Os: Single-/Double-Ended (Analog)

Fusion DevicesFG256

U1AFS250114/37 (24)

U1AFS600119/58 (40)

U1AFS1500119/58 (40)

Note:All devices in the same package are pin compatible with the exception of the PQ208 package (AFS250 and AFS600).

IIPreliminary v0.4

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Actel Fusion Mixed-Signal FPGAs for the MicroBlade AdvancedMC Solution

Product Ordering Codes

U1AFS600_FGG256IApplication (ambient temperature range)Blank=Commercial (0 to +70°C)I=Industrial (–40 to +85°C)Package Lead CountLead-Free Packaging Options Blank = Standard Packaging G = RoHS-Compliant (green) PackagingPackage TypeFG=Fine Pitch Ball Grid Array (1.0 mm pitch)Speed Grade Blank=StandardPart Number U1AFS250=250,000 System Gates U1AFS600=600,000 System GatesU1AFS1500=1,500,000 System GatesPreliminary v0.4III

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Actel Fusion Mixed-Signal FPGAs for the MicroBlade AdvancedMC Solution

Temperature Grade Offerings

MicroBlade-Based Fusion DevicesFG256

U1AFS250

C, I

U1AFS600

C, I

U1AFS1500

C, I

Notes:

1.C = Commercial Temperature Range: 0°C to 70°C Ambient2.I = Industrial Temperature Range: –40°C to 85°C Ambient

Speed Grade and Temperature Grade Matrix

Std.

1I2Notes:

1.C = Commercial Temperature Range: 0°C to 70°C Ambient2.I = Industrial Temperature Range: –40°C to 85°C Ambient

✓✓Contact your local Actel representative for device availability (http://www.actel.com/contact/offices/index.html).

IVPreliminary v0.4

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1 – Fusion Device Family Overview

Introduction

The Actel MicroBlade-based Fusion® mixed-signal FPGA satisfies the demand from systemarchitects for a device that simplifies design and unleashes their creativity. As the world’s firstmixed-signal programmable logic family, MicroBlade-based Fusion integrates mixed-signalanalog, flash memory, and FPGA fabric in a monolithic device. Actel MicroBlade-based Fusiondevices enable designers to quickly move from concept to completed design and then deliverfeature-rich systems to market. This new technology takes advantage of the unique properties ofActel flash-based FPGAs, including a high-isolation, triple-well process and the ability to supporthigh-voltage transistors to meet the demanding requirements of mixed-signal system design. Actel Fusion mixed-signal FPGAs bring the benefits of programmable logic to many applicationareas, including power management, smart battery charging, clock generation and management,and motor control. Until now, these applications have only been implemented with costly andspace-consuming discrete analog components or mixed-signal ASIC solutions. Actel Fusion mixed-signal FPGAs present new capabilities for system development by allowing designers to integrate awide range of functionality into a single device, while at the same time offering the flexibility ofupgrades late in the manufacturing process or after the device is in the field. Actel Fusion devicesprovide an excellent alternative to costly and time-consuming mixed-signal ASIC designs. Inaddition, when used in conjunction with the Actel for the MicroTCA market. Actel Fusiontechnology represents the definitive mixed-signal FPGA platform.

Flash-based Fusion devices are live at power-up. As soon as system power is applied and withinnormal operating specifications, Fusion devices are working. Fusion devices have a 128-bit flash-based lock and industry-leading AES decryption, used to secure programmed intellectual property(IP) and configuration data. Actel Fusion devices are the most comprehensive single-chip analogand digital programmable logic solution available today.

To support this new ground-breaking technology, Actel has developed a series of major toolinnovations to help maximize designer productivity. Implemented as extensions to the popularActel Libero® Integrated Design Environment (IDE), these new tools allow designers to easilyinstantiate and configure peripherals within a design, establish links between peripherals, createor import building blocks or reference designs, and perform hardware verification. This tool suitewill also add comprehensive hardware/software debug capability as well as a suite of utilities tosimplify development of embedded soft-processor-based solutions.

MicroBlade-based Fusion (U1AFS) devices are targeted to Actel’s Advanced Mezzanine Card (AMC)design developed in partnership with MicroBlade, Inc. The AMC design is an 8051-based ModuleManagement Controller (MMC) and is fully compliant with the PICMG Advanced Mezzanine CardAMC.0 R2.0 and IPMI v2.0 specification, implementing in the AMC reference design and AMCStarter Kit as a complete board including a variable load board 100 W payload. The AMC referencedesign is available for free download from the Actel website, including board design files,documentation, FPGA design as a complete Libero® Integrated Design Environment (IDE) project,and an executable firmware image. The AMC Starter Kit adds complete firmware source code in Cformat. Designs based on the AMC Starter Kit (part number UTCA-AMC-SK) design are required touse one of the U1AFS devices: U1AFS250, U1AFS600, or U1AFS1500.

Preliminary v0.41-1

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Fusion Device Family Overview

General Description

The Actel MicroBlade-based Fusion family, based on the highly successful ProASIC®3 and ProASIC3EFlash FPGA architecture, has been designed as a high-performance, programmable, mixed-signalplatform. By combining an advanced flash FPGA core with flash memory blocks and analogperipherals, Fusion devices dramatically simplify system design and, as a result, dramatically reduceoverall system cost and board space.

The state-of-the-art flash memory technology offers high-density integrated flash memory blocks,enabling savings in cost, power, and board area relative to external flash solutions, while providingincreased flexibility and performance. The flash memory blocks and integrated analog peripheralsenable true mixed-mode programmable logic designs. Two examples are using an on-chip softprocessor to implement a fully functional Flash MCU and using high-speed FPGA logic to offersystem and power supervisory capabilities. Live at power-up and capable of operating from a single3.3V supply, the Fusion family is ideally suited for system management and control applications.The devices in the Fusion family are categorized by FPGA core density. Each family membercontains many peripherals, including flash memory blocks, an analog-to-digital-converter (ADC),high-drive outputs, both RC and crystal oscillators, and a real-time counter (RTC). This provides theuser with a high level of flexibility and integration to support a wide variety of mixed-signalapplications. The flash memory block capacity ranges from 2 Mbits to 8 Mbits. The integrated 12-bit ADC supports up to 30 independently configurable input channels. The on-chip crystal and RCoscillators work in conjunction with the integrated phase-locked loops (PLLs) to provide clockingsupport to the FPGA array and on-chip resources. In addition to supporting typical RTC uses such aswatchdog timer, the Fusion RTC can control the on-chip voltage regulator to power down thedevice (FPGA fabric, flash memory block, and ADC), enabling a low-power standby mode.

The Actel MicroBlade-based Fusion family offers revolutionary features, never before available inan FPGA. The nonvolatile flash technology gives the Fusion solution the advantage of being asecure, low-power, single-chip solution that is live at power-up. Fusion is reprogrammable andoffers time to market benefits at an ASIC-level unit cost. These features enable designers to createhigh-density systems using existing ASIC or FPGA design flows and tools.

The family has up to 1.5 M system gates, supported with up to 270 kbits of true dual-port SRAM, upto 8 Mbits of flash memory, 1 kbit of user FlashROM, and up to 278 user I/Os. With integrated flashmemory, the Fusion family is the ultimate soft-processor platform.

Flash Advantages

Reduced Cost of Ownership

Advantages to the designer extend beyond low unit cost, high performance, and ease of use. Flash-based Fusion devices are live at power-up and do not need to be loaded from an external bootPROM. On-board security mechanisms prevent access to the programming information and enablesecure remote updates of the FPGA logic. Designers can perform secure remote in-systemreprogramming to support future design iterations and field upgrades, with confidence thatvaluable IP cannot be compromised or copied. Secure ISP can be performed using the industry-standard AES algorithm with MAC data authentication on the device. The Fusion family devicearchitecture mitigates the need for ASIC migration at higher user volumes. This makes the Fusionfamily a cost-effective ASIC replacement solution for applications in the consumer, networking andcommunications, computing, and avionics markets.

Security

As the nonvolatile, flash-based Fusion family requires no boot PROM, there is no vulnerableexternal bitstream. Fusion devices incorporate FlashLock, which provides a unique combination ofreprogrammability and design security without external overhead, advantages that only an FPGAwith nonvolatile flash programming can offer.

Fusion devices utilize a 128-bit flash-based key lock and a separate AES key to secure programmedIP and configuration data. The FlashROM data in Fusion devices can also be encrypted prior toloading. Additionally, the Flash memory blocks can be programmed during runtime using theindustry-leading AES-128 block cipher encryption standard (FIPS Publication 192). The AES standard

1-2Preliminary v0.4

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Actel Fusion Mixed-Signal FPGAs for the MicroBlade AdvancedMC Solution

was adopted by the National Institute of Standards and Technology (NIST) in 2000 and replaces theDES standard, which was adopted in 1977. Fusion devices have a built-in AES decryption engineand a flash-based AES key that make Fusion devices the most comprehensive programmable logicdevice security solution available today. Fusion devices with AES-based security allow for secureremote field updates over public networks, such as the Internet, and ensure that valuable IPremains out of the hands of system overbuilders, system cloners, and IP thieves. As an additionalsecurity measure, the FPGA configuration data of a programmed Fusion device cannot be readback, although secure design verification is possible. During design, the user controls and definesboth internal and external access to the flash memory blocks.

Security, built into the FPGA fabric, is an inherent component of the Fusion family. The Flash cellsare located beneath seven metal layers, and many device design and layout techniques have beenused to make invasive attacks extremely difficult. Fusion with FlashLock and AES security is uniquein being highly resistant to both invasive and noninvasive attacks. Your valuable IP is protected,making secure remote ISP possible. A Fusion device provides the most impenetrable security forprogrammable logic designs.

Single Chip

Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed,the configuration data is an inherent part of the FPGA structure, and no external configurationdata needs to be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-basedFusion FPGAs do not require system configuration components such as EEPROMs ormicrocontrollers to load device configuration data. This reduces bill-of-materials costs and PCBarea, and increases security and system reliability.

Live at Power-Up

Flash-based Fusion devices are Level 0 live at power-up (LAPU). LAPU Fusion devices greatly simplifytotal system design and reduce total system cost by eliminating the need for CPLDs. The FusionLAPU clocking (PLLs) replaces off-chip clocking resources. The Fusion mix of LAPU clocking andanalog resources makes these devices an excellent choice for both system supervisor and systemmanagement functions. LAPU from a single 3.3V source enables Fusion devices to initiate, control,and monitor multiple voltage supplies while also providing system clocks. In addition, glitches andbrownouts in system power will not corrupt the Fusion device flash configuration. Unlike SRAM-based FPGAs, the device will not have to be reloaded when system power is restored. This enablesreduction or complete removal of expensive voltage monitor and brownout detection devices fromthe PCB design. Flash-based Fusion devices simplify total system design and reduce cost and designrisk, while increasing system reliability.

Firm Errors

Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere,strike a configuration cell of an SRAM FPGA. The energy of the collision can change the state of theconfiguration cell and thus change the logic, routing, or I/O behavior in an unpredictable way.Another source of radiation-induced firm errors is alpha particles. For an alpha to cause a soft orfirm error, its source must be in very close proximity to the affected circuit. The alpha source mustbe in the package molding compound or in the die itself. While low-alpha molding compounds arebeing used increasingly, this helps reduce but does not entirely eliminate alpha-induced firm errors.Firm errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can bea complete system failure. Firm errors do not occur in Fusion Flash-based FPGAs. Once it isprogrammed, the flash cell configuration element of Fusion FPGAs cannot be altered by high-energy neutrons and is therefore immune to errors from them.

Recoverable (or soft) errors occur in the user data SRAMs of all FPGA devices. These can easily bemitigated by using error detection and correction (EDAC) circuitry built into the FPGA fabric.

Low Power

Flash-based Fusion devices exhibit power characteristics similar to those of an ASIC, making theman ideal choice for power-sensitive applications. With Fusion devices, there is no power-on currentsurge and no high current transition, both of which occur on many FPGAs.

Fusion devices also have low dynamic power consumption and support both low power standbymode and very low power sleep mode, offering further power savings.

Preliminary v0.41-3

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Fusion Device Family Overview

Advanced Flash Technology

The Fusion family offers many benefits, including nonvolatility and reprogrammability through anadvanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS designtechniques are used to implement logic and control functions. The combination of fine granularity,enhanced flexible routing resources, and abundant flash switches allows very high logic utilization(much higher than competing SRAM technologies) without compromising device routability orperformance. Logic functions within the device are interconnected through a four-level routinghierarchy.

Advanced Architecture

The proprietary Fusion architecture provides granularity comparable to standard-cell ASICs. TheFusion device consists of several distinct and programmable architectural features, including thefollowing (Figure1-1 on page1-6):

•

Embedded memories–Flash memory blocks–FlashROM –SRAM and FIFO•

Clocking resources

–PLL and CCC–

RC oscillator

–

Crystal oscillator

–No-Glitch MUX (NGMUX)

•Digital I/Os with advanced I/O standards•FPGA VersaTiles•

Analog components –ADC

–

Analog I/Os supporting voltage, current, and temperature monitoring

–

1.5 V on-board voltage regulator

–

Real-time counter

The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-inputlogic lookup table (LUT) equivalent or a D-flip-flop or latch (with or without enable) byprogramming the appropriate flash switch interconnections. This versatility allows efficient use ofthe FPGA fabric. The VersaTile capability is unique to the Actel families of flash-based FPGAs.VersaTiles and larger functions are connected with any of the four levels of routing hierarchy. Flashswitches are distributed throughout the device to provide nonvolatile, reconfigurable interconnectprogramming. Maximum core utilization is possible for virtually any design.

In addition, extensive on-chip programming circuitry allows for rapid (3.3V) single-voltageprogramming of Fusion devices via an IEEE 1532 JTAG interface.

1-4Preliminary v0.4

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Actel Fusion Mixed-Signal FPGAs for the MicroBlade AdvancedMC Solution

Unprecedented Integration

Integrated Analog Blocks and Analog I/Os

Fusion devices offer robust and flexible analog mixed-signal capability in addition to the high-performance flash FPGA fabric and flash memory block. The many built-in analog peripheralsinclude a configurable 32:1 input analog MUX, up to 10 independent MOSFET gate driver outputs,and a configurable ADC. The ADC supports 8-, 10-, and 12-bit modes of operation with acumulative sample rate up to 600 k samples per second (ksps), differential nonlinearity (DNL) < 1.0LSB, and Total Unadjusted Error (TUE) of 0.72 LSB in 10-bit mode. The TUE is used forcharacterization of the conversion error and includes errors from all sources, such as offset andlinearity. Internal bandgap circuitry offers 1% voltage reference accuracy with the flexibility ofutilizing an external reference voltage. The ADC channel sampling sequence and sampling rate areprogrammable and implemented in the FPGA logic using Designer and Libero IDE software toolsupport.

Two channels of the 32-channel ADCMUX are dedicated. Channel 0 is connected internally to VCCand can be used to monitor core power supply. Channel 31 is connected to an internal temperaturediode which can be used to monitor device temperature. The 30 remaining channels can beconnected to external analog signals. The exact number of I/Os available for external connectionsignals is device-dependent (refer to the \"MicroBlade Fusion Solutions\" table on page I for details). With Fusion, Actel also introduces the Analog Quad I/O structure (Figure1-1 on page1-6). Eachquad consists of three analog inputs and one gate driver. Each quad can be configured in variousbuilt-in circuit combinations, such as three prescaler circuits, three digital input circuits, a currentmonitor circuit, or a temperature monitor circuit. Each prescaler has multiple scaling factorsprogrammed by FPGA signals to support a large range of analog inputs with positive or negativepolarity. When the current monitor circuit is selected, two adjacent analog inputs measure thevoltage drop across a small external sense resistor. Built-in operational amplifiers amplify smallvoltage signals (2mV sensitivity) for accurate current measurement. One analog input in each quadcan be connected to an external temperature monitor diode and achieves detection accuracy of±3ºC. In addition to the external temperature monitor diode(s), a Fusion device can monitor aninternal temperature diode using dedicated channel 31 of the ADCMUX.

Figure1-1 on page1-6 illustrates a typical use of the Analog Quad I/O structure. The Analog Quadshown is configured to monitor and control an external power supply. The AV pad measures thesource of the power supply. The AC pad measures the voltage drop across an external sense resistor

Preliminary v0.41-5

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Fusion Device Family Overview

to calculate current. The AG MOSFET gate driver pad turns the external MOSFET on and off. The ATpad measures the load-side voltage level.

PowerLine SideLoad SideOff-ChipRpullupAVACAGATPadsVoltageCurrentGateTemperatureMonitor BlockMonitor BlockDriverMonitor BlockOn-ChipAnalog QuadPre-Pre-Pre-scalerscalerscalerPowerDigitalDigitalMOSFETInputInputGate DriverDigitalInputCurrentMonitor/InstrTemperatureAmplifierMonitorTo FPGATo FPGAFrom FPGATo FPGA(DAVOUTx)(DACOUTx)(GDONx)(DATOUTx)To Analog MUX To Analog MUX To Analog MUX Figure 1-1 • Analog Quad

Embedded Memories

Flash Memory Blocks

The flash memory available in each Fusion device is composed of one to four flash blocks, each 2Mbits in density. Each block operates independently with a dedicated flash controller andinterface. Fusion flash memory blocks combine fast access times (60ns random access and 10nsaccess in Read-Ahead mode) with a configurable 8-, 16-, or 32-bit datapath, enabling high-speedflash operation without wait states. The memory block is organized in pages and sectors. Eachpage has 128 bytes, with 33 pages comprising one sector and sectors per block. The flash blockcan support multiple partitions. The only constraint on size is that partition boundaries mustcoincide with page boundaries. The flexibility and granularity enable many use models and allowadded granularity in programming updates.

Fusion devices support two methods of external access to the flash memory blocks. The firstmethod is a serial interface that features a built-in JTAG-compliant port, which allows in-systemprogrammability during user or monitor/test modes. This serial interface supports programming ofan AES-encrypted stream. Secure data can be passed through the JTAG interface, decrypted, andthen programmed in the flash block. The second method is a soft parallel interface.

FPGA logic or an on-chip soft microprocessor can access flash memory through the parallelinterface. Since the flash parallel interface is implemented in the FPGA fabric, it can potentially becustomized to meet special user requirements. For more information, refer to the CoreCFI

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Actel Fusion Mixed-Signal FPGAs for the MicroBlade AdvancedMC Solution

Handbook. The flash memory parallel interface provides configurable byte-wide (×8), word-wide(×16), or dual-word-wide (×32) data port options. Through the programmable flash parallelinterface, the on-chip and off-chip memories can be cascaded for wider or deeper configurations. The flash memory has built-in security. The user can configure either the entire flash block or thesmall blocks to prevent unintentional or intrusive attempts to change or destroy the storagecontents. Each on-chip flash memory block has a dedicated controller, enabling each block tooperate independently.

The flash block logic consists of the following sub-blocks:

••••

Flash block – Contains all stored data. The flash block contains sectors and each sectorcontains 33 pages of data.

Page Buffer – Contains the contents of the current page being modified. A page contains 8blocks of data.

Block Buffer – Contains the contents of the last block accessed. A block contains 128 databits.

ECC Logic – The flash memory stores error correction information with each block toperform single-bit error correction and double-bit error detection on all data blocks.

User Nonvolatile FlashROM

In addition to the flash blocks, Actel Fusion devices have 1kbit of user-accessible, nonvolatileFlashROM on-chip. The FlashROM is organized as 8×128-bit pages. The FlashROM can be used indiverse system applications:

••••••••

Internet protocol addressing (wireless or fixed)System calibration settings

Device serialization and/or inventory control

Subscription-based business models (for example, set-top boxes)Secure key storage for secure communications algorithmsAsset management/trackingDate stampingVersion management

The FlashROM is written using the standard IEEE 1532 JTAG programming interface. Pages can beindividually programmed (erased and written). On-chip AES decryption can be used selectively overpublic networks to securely load data such as security keys stored in the FlashROM for a userdesign.

The FlashROM can be programmed (erased and written) via the JTAG programming interface, andits contents can be read back either through the JTAG programming interface or via direct FPGAcore addressing.

The FlashPoint tool in the Actel Fusion development software solutions, Libero IDE and Designer,has extensive support for flash memory blocks and FlashROM. One such feature is auto-generationof sequential programming files for applications requiring a unique serial number in each part.Another feature allows the inclusion of static data for system version control. Data for theFlashROM can be generated quickly and easily using the Actel Libero IDE and Designer softwaretools. Comprehensive programming file support is also included to allow for easy programming oflarge numbers of parts with differing FlashROM contents.

SRAM and FIFO

Fusion devices have embedded SRAM blocks along the north and south sides of the device. Eachvariable-aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256×18,512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks have independent read and write ports thatcan be configured with different bit widths on each port. For example, data can be writtenthrough a 4-bit port and read as a single bitstream. The SRAM blocks can be initialized from theflash memory blocks or via the device JTAG port (ROM emulation mode), using the UJTAG macro. In addition, every SRAM block has an embedded FIFO control unit. The control unit allows theSRAM block to be configured as a synchronous FIFO without using additional core VersaTiles. TheFIFO width and depth are programmable. The FIFO also features programmable Almost Empty

Preliminary v0.41-7

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Fusion Device Family Overview

(AEMPTY) and Almost Full (AFULL) flags in addition to the normal EMPTY and FULL flags. Theembedded FIFO control unit contains the counters necessary for the generation of the read andwrite address pointers. The SRAM/FIFO blocks can be cascaded to create larger configurations.

Clock Resources

PLLs and Clock Conditioning Circuits (CCCs)

Fusion devices provide designers with very flexible clock conditioning capabilities. Each member ofthe Fusion family contains six CCCs. In the two larger family members, two of these CCCs alsoinclude a PLL; the smaller devices support one PLL.

The inputs of the CCC blocks are accessible from the FPGA core or from one of several inputs withdedicated CCC block connections.

The CCC block has the following key features:

•Wide input frequency range (fIN_CCC) = 1.5MHz to 350MHz•Output frequency range (fOUT_CCC) = 0.75MHz to 350MHz

•Clock phase adjustment via programmable and fixed delays from –6.275 ns to +8.75 ns•Clock skew minimization (PLL)•Clock frequency synthesis (PLL)

•

On-chip analog clocking resources usable as inputs:–100 MHz on-chip RC oscillator–Crystal oscillator

Additional CCC specifications:

•Internal phase shift = 0°, 90°, 180°, and 270° •Output duty cycle = 50% ± 1.5%

•

Low output jitter. Samples of peak-to-peak period jitter when a single global network isused:–70 ps at 350 MHz–90 ps at 100 MHz–180 ps at 24 MHz

–Worst case < 2.5% × clock period

•Maximum acquisition time = 150 µs •

Low power consumption of 5 mW

Global Clocking

Fusion devices have extensive support for multiple clocking domains. In addition to the CCC andPLL support described above, there are on-chip oscillators as well as a comprehensive global clockdistribution network.

The integrated RC oscillator generates a 100MHz clock. It is used internally to provide a knownclock source to the flash memory read and write control. It can also be used as a source for the PLLs.The crystal oscillator supports the following operating modes:

•Crystal (32.768 kHz to 20 MHz)•Ceramic (500 kHz to 8 MHz)•

RC (32.768 kHz to 4 MHz)

Each VersaTile input and output port has access to nine VersaNets: six main and three quadrantglobal networks. The VersaNets can be driven by the CCC or directly accessed from the core viaMUXes. The VersaNets can be used to distribute low-skew clock signals or for rapid distribution ofhigh-fanout nets.

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Actel Fusion Mixed-Signal FPGAs for the MicroBlade AdvancedMC Solution

Digital I/Os with Advanced I/O Standards

The Fusion family of FPGAs features a flexible digital I/O structure, supporting a range of voltages(1.5V, 1.8V, 2.5V, and 3.3V). Fusion FPGAs support many different digital I/O standards, bothsingle-ended and differential.

The I/Os are organized into banks, with four or five banks per device. The configuration of thesebanks determines the I/O standards supported. The banks along the east and west sides of thedevice support the full range of I/O standards (single-ended and differential). The south banksupports the Analog Quads (analog I/O). In the family's two smaller devices, the north banksupports multiple single-ended digital I/O standards. In the family’s larger devices, the north bank isdivided into two banks of digital Pro I/Os, supporting a wide variety of single-ended, differential,and voltage-referenced I/O standards.

Each I/O module contains several input, output, and enable registers. These registers allow theimplementation of the following applications:

•••

Single-Data-Rate (SDR) applications

Double-Data-Rate (DDR) applications—DDR LVDS I/O for chip-to-chip communicationsFusion banks support LVPECL, LVDS, BLVDS, and M-LVDS with 20 multi-drop points.

VersaTiles

The Fusion core consists of VersaTiles, which are also used in the successful Actel ProASIC3 family.The Fusion VersaTile supports the following:

•••

All 3-input logic functions—LUT-3 equivalent Latch with clear or set

D-flip-flop with clear or set and optional enable

Refer to Figure1-2 for the VersaTile configuration arrangement.

LUT-3 EquivalentX1X2X3D-Flip-Flop with Clear or SetDataCLKCLRYEnable D-Flip-Flop with Clear or SetDataCLKEnableCLRYLUT-3YD-FFD-FFEFigure 1-2•VersaTile Configurations

Preliminary v0.41-9

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Fusion Device Family Overview