Configuration and method for testing a delay chain

专利名称：Configuration and method for testing a

delay chain within a microprocessor clockgenerator

发明人：Brian D. McMinn,Stephen C. Horne申请号：US08/212037申请日：19940311公开号：US05430394A公开日：19950704

摘要：A test configuration is provided which allows a plurality of variable delay unitswithin a delay chain of a microprocessor clock generator to be compared with respect toone another. During normal operation, a set of multiplexers interposed within the delaychain are configured such that the plurality of variable delay units are electrically coupledin series with respect to one another. An external command signal may be provided tothe microprocessor to initiate a test operation in which the variable delay units are testedfor possible defects. During the test operation, a control unit selects the multiplexerssuch that the four delay units are electrically separated from one another. A commontest signal is then driven through two or more of the variable delay units simultaneously,and a compare circuit coupled to the output of each variable delay unit determineswhether a transition in the common pulse signal propagated through each variable delayunit at essentially the same time. If no manufacturing defects are present, the fouroutputs of the variable delay units should be virtually indistinguishable from one another.The results of the compare operation may be driven on external pins of the

microprocessor or may be processed internally within the microprocessor. Similar tests

may be conducted throughout the entire operating range of the variable delay units.

申请人：ADVANCED MICRO DEVICES, INC.

代理机构：Conley, Rose & Tayon

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