PHASE LOCKED LOOP WITH PHASE CORRECTION IN THE FEE

专利名称：PHASE LOCKED LOOP WITH PHASE

CORRECTION IN THE FEEDBACK LOOP

发明人：ZHANG, Gang申请号：EP12751182.2申请日：20120801公开号：EP2740219B1公开日：20150520

摘要：A frequency synthesizer circuit is disclosed. The frequency synthesizer circuitincludes a comparator circuit coupled to a reference clock and a phase-corrected outputsignal. The frequency synthesizer circuit also includes a loop filter coupled to thecomparator circuit. The frequency synthesizer circuit also includes an oscillator coupledto the loop filter. The frequency synthesizer circuit also includes a fractional dividercoupled to an output of the oscillator. The frequency synthesizer circuit also includesphase correction circuitry that corrects a phase of an output of the fractional divider toproduce the phase-corrected output signal.

申请人：QUALCOMM INC

地址：US

国籍：US

代理机构：Carstens, Dirk Wilhelm

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