Semiconductor memory device and refresh period con

专利名称：Semiconductor memory device and refresh

period controlling method

发明人：Yutaka Ito,Takeshi Hashimoto申请号：US11152762申请日：20050615公开号：US07493531B2公开日：20090217

专利附图：

摘要：Disclosed is a memory device including an error rate measurement circuit and acontrol circuit. The error rate measurement circuit, carrying a BIST circuit, reads out andwrites data for an area for monitor bits every refresh period to detect an error rate

(error count) with the refresh period. The control circuit performs control for elongatingand shortening the refresh period so that a desired error rate will be achieved. The BISTcircuit issues an internal command and an internal address and drives the DRAM frominside. The BIST circuit writes and reads out desired data, compares the monitor bits toexpected values (error decision) and counts the errors.

申请人：Yutaka Ito,Takeshi Hashimoto

地址：Tokyo JP,Tokyo JP

国籍：JP,JP

代理机构：Foley & Lardner LLP

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