Master slice type integrated circuit system having

专利名称：Master slice type integrated circuit system

having block areas optimized based onfunction

发明人：Masao Mizuno申请号：US08/283766申请日：19940801公开号：US05796129A公开日：19980818

摘要：A master slice type gate array has a plurality of block areas. Each block areaincludes a plurality of basic cells arranged in a matrix. Different block areas havetransistors with different channel widths. Within each of the block areas, a plurality ofbasic cells are connected to one another through a wiring layer to form function cells.First layer wirings for the function cells are completed within an area between rows ofpower source wirings Vdd and Vss of the first layer in the transverse direction. Contactsfor connecting the sources and drains of P- and N- channel type MOS transistors to thefirst layer wirings are arranged in rows. Even if the channel widths are changed, theposition of the contacts for forming the function cells and the wiring pattern remainunchanged for every block. Therefore, the master slice type gate array can be optimizedfor various performance parameters such as speed, integration, power consumption andother factors. As a result, the number of steps required to arrange the function cells canbe reduced.

申请人：SEIKO EPSON CORP.

代理机构：Oliff & Berridge, PLC

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