XC167CI
16-Bit Single-Chip MicrocontrollerPreliminary
Microcontrollers
Never stop thinking.
Edition 2003-06
Published by Infineon Technologies AG,St.-Martin-Strasse 53,
D-81541 München, Germany
© Infineon Technologies AG 2003.All Rights Reserved.Attention please!
The information herein is given to describe certain components and shall not be considered as warranted characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein.Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list).Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
Data Sheet, V1.1, Jun. 2003
XC167CI
Preliminary
16-Bit Single-Chip Microcontroller
limMicrocontrollers
PNever stop thinking.
re inaryXC167
Preliminary
Revision History:Previous Version:Page11616, 493549515253ff5758596267
2003-062002-10
V1.0
V1.1
Subjects (major changes since last revision)AD conversion times updated
Reference to internal pullup resistor removedRSTIN note addedSentence added about the RTC clock source.Digital supply voltage range for IO pads improvedNote 2 addedNote 3 changed
Specification of Sleep and Power-down mode supply current improvedConversion time formulas improvedNote 4 changed
Converter timing example improvedNote 1 addedTable 19 changed
Controller Area Network (CAN): License of Robert Bosch GmbH
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Any information within this document that you feel is wrong, unclear or missing at all?Your feedback will help us to continuously improve the quality of this document.Please send your proposal (including a reference to this document) to:mcdocu.comments@infineon.com
Preliminary
16-Bit Single-Chip MicrocontrollerXC166 FamilyXC167
XC167
1Summary of Features
•High Performance 16-bit CPU with 5-Stage Pipeline
–25 ns Instruction Cycle Time at 40MHz CPU Clock (Single-Cycle Execution)
–1-Cycle Multiplication (16 × 16 bit), Background Division (32 / 16 bit) in 21 Cycles–1-Cycle Multiply-and-Accumulate (MAC) Instructions–Enhanced Boolean Bit Manipulation Facilities–Zero-Cycle Jump Execution
–Additional Instructions to Support HLL and Operating Systems–Register-Based Design with Multiple Variable Register Banks
–Fast Context Switching Support with Two Additional Local Register Banks–16 Mbytes Total Linear Address Space for Code and Data
–1024 Bytes On-Chip Special Function Register Area (C166Family Compatible)•16-Priority-Level Interrupt System with 77 Sources, Sample-Rate down to 50 ns•8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via
Peripheral Event Controller (PEC), 24-Bit Pointers Cover Total Address Space•Clock Generation via on-chip PLL (factors 1:0.15 … 1:10), orvia Prescaler (factors 1:1 … 60:1)•On-Chip Memory Modules
–2 Kbytes On-Chip Dual-Port RAM (DPRAM)–4 Kbytes On-Chip Data SRAM (DSRAM)
–2 Kbytes On-Chip Program/Data SRAM (PSRAM)
–128 Kbytes On-Chip Program Memory (Flash Memory)•On-Chip Peripheral Modules
–16-Channel A/D Converter with Programmable Resolution (10-bit or 8-bit) andConversion Time (down to 2.55 µs or 2.15 µs)
–Two 16-Channel General Purpose Capture/Compare Units (32 Input/Output Pins)–Capture/Compare Unit for flexible PWM Signal Generation (CAPCOM6)(3/6 Capture/Compare Channels and 1 Compare Channel)–Multi-Functional General Purpose Timer Unit with 5 Timers–Two Synchronous/Asynchronous Serial Channels (USARTs)–Two High-Speed-Synchronous Serial Channels
–On-Chip TwinCAN Interface (Rev. 2.0B active) with 32 Message Objects(Full CAN/Basic CAN) on Two CAN Nodes, and Gateway Functionality
–IIC Bus Interface (10-bit addressing, 400 kbit/s) with 3 Channels (multiplexed)–On-Chip Real Time Clock, Driven by Dedicated Oscillator
•Idle, Sleep, and Power Down Modes with Flexible Power Management•Programmable Watchdog Timer and Oscillator Watchdog
Data Sheet
1
V1.1, 2003-06
XC167Derivatives
Preliminary
Summary of Features
•Up to 12 Mbytes External Address Space for Code and Data
–Programmable External Bus Characteristics for Different Address Ranges–Multiplexed or Demultiplexed External Address/Data Buses–Selectable Address Bus Width–16-Bit or 8-Bit Data Bus Width
–Five Programmable Chip-Select Signals
–Hold- and Hold-Acknowledge Bus Arbitration Support•Up to 103 General Purpose I/O Lines,
partly with Selectable Input Thresholds and Hysteresis•On-Chip Bootstrap Loader
•Supported by a Large Range of Development Tools like C-Compilers,
Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers,Simulators, Logic Analyzer Disassemblers, Programming Boards•On-Chip Debug Support via JTAG Interface
•144-Pin TQFP Package, 0.5mm (19.7 mil) pitchOrdering Information
The ordering code for Infineon microcontrollers provides an exact reference to therequired product. This ordering code identifies:
•the derivative itself, i.e. its function set, the temperature range, and the supply voltage•the package and the type of delivery.
For the available ordering codes for the XC167 please refer to the “Product CatalogMicrocontrollers”, which summarizes all available microcontroller variants.
Note:The ordering codes for Mask-ROM versions are defined for each product afterverification of the respective ROM code.This document describes several derivatives of the XC167 group. Table1 enumeratesthese derivatives and summarizes the differences. As this document refers to all of thesederivatives, some descriptions may not apply to a specific product.
For simplicity all versions are referred to by the term XC167 throughout this document.
Data Sheet2V1.1, 2003-06
XC167Derivatives
PreliminaryTable1Derivative1)SAK-XC167CI-16F40F,SAK-XC167CI-16F20F
XC167 Derivative Synopsis
Program Memory128 Kbytes Flash
On-Chip RAM2 Kbytes DPRAM,4 Kbytes DSRAM,2 Kbytes PSRAM2 Kbytes DPRAM,4 Kbytes DSRAM,2 Kbytes PSRAM2 Kbytes DPRAM,4 Kbytes DSRAM,2 Kbytes PSRAM
InterfacesASC0, ASC1,SSC0, SSC1,CAN0, CAN1,IIC
ASC0, ASC1,SSC0, SSC1,CAN0, CAN1,IIC
ASC0, ASC1,SSC0, SSC1,CAN0, CAN1,IIC
Summary of Features
SAF-XC167CI-16F40F,SAF-XC167CI-16F20F
128 Kbytes Flash
SAB-XC167CI-16F40F,SAB-XC167CI-16F20F(on request)
1)
128 Kbytes Flash
This Data Sheet is valid for devices starting with and including design step AD.
Data Sheet3V1.1, 2003-06
XC167Derivatives
Preliminary
General Device Information
2
2.1
General Device Information
Introduction
The XC167 derivatives are high-performance members of the Infineon XC166Family offull featured single-chip CMOS microcontrollers. These devices extend the functionalityand performance of the C166Family in terms of instructions (MAC unit), peripherals, andspeed. They combine high CPU performance (up to 40 million instructions per second)with high peripheral functionality and enhanced IO-capabilities. They also provide clockgeneration via PLL and various on-chip memory modules such as program Flash,program RAM, and data RAM.
VAREFVDDI/P
VAGNDVSSI/P
XTAL1
XTAL2XTAL3XTAL4NMIRSTINRSTOUTEAPort 206 bit
READYALERDWR/WRLPORT016 bitPORT116 bitPort 28 bit
XC167
Port 315 bitPort 48 bitPort 68 bitPort 74 bitPort 96 bit
Port 516 bit
TRSTJTAGDebug
5 bit2 bit
Figure1Logic Symbol
Data Sheet4V1.1, 2003-06
XC167Derivatives
Preliminary
General Device Information
2.2Pin Configuration and Definition
The pins of the XC167 are described in detail in Table2, including all their alternatefunctions. Figure2 summarizes all pins in a condensed way, showing their location onthe 4 sides of the package. E*) and C*) mark pins to be used as alternate externalinterrupt inputs, C*) marks pins that can have CAN interface lines assigned to them.
BRKINBRKOUTRSTINXTAL4XTAL3VSSIXTAL1XTAL2VSSIVDDIP1H.7/A15/CC27IOP1H.6/A14/CC26IOP1H.5/A13/CC25IOP1H.4/A12/CC24IOP1H.3/A11/SCLK1/E*)P1H.2/A10/C6P2/MTSR1P1H.1/A9/C6P1/MRST1P1H.0/A8/C6P0/CC23/E*)VSSPVDDPP1L.7/A7/CTRAP/CC22P1L.6/A6/COUT63P1L.5/A5/COUT62P1L.4/A4/CC62P1L.3/A3/COUT61P1L.2/A2/CC61P1L.1/A1/COUT60P1L.0/A0/CC60P0H.7/AD15P0H.6/AD14P0H.5/AD13P0H.4/AD12P0H.3/AD11P0H.2/AD10NCNC123456789101112131415161718192021222324252627282930313233343536
144143142141140139138137136135134133132131130129128127126125124123122121120119118117116115114113112111110109108107106105104103102101100999897969594939291908988878685848382818079787776757473
NCNCP20.12/RSTOUTNMIVSSPVDDP
P6.0/CS0/CC0IOP6.1/CS1/CC1IOP6.2/CS2/CC2IOP6.3/CS3/CC3IOP6.4/CS4/CC4IOP6.5/HOLD/CC5IOP6.6/HLDA/CC6IOP6.7/BREQ/CC7IOP7.4/CC28IO/C*)P7.5/CC29IO/C*)P7.6/CC30IO/C*)P7.7/CC31IO/C*)
VSSPVDDP
P9.0/SDA0/CC16Io/C*)P9.1/SCL0/CC17Io/C*)P9.2/SDA1/CC18Io/C*)P9.3/SCL1/CC19Io/C*)P9.4/SDA2/CC20IOP9.5/SCL2/CC21IO
VSSPVDDPP5.0/AN0P5.1/AN1P5.2/AN2P5.3/AN3P5.4/AN4P5.5/AN5
P5.10/AN10/T6EUDP5.11/AN11/T5EUD
XC167
NCNC
P0H.1/AD9P0H.0/AD8VSSPVDDP
P0L.7/AD7P0L.6/AD6P0L.5/AD5P0L.4/AD4P0L.3/AD3P0L.2/AD2P0L.1/AD1P0L.0/AD0P20.5/EAP20.4/ALEP20.2/READYP20.1/WR/WRLP20.0/RDVSSPVDDP
P4.7/A23/C*)P4.6/A22/C*)P4.5/A21/C*)P4.4/A20/C*)P4.3/A19P4.2/A18P4.1/A17P4.0/A16VSSIVDDI
P3.15/CLKOUT/FOP3.13/SCLK0/E*)P3.12/BHE/WRH/TMS/E*)TDO
Figure2
Data Sheet
Pin Configuration (top view)
5
V1.1, 2003-06
P5.8/AN8P5.9/AN9P5.6/AN6P5.7/AN7VAREFVAGNDP5.12/AN12/T6INP5.13/AN13/T5INP5.14/AN14T4EUDP5.15/AN15/T2EUDVSSIVDDIP2.8/CC8IO/EX0INP2.9/CC9IO/EX1INP2.10/CC10IO/EX2INP2.11/CC11IO/EX3INP2.12/CC12IO/EX4INP2.13/CC13IO/EX5INP2.14/CC14IO/EX6INP2.15/CC15IO/EX7IN/T7INTRSTVDDPP3.0/T0IN/TxD1/E*)P3.1/T6OUT/RxD1/E*)P3.2/CAPINP3.3/T3OUTP3.4/T3EUDP3.5/T4INP3.6/T3INP3.7/T2INP3.8/MRST0P3.9/MTSR0P3.10/TxD0/E*)P3.11/RxD0/E*)TCKTDI373839404142434445464748495051525354555657585960616263646566676869707172XC167Derivatives
PreliminaryTable2
Pin Definitions and Functions
InputOutp.IOI
Function
For details, please refer to the description of P20.
Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to vector to the NMI trap routine. When the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the XC167 into power down mode. If NMI is high, when PWRDN is executed, the part will continue to run in normal mode.
If not used, pin NMI should be pulled high externally.Port6 is an 8-bit bidirectional I/O port. Each pin can be programmed for input (output driver in high-impedance state) or output (configurable as push/pull or open drain driver). The input threshold of Port6 is selectable (standard or special).
The Port6 pins also serve for alternate functions:
Chip Select 0 Output,CS0CC0IOCAPCOM1: CC0 Capture Inp./Compare OutputCS1Chip Select 1 Output,CC1IOCAPCOM1: CC1 Capture Inp./Compare OutputCS2Chip Select 2 Output,CC2IOCAPCOM1: CC2 Capture Inp./Compare OutputCS3Chip Select 3 Output,CC3IOCAPCOM1: CC3 Capture Inp./Compare OutputCS4Chip Select 4 Output,CC4IOCAPCOM1: CC4 Capture Inp./Compare OutputHOLDExternal Master Hold Request Input,CC5IOCAPCOM1: CC5 Capture Inp./Compare OutputHLDAHold Acknowledge Output (master mode)
or Input (slave mode),
CC6IOCAPCOM1: CC6 Capture Inp./Compare OutputBREQBus Request Output,CC7IOCAPCOM1: CC7 Capture Inp./Compare Output
General Device Information
SymbolPin
Num.P20.123NMI4
P6IO
P6.0P6.1P6.2P6.3P6.4P6.5P6.6
78910111213OIOOIOOIOOIOOIOIIOI/OIOOIO
P6.714
Data Sheet6V1.1, 2003-06
XC167Derivatives
PreliminaryTable2
Pin Definitions and Functions (cont’d)
InputOutp.IO
Function
Port7 is a 4-bit bidirectional I/O port. Each pin can be programmed for input (output driver in high-impedance state) or output (configurable as push/pull or open drain driver). The input threshold of Port7 is selectable (standard or special).
Port7 pins provide inputs/outputs for CAPCOM2 and serial interface lines.1)CC28IOCAPCOM2: CC28 Capture Inp./Compare Outp.,CAN2_RxDCAN Node 2 Receive Data Input,EX7INFast External Interrupt 7 Input (alternate pin B)CC29IOCAPCOM2: CC29 Capture Inp./Compare Outp.,CAN2_TxDCAN Node 2 Transmit Data Output,EX6INFast External Interrupt 6 Input (alternate pin B)CC30IOCAPCOM2: CC30 Capture Inp./Compare Outp.,CAN1_RxDCAN Node 1 Receive Data Input,EX7INFast External Interrupt 7 Input (alternate pin A)CC31IOCAPCOM2: CC31 Capture Inp./Compare Outp.,CAN1_TxDCAN Node 1 Transmit Data Output,EX6INFast External Interrupt 6 Input (alternate pin A)
General Device Information
SymbolPin
Num.P7
P7.415
P7.516
P7.617
P7.718
I/OIII/OOII/OIII/OOI
Data Sheet7V1.1, 2003-06
XC167Derivatives
PreliminaryTable2
Pin Definitions and Functions (cont’d)
InputOutp.IO
Function
Port9 is a 6-bit bidirectional I/O port. Each pin can be programmed for input (output driver in high-impedance state) or output (configurable as push/pull or open drain driver). The input threshold of Port9 is selectable (standard or special).
The following Port9 pins also serve for alternate functions:1)CC16IOCAPCOM2: CC16 Capture Inp./Compare Outp.,CAN2_RxDCAN Node 2 Receive Data Input,SDA0IIC Bus Data Line 0CC17IOCAPCOM2: CC17 Capture Inp./Compare Outp.,CAN2_TxDCAN Node 2 Transmit Data Output,SCL0IIC Bus Clock Line 0CC18IOCAPCOM2: CC18 Capture Inp./Compare Outp.,CAN1_RxDCAN Node 1 Receive Data Input,SDA1IIC Bus Data Line 1CC19IOCAPCOM2: CC19 Capture Inp./Compare Outp.,CAN1_TxDCAN Node 1 Transmit Data Output,SCL1IIC Bus Clock Line 1CC20IOCAPCOM2: CC20 Capture Inp./Compare Outp.,SDA2IIC Bus Data Line 2CC21IOCAPCOM2: CC21 Capture Inp./Compare Outp.,SCL2IIC Bus Clock Line 2
General Device Information
SymbolPin
Num.P9
P9.021
P9.122
P9.223
P9.324
P9.4P9.5
2526
I/OII/OI/OOI/OI/OII/OI/OOI/OI/OI/OI/OI/O
Data Sheet8V1.1, 2003-06
XC167Derivatives
PreliminaryTable2
Pin Definitions and Functions (cont’d)
InputOutp.I
Function
Port5 is a 16-bit input-only port.
The pins of Port5 also serve as analog input channels for the A/D converter, or they serve as timer inputs:AN0AN1AN2AN3AN4AN5AN10,T6EUDGPT2 Timer T6 Ext. Up/Down Ctrl. Inp.AN11,T5EUDGPT2 Timer T5 Ext. Up/Down Ctrl. Inp.AN8AN9AN6AN7AN12,T6INGPT2 Timer T6 Count/Gate InputAN13,T5INGPT2 Timer T5 Count/Gate InputAN14,T4EUDGPT1 Timer T4 Ext. Up/Down Ctrl. Inp.AN15,T2EUDGPT1 Timer T2 Ext. Up/Down Ctrl. Inp.
General Device Information
SymbolPin
Num.P5
P5.0P5.1P5.2P5.3P5.4P5.5P5.10P5.11P5.8P5.9P5.6P5.7P5.12P5.13P5.14P5.1529303132333435363738394043444546IIIIIIIIIIIIIIII
Data Sheet9V1.1, 2003-06
XC167Derivatives
PreliminaryTable2
Pin Definitions and Functions (cont’d)
InputOutp.IO
Function
Port2 is an 8-bit bidirectional I/O port. Each pin can be programmed for input (output driver in high-impedance state) or output (configurable as push/pull or open drain driver). The input threshold of Port2 is selectable (standard or special).
The following Port2 pins also serve for alternate functions:CC8IOCAPCOM1: CC8 Capture Inp./Compare Output,EX0INFast External Interrupt 0 Input (default pin)CC9IOCAPCOM1: CC9 Capture Inp./Compare Output,EX1INFast External Interrupt 1 Input (default pin)CC10IOCAPCOM1: CC10 Capture Inp./Compare Outp.,EX2INFast External Interrupt 2 Input (default pin)CC11IOCAPCOM1: CC11 Capture Inp./Compare Outp.,EX3INFast External Interrupt 3 Input (default pin)CC12IOCAPCOM1: CC12 Capture Inp./Compare Outp.,EX4INFast External Interrupt 4 Input (default pin)CC13IOCAPCOM1: CC13 Capture Inp./Compare Outp.,EX5INFast External Interrupt 5 Input (default pin)CC14IOCAPCOM1: CC14 Capture Inp./Compare Outp.,EX6INFast External Interrupt 6 Input (default pin)CC15IOCAPCOM1: CC15 Capture Inp./Compare Outp.,EX7INFast External Interrupt 7 Input (default pin),T7INCAPCOM2: Timer T7 Count InputTest-System Reset Input. A high level at this pin activates the XC167’s debug system.
General Device Information
SymbolPin
Num.P2
P2.8P2.9P2.10P2.11P2.12P2.13P2.14P2.15
4950515253545556
I/OII/OII/OII/OII/OII/OII/OII/OIII
TRST57
Note:For normal system operation, pin TRST should beheld low.Data Sheet10V1.1, 2003-06
XC167Derivatives
PreliminaryTable2
Pin Definitions and Functions (cont’d)
InputOutp.IO
Function
Port3 is a 15-bit bidirectional I/O port. Each pin can be programmed for input (output driver in high-impedance state) or output (configurable as push/pull or open drain driver). The input threshold of Port3 is selectable (standard or special).
The following Port3 pins also serve for alternate functions:T0INCAPCOM1 Timer T0 Count Input,TxD1ASC1 Clock/Data Output (Async./Sync),EX1INFast External Interrupt 1 Input (alternate pin B)T6OUTGPT2 Timer T6 Toggle Latch Output,RxD1ASC1 Data Input (Async.) or Inp./Outp. (Sync.),EX1INFast External Interrupt 1 Input (alternate pin A)CAPINGPT2 Register CAPREL Capture InputT3OUTGPT1 Timer T3 Toggle Latch OutputT3EUDGPT1 Timer T3 External Up/Down Control InputT4INGPT1 Timer T4 Count/Gate/Reload/Capture InpT3INGPT1 Timer T3 Count/Gate InputT2INGPT1 Timer T2 Count/Gate/Reload/Capture InpMRST0SSC0 Master-Receive/Slave-Transmit In/Out.MTSR0SSC0 Master-Transmit/Slave-Receive Out/In.TxD0ASC0 Clock/Data Output (Async./Sync.),EX2INFast External Interrupt 2 Input (alternate pin B)RxD0ASC0 Data Input (Async.) or Inp./Outp. (Sync.),EX2INFast External Interrupt 2 Input (alternate pin A)BHEExternal Memory High Byte Enable Signal,WRHExternal Memory High Byte Write Strobe,EX3INFast External Interrupt 3 Input (alternate pin B)SCLK0SSC0 Master Clock Output / Slave Clock Input.,EX3INFast External Interrupt 3 Input (alternate pin A)CLKOUTMaster Clock Output,FOUTProgrammable Frequency OutputDebug System: JTAG Clock InputDebug System: JTAG Data InDebug System: JTAG Data Out
Debug System: JTAG Test Mode Selection
General Device Information
SymbolPin
Num.P3
P3.059
P3.160
P3.2P3.3P3.4P3.5P3.6P3.7P3.8P3.9P3.10P3.11P3.12
6162636465666768697075
P3.13P3.15TCKTDITDOTMS
767771727374
IOIOI/OIIOIIIII/OI/OOII/OIOOII/OIOOIIOI
Data Sheet11V1.1, 2003-06
XC167Derivatives
PreliminaryTable2
Pin Definitions and Functions (cont’d)
InputOutp.IO
Function
Port4 is an 8-bit bidirectional I/O port. Each pin can be programmed for input (output driver in high-impedance state) or output (configurable as push/pull or open drain driver). The input threshold of Port4 is selectable (standard or special).
Port4 can be used to output the segment address lines, the optional chip select lines, and for serial interface lines:1)A16Least Significant Segment Address LineA17Segment Address LineA18Segment Address LineA19Segment Address LineA20Segment Address Line,
CAN2_RxDCAN Node 2 Receive Data Input,EX5INFast External Interrupt 5 Input (alternate pin B)A21Segment Address Line,
CAN1_RxDCAN Node 1 Receive Data Input,EX4INFast External Interrupt 4 Input (alternate pin B)A22Segment Address Line,
CAN1_TxDCAN Node 1 Transmit Data Output,EX5INFast External Interrupt 5 Input (alternate pin A)A23Most Significant Segment Address Line,CAN1_RxDCAN Node 1 Receive Data Input,CAN2_TxDCAN Node 2 Transmit Data Output,EX4INFast External Interrupt 4 Input (alternate pin A)
General Device Information
SymbolPin
Num.P4
P4.0P4.1P4.2P4.3P4.48081828384
P4.585
P4.686
P4.787
OOOOOIIOIIOOIOIOI
Data Sheet12V1.1, 2003-06
XC167Derivatives
PreliminaryTable2
Pin Definitions and Functions (cont’d)
InputOutp.IO
Function
Port20 is a 6-bit bidirectional I/O port. Each pin can be programmed for input (output driver in high-impedance
state) or output. The input threshold of Port20 is selectable (standard or special).
The following Port20 pins also serve for alternate functions:
External Memory Read Strobe, activated forRDevery external instruction or data read access.
WR/WRLExternal Memory Write Strobe.
In WR-mode this pin is activated for every external data write access.
In WRL-mode this pin is activated for low byte data write accesses on a 16-bit bus, and for every data write access on an 8-bit bus.
READYREADY Input. When the READY function is
enabled, memory cycle time waitstates can be forced via this pin during an external access.
ALEAddress Latch Enable Output.
Can be used for latching the address into external memory or an address latch in the multiplexed bus modes.
EAExternal Access Enable pin.
A low level at this pin during and after Reset forces the XC167 to latch the configuration from PORT0 and pin RD, and to begin instruction execution out of external memory.
A high level forces the XC167 to latch the configuration from pins RD, ALE, and WR, and to begin instruction execution out of the internal program memory. \"ROMless\" versions must have this pin tied to ‘0’.
RSTOUTInternal Reset Indication Output.
Is activated asynchronously with an external hardware reset. It may also be activated (selectable) synchronously with an internal software or watchdog reset.
Is deactivated upon the execution of the EINIT instruction, optionally at the end of reset, or at any time (before EINIT) via user software.
General Device Information
SymbolPin
Num.P20
P20.0P20.1
9091
OO
P20.292I
P20.493O
P20.594I
P20.123O
Note:Port20 pins may input configuration values (see EA).Data Sheet
13
V1.1, 2003-06
XC167Derivatives
PreliminaryTable2
Pin Definitions and Functions (cont’d)
InputOutp.IO
Function
PORT0 consists of the two 8-bit bidirectional I/O ports P0L and P0H. Each pin can be programmed for input (output driver in high-impedance state) or output.
In case of an external bus configuration, PORT0 serves as the address (A) and address/data (AD) bus in multiplexed bus modes and as the data (D) bus in demultiplexed bus modes.
Demultiplexed bus modes:Data Path Width:8-bit16-bitP0L.0 – P0L.7:D0 – D7D0 - D7P0H.0 – P0H.7:I/OD8 - D15Multiplexed bus modes:Data Path Width:8-bit16-bitP0L.0 – P0L.7:AD0 – AD7AD0 - AD7P0H.0 – P0H.7:A8 - A15AD8 - AD15
General Device Information
SymbolPin
Num.PORT0
P0L.0-795 -
102
P0H.0-1105 -
106
P0H.2-7111 -
116
Note:At the end of an external reset (EA = 0) PORT0 alsomay input configuration values.PORT1
IO
PORT1 consists of the two 8-bit bidirectional I/O ports P1L and P1H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. PORT1 is used as the 16-bit address bus (A) in demultiplexed bus modes (also after switching from a demultiplexed to a multiplexed bus mode).The following PORT1 pins also serve for alt. functions:CC60CAPCOM6: Input / Output of Channel 0COUT60CAPCOM6: Output of Channel 0CC61CAPCOM6: Input / Output of Channel 1COUT61CAPCOM6: Output of Channel 1CC62CAPCOM6: Input / Output of Channel 2COUT62CAPCOM6: Output of Channel 2COUT63Output of 10-bit Compare Channel
CAPCOM6: Trap InputCTRAPCTRAP is an input pin with an internal pullup resistor. A low level on this pin switches the CAPCOM6 compare outputs to the logic level defined by software (if enabled).CC22IOCAPCOM2: CC22 Capture Inp./Compare Outp.…continued…
P1L.0
P1L.1P1L.2P1L.3P1L.4P1L.5P1L.6P1L.7117118119120121122123124I/OOI/OOI/OOOI
I/O
P1H
…
Data Sheet14V1.1, 2003-06
XC167Derivatives
PreliminaryTable2
Pin Definitions and Functions (cont’d)
InputOutp.IOIII/OII/OII/OI/OII/OI/OI/OI/OOI
Function…continued…CC6POS0EX0INCC23IOCC6POS1MRST1CC6POS2MTSR1SCLK1EX0INCC24IOCC25IOCC26IOCC27IOXTAL2:XTAL1:
CAPCOM6: Position 0 Input,
Fast External Interrupt 0 Input (alternate pin B),CAPCOM2: CC23 Capture Inp./Compare Outp.CAPCOM6: Position 1 Input,
SSC1 Master-Receive/Slave-Transmit In/Out.CAPCOM6: Position 2 Input,
SSC1 Master-Transmit/Slave-Receive Out/Inp.SSC1 Master Clock Output / Slave Clock Input,Fast External Interrupt 0 Input (alternate pin A)CAPCOM2: CC24 Capture Inp./Compare Outp.CAPCOM2: CC25 Capture Inp./Compare Outp.CAPCOM2: CC26 Capture Inp./Compare Outp.CAPCOM2: CC27 Capture Inp./Compare Outp.
General Device Information
SymbolPin
Num.PORT1(cont’d)
P1H.0127
P1H.1P1H.2P1H.3P1H.4P1H.5P1H.6P1H.7XTAL2XTAL1
128129130131132133134137138
Output of the main oscillator amplifier circuitInput to the main oscillator amplifier and inputto the internal clock generator
To clock the device from an external source, drive XTAL1, while leaving XTAL2 unconnected. Minimum and maximum high/low and rise/fall times specified in the AC Characteristics must be observed.XTAL3:XTAL4:
Input to the auxiliary (32-kHz) oscillator amplifierOutput of the auxiliary (32-kHz) oscillatoramplifier circuit
To clock the device from an external source, drive XTAL3, while leaving XTAL4 unconnected. Minimum and maximum high/low and rise/fall times specified in the AC Characteristics must be observed.
XTAL3XTAL4140141IO
Data Sheet15V1.1, 2003-06
XC167Derivatives
PreliminaryTable2
Pin Definitions and Functions (cont’d)
InputOutp.I
Function
Reset Input with Schmitt-Trigger characteristics. A low level at this pin while the oscillator is running resets the XC167.A spike filter suppresses input pulses <10ns. Input pulses >100ns safely pass the filter. The minimum duration for a safe recognition should be 100ns + 2 CPU clock cycles.
General Device Information
SymbolPin
Num.RSTIN142
Note:The reset duration must be sufficient to let thehardware configuration signals settle.External circuitry must guarantee low level at theRSTIN pin at least until both power supply voltageshave reached the operating range.BRK OUTBRKINNC
1431441, 2, 107 - 1104142
OI-Debug System: Break OutDebug System: Break In
No connection.
It is recommended not to connect these pins to the PCB.Reference voltage for the A/D converter.Reference ground for the A/D converter.Digital Core Supply Voltage (On-Chip Modules):+2.5 V during normal operation and idle mode.Please refer to the Operating ConditionsDigital Pad Supply Voltage (Pin Output Drivers):+5 V during normal operation and idle mode.Please refer to the Operating Conditions
VAREFVAGNDVDDIVDDP
--
48, 78, -1356, 20, -28, 58, 88, 103, 12547, 79, -136, 1395, 19, -27, 89, 104, 126
VSSIVSSP
Digital Ground.
Connect decoupling capacitors to adjacent VDD/VSS pin pairs as close as possible to the pins.
All VSS pins must be connected to the ground-line or ground-plane.
1)
The CAN interface lines are assigned to ports P4, P7, and P9 under software control.
Data Sheet16V1.1, 2003-06
XC167Derivatives
Preliminary
Functional Description
3Functional Description
The architecture of the XC167 combines advantages of RISC, CISC, and DSPprocessors with an advanced peripheral subsystem in a very well-balanced way. Inaddition, the on-chip memory blocks allow the design of compact systems-on-silicon withmaximum performance (computing, control, communication).
The on-chip memory blocks (program code-memory and SRAM, dual-port RAM, dataSRAM) and the set of generic peripherals are connected to the CPU via separate buses.Another bus, the LXBus, connects additional on-chip resoures as well as externalresources (see Figure3).
This bus structure enhances the overall system performance by enabling the concurrentoperation of several subsystems of the XC167.
The following block diagram gives an overview of the different on-chip components andof the advanced, high bandwidth internal bus structure of the XC167.
PSRAMProgMemPMUDPRAMDSRAMEBCDMUFlash128 KBytesCPUC166SV2-CoreXBUS ControlExternal BusControlOCDSDebug SupportXTALOsc / PLLClock GenerationRTCWDTInterrupt & PECInterrupt BusPeripheral Data BusADC8/10-Bit16ChannelsGPTASC0ASC1SSC0SSC1CC1T2T3T4T5T6BRGenPort 648BRGenPort 516BRGenBRGenPort 315(USART)(USART)(SPI)(SPI)T0T1CC2T7T8IICCC6T12T13TwinCANABRGenPort 28PORT116PORT016BP 20Port 9P 766Port 48MCB04323_x7.vsdFigure3Block Diagram
Data Sheet17V1.1, 2003-06
XC167Derivatives
Preliminary
Functional Description
3.1Memory Subsystem and Organization
The memory space of the XC167 is configured in a VonNeumann architecture, whichmeans that all internal and external resources, such as code memory, data memory,registers and I/O ports, are organized within the same linear address space. Thiscommon memory space includes 16Mbytes and is arranged as 256segments of64Kbytes each, where each segment consists of four data pages of 16Kbytes each.The entire memory space can be accessed bytewise or wordwise. Portions of the on-chip DPRAM and the register spaces (E/SFR) have additionally been made directlybitaddressable.
The internal data memory areas and the Special Function Register areas (SFR andESFR) are mapped into segment0, the system segment.
The Program Management Unit (PMU) handles all code fetches and, therefore, controlsaccesses to the program memories, such as Flash memory and PSRAM.
The Data Management Unit (DMU) handles all data transfers and, therefore, controlsaccesses to the DSRAM and the on-chip peripherals.
Both units (PMU and DMU) are connected via the high-speed system bus to exchangedata. This is required if operands are read from program memory, code or data is writtento the PSRAM, code is fetched from external memory, or data is read from or written toexternal resources, including peripherals on the LXbus (such as TwinCAN). The systembus allows concurrent two-way communication for maximum transfer performance.128Kbytes of on-chip Flash memory store code or constant data. The on-chip Flashmemory is organized as four 8-Kbyte sectors, one 32-Kbyte sector, and one 64-Kbytesector. Each sector can be separately write protected1), erased and programmed (inblocks of 128 Bytes). The complete Flash area can be read-protected. A passwordsequence temporarily unlocks protected areas. The Flash module combines very fast64-bit one-cycle read accesses with protected and efficient writing algorithms forprogramming and erasing. Thus, program execution out of the internal Flash results inmaximum performance. Dynamic error correction provides extremely high read datasecurity for all read accesses.
Programming typically takes 2ms per 128-byte block (5ms max.), erasing a sectortypically takes 200ms (500ms max.).
2Kbytes of on-chip Program SRAM (PSRAM) are provided to store user code or data.The PSRAM is accessed via the PMU and is therefore optimized for code fetches.4Kbytes of on-chip Data SRAM (DSRAM) are provided as a storage for general userdata.The DSRAM is accessed via the DMU and is therefore optimized for data accesses.2Kbytes of on-chip Dual-Port RAM (DPRAM) are provided as a storage for userdefined variables, for the system stack, general purpose register banks. A register bankcan consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0, …, RL7, RH7)
1)
Each two 8-Kbyte sectors are combined for write-protection purposes.
Data Sheet18V1.1, 2003-06
XC167Derivatives
Preliminary
Functional Description
so-called General Purpose Registers (GPRs).
The upper 256 bytes of the DPRAM are directly bitaddressable. When used by a GPR,any location in the DPRAM is bitaddressable.
1024 bytes (2 × 512 bytes) of the address space are reserved for the Special FunctionRegister areas (SFR space and ESFR space). SFRs are wordwide registers which are
used for controlling and monitoring functions of the different on-chip units. Unused SFR
Family. Therefore, they shouldaddresses are reserved for future members of the XC166 either not be accessed, or written with zeros, to ensure upward compatibility.
In order to meet the needs of designs where more memory is required than is provided
on chip, up to 12Mbytes (approximately, see Table3) of external RAM and/or ROM canbe connected to the microcontroller. The External Bus Interface also provides access toexternal peripherals.Table3
XC167 Memory Map1)
Start Loc.FF’F000HF8’0000HE0’0800HE0’0000HC2’0000HC0’0000HBF’0000H40’0000H20’0800H20’0000H01’0000H00’8000H00’0000H
End Loc.FF’FFFFHFF’EFFFHF7’FFFFHE0’07FFHDF’FFFFHC1’FFFFHBF’FFFFHBE’FFFFH3F’FFFFH20’07FFH1F’FFFFH00’FFFFH00’7FFFH
Area Size2)4 Kbytes<0.5 Mbytes<1.5 Mbytes2 Kbytes<2 Mbytes128 Kbytes64 Kbytes<8Mbytes<2Mbytes2 Kbytes<2Mbytes32 Kbytes32 Kbytes
Minus segment0Partly usedMinus res. seg.Minus TwinCANNotes
3)Address AreaFlash register space
Reserved (Acc. trap)Reserved for PSRAMProgram SRAM
Minus Flash regsMinus PSRAMMaximumMinus Flash
Reserved for pr. mem.Program Flash
ReservedExternal memory areaExternal IO area4)TwinCAN registersExternal memory areaData RAMs and SFRsExternal memory area
1)2)3)4)
Accesses to the shaded areas generate external bus accesses.
The areas marked with “<“ are slightly smaller than indicated, see column “Notes”.Not defined register locations return a trap code.
Several pipeline optimizations are not active within the external IO area. This is necessary to control externalperipherals properly.
Data Sheet19V1.1, 2003-06
XC167Derivatives
Preliminary
Functional Description
3.2External Bus Controller
All of the external memory accesses are performed by a particular on-chip External BusController (EBC). It can be programmed either to Single Chip Mode when no externalmemory is required, or to one of four different external memory access modes1), whichare as follows:––––
16 … 24-bit Addresses, 16-bit Data, Demultiplexed16 … 24-bit Addresses, 16-bit Data, Multiplexed16 … 24-bit Addresses, 8-bit Data, Multiplexed16 … 24-bit Addresses, 8-bit Data, Demultiplexed
In the demultiplexed bus modes, addresses are output on PORT1 and data is input/output on PORT0 or P0L, respectively. In the multiplexed bus modes both addressesand data use PORT0 for input/output. The high order address (segment) lines usePort4. The number of active segment address lines is selectable, restricting the externaladdress space to 8Mbytes … 64Kbytes. This is required when interface lines areassigned to Port4.
Up to 5 external CS signals (4 windows plus default) can be generated in order to saveexternal glue logic. External modules can directly be connected to the common address/data bus and their individual select lines.
Access to very slow memories or modules with varying access times is supported via aparticular ‘Ready’ function. The active level of the control input signal is selectable.A HOLD/HLDA protocol is available for bus arbitration and allows the sharing of externalresources with other bus masters. The bus arbitration is enabled by software. Afterenabling, pins P6.7 … P6.5 (BREQ, HLDA, HOLD) are automatically controlled by theEBC. In Master Mode (default after reset) the HLDA pin is an output. In Slave Mode pinHLDA is switched to input. This allows the direct connection of the slave controller toanother master controller without glue logic.
Important timing characteristics of the external bus interface have been madeprogrammable (via registers TCONCSx/FCONCSx) to allow the user the adaption of awide range of different types of memories and external peripherals.
In addition, up to 4 independent address windows may be defined (via registersADDRSELx) which control the access to different resources with different buscharacteristics. These address windows are arranged hierarchically where window4overrides window3, and window2 overrides window1. All accesses to locations notcovered by these 4 address windows are controlled by TCONCS0/FCONCS0. Thecurrently active window can generate a chip select signal.
The external bus timing is related to the rising edge of the reference clock outputCLKOUT. The external bus protocol is compatible with that of the standard C166Family.
1)
Bus modes are switched dynamically if several address windows with different mode settings are used.
Data Sheet20V1.1, 2003-06
XC167Derivatives
Preliminary
Functional Description
The EBC also controls accesses to resources connected to the on-chip LXBus. TheLXBus is an internal representation of the external bus and allows accessing integratedperipherals and modules in the same way as external components.The TwinCAN module is connected and accessed via the LXBus.
3.3Central Processing Unit (CPU)
The main core of the CPU consists of a 5-stage execution pipeline with a 2-stageinstruction-fetch pipeline, a 16-bit arithmetic and logic unit (ALU), a 32-bit/40-bit multiplyand accumulate unit (MAC), a register-file providing three register banks, and dedicatedSFRs. The ALU features a multiply and divide unit, a bit-mask generator, and a barrelshifter.
System-Bus Internal Program MemoryPMUdata outaddressdata in CPUPrefetch UnitBranch Unit FIFO CSPIPVECSEGTFRCPUCON1CPUCON2CPUIDReturn Stack 2-Stage PrefetchPipeline5-Stage PipelineDPRAMIFUInjection/ExceptionHandlerSPSEGSPSTKOVSTKUNCPIPIPaddressIDX0IDX1QX0QX1QR0QR1DPP0DPP1DPP2DPP3+/-+/-MRWMCWMSWMALDivision UnitMultiply UnitADUBit-Mask-Gen.Barrel-ShifterR15R15R14R15R14R14GPRsGPRsGPRsR1R1R0R1R0R0R15R14GPRsMultiply Unit+/-MAHMDCPSWMDHZeros+/-MDLOnesR1R0RFdata inMACaddressdata outdata inALUdata inBufferWBdata outaddressdata outSRAMDMUPeripheral-BusSystem-BusFigure4CPU Block Diagram
Based on these hardware provisions, most of the XC167’s instructions can be executedin just one machine cycle which requires 25ns at 40MHz CPU clock. For example, shiftand rotate instructions are always processed during one machine cycle independent of
Data Sheet
21
V1.1, 2003-06
XC167Derivatives
Preliminary
Functional Description
the number of bits to be shifted. Also multiplication and most MAC instructions executein one single cycle. All multiple-cycle instructions have been optimized so that they canbe executed very fast as well: for example, a 32-/16-bit division is started within 4cycles,while the remaining 15cycles are executed in the background. Another pipelineoptimization, the branch target prediction, allows eliminating the execution time ofbranch instructions if the prediction was correct.
The CPU has a register context consisting of up to three register banks with 16 wordwideGPRs each at its disposal. One of these register banks is physically allocated within theon-chip DPRAM area. A Context Pointer (CP) register determines the base address ofthe active register bank to be accessed by the CPU at any time. The number of registerbanks is only restricted by the available internal RAM space. For easy parameterpassing, a register bank may overlap others.
A system stack of up to 32 Kwords is provided as a storage for temporary data. Thesystem stack can be allocated to any location within the address space (preferably in theon-chip RAM area), and it is accessed by the CPU via the stack pointer (SP) register.Two separate SFRs, STKOV and STKUN, are implicitly compared against the stackpointer value upon each stack access for the detection of a stack overflow or underflow.The high performance offered by the hardware implementation of the CPU can efficientlybe utilized by a programmer via the highly efficient XC167 instruction set which includesthe following instruction classes:–––––––––––––
Standard Arithmetic Instructions
DSP-Oriented Arithmetic InstructionsLogical Instructions
Boolean Bit Manipulation InstructionsCompare and Loop Control InstructionsShift and Rotate InstructionsPrioritize Instruction
Data Movement InstructionsSystem Stack InstructionsJump and Call InstructionsReturn Instructions
System Control InstructionsMiscellaneous Instructions
The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytesand words. A variety of direct, indirect or immediate addressing modes are provided tospecify the required operands.
Data Sheet22V1.1, 2003-06
XC167Derivatives
Preliminary
Functional Description
3.4Interrupt System
With an interrupt response time of typically 8CPU clocks (in case of internal programexecution), the XC167 is capable of reacting very fast to the occurrence of non-deterministic events.
The architecture of the XC167 supports several mechanisms for fast and flexibleresponse to service requests that can be generated from various sources internal orexternal to the microcontroller. Any of these interrupt requests can be programmed tobeing serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC).In contrast to a standard interrupt service where the current program execution issuspended and a branch to the interrupt vector table is performed, just one cycle is‘stolen’ from the current CPU activity to perform a PEC service. A PEC service implies asingle byte or word data transfer between any two memory locations with an additionalincrement of either the PEC source, or the destination pointer, or both. An individual PECtransfer counter is implicitly decremented for each PEC service except when performingin the continuous transfer mode. When this counter reaches zero, a standard interrupt isperformed to the corresponding source related vector location. PEC services are verywell suited, for example, for supporting the transmission or reception of blocks of data.The XC167 has 8 PEC channels each of which offers such fast interrupt-driven datatransfer capabilities.
A separate control register which contains an interrupt request flag, an interrupt enableflag and an interrupt priority bitfield exists for each of the possible interrupt nodes. Via itsrelated register, each node can be programmed to one of sixteen interrupt priority levels.Once having been accepted by the CPU, an interrupt service can only be interrupted bya higher prioritized service request. For the standard interrupt processing, each of thepossible interrupt nodes has a dedicated vector location.
Fast external interrupt inputs are provided to service external interrupts with highprecision requirements. These fast interrupt inputs feature programmable edgedetection (rising edge, falling edge, or both edges).
Software interrupts are supported by means of the ‘TRAP’ instruction in combination withan individual trap (interrupt) number.
Table4 shows all of the possible XC167 interrupt sources and the correspondinghardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers.
Note:Interrupt nodes which are not assigned to peripherals (unassigned nodes), maybe used to generate software controlled interrupt requests by setting therespective interrupt request bit (xIR).
Data Sheet23V1.1, 2003-06
XC167Derivatives
PreliminaryTable4
XC167 Interrupt Nodes
Control RegisterCC1_CC0ICCC1_CC1ICCC1_CC2ICCC1_CC3ICCC1_CC4ICCC1_CC5ICCC1_CC6ICCC1_CC7ICCC1_CC8ICCC1_CC9ICCC1_CC10ICCC1_CC11ICCC1_CC12ICCC1_CC13ICCC1_CC14ICCC1_CC15ICCC2_CC16ICCC2_CC17ICCC2_CC18ICCC2_CC19ICCC2_CC20ICCC2_CC21ICCC2_CC22ICCC2_CC23ICCC2_CC24ICCC2_CC25ICCC2_CC26ICCC2_CC27ICCC2_CC28ICCC2_CC29IC
24
Functional Description
Source of Interrupt or PECService RequestCAPCOM Register 0CAPCOM Register 1CAPCOM Register 2CAPCOM Register 3CAPCOM Register 4CAPCOM Register 5CAPCOM Register 6CAPCOM Register 7CAPCOM Register 8CAPCOM Register 9CAPCOM Register 10CAPCOM Register 11CAPCOM Register 12CAPCOM Register 13CAPCOM Register 14CAPCOM Register 15CAPCOM Register 16CAPCOM Register 17CAPCOM Register 18CAPCOM Register 19CAPCOM Register 20CAPCOM Register 21CAPCOM Register 22CAPCOM Register 23CAPCOM Register 24CAPCOM Register 25CAPCOM Register 26CAPCOM Register 27CAPCOM Register 28CAPCOM Register 29
Data Sheet
VectorLocation1)xx’0040Hxx’0044Hxx’0048Hxx’004CHxx’0050Hxx’0054Hxx’0058Hxx’005CHxx’0060Hxx’0064Hxx’0068Hxx’006CHxx’0070Hxx’0074Hxx’0078Hxx’007CHxx’00C0Hxx’00C4Hxx’00C8Hxx’00CCHxx’00D0Hxx’00D4Hxx’00D8Hxx’00DCHxx’00E0Hxx’00E4Hxx’00E8Hxx’00ECHxx’00E0Hxx’0110H
TrapNumber10H / 16D11H / 17D12H / 18D13H / 19D14H / 20D15H / 21D16H / 22D17H / 23D18H / 24D19H / 25D1AH / 26D1BH / 27D1CH / 28D1DH / 29D1EH / 30D1FH / 31D30H / 48D31H / 49D32H / 50D33H / 51D34H / 52D35H / 53D36H / 54D37H / 55D38H / 56D39H / 57D3AH / 58D3BH / 59D3CH / 60D44H / 68D
V1.1, 2003-06
XC167Derivatives
PreliminaryTable4
XC167 Interrupt Nodes (cont’d)
Control RegisterCC2_CC30ICCC2_CC31ICCC1_T0ICCC1_T1ICCC2_T7ICCC2_T8ICGPT12E_T2ICGPT12E_T3ICGPT12E_T4ICGPT12E_T5ICGPT12E_T6ICGPT12E_CRICADC_CICADC_EICASC0_TICASC0_TBICASC0_RICASC0_EICASC0_ABICSSC0_TICSSC0_RICSSC0_EICIIC_DTICIIC_PEICPLLICASC1_TICASC1_TBICASC1_RICASC1_EICASC1_ABIC
25
Functional Description
Source of Interrupt or PECService RequestCAPCOM Register 30CAPCOM Register 31CAPCOM Timer 0CAPCOM Timer 1CAPCOM Timer 7CAPCOM Timer 8GPT1 Timer 2GPT1 Timer 3GPT1 Timer 4GPT2 Timer 5GPT2 Timer 6GPT2 CAPREL Reg.A/D Conversion Compl.A/D Overrun ErrorASC0 TransmitASC0 Transmit BufferASC0 ReceiveASC0 ErrorASC0 AutobaudSSC0 TransmitSSC0 ReceiveSSC0 Error
IIC Data Transfer EventIIC Protocol EventPLL/OWDASC1 TransmitASC1 Transmit BufferASC1 ReceiveASC1 ErrorASC1 Autobaud
Data Sheet
VectorLocation1)xx’0114Hxx’0118Hxx’0080Hxx’0084Hxx’00F4Hxx’00F8Hxx’0088Hxx’008CHxx’0090Hxx’0094Hxx’0098Hxx’009CHxx’00A0Hxx’00A4Hxx’00A8Hxx’011CHxx’00ACHxx’00B0Hxx’017CHxx’00B4Hxx’00B8Hxx’00BCHxx’0100Hxx’0104Hxx’010CHxx’0120Hxx’0178Hxx’0124Hxx’0128Hxx’0108H
TrapNumber45H / 69D46H / 70D20H / 32D21H / 33D3DH / 61D3EH / 62D22H / 34D23H / 35D24H / 36D25H / 37D26H / 38D27H / 39D28H / 40D29H / 41D2AH / 42D47H / 71D2BH / 43D2CH / 44D5FH / 95D2DH / 45D2EH / 46D2FH / 47D40H / 64D41H / 65D43H / 67D48H / 72D5EH / 94D49H / 73D4AH / 74D42H / 66D
V1.1, 2003-06
XC167Derivatives
PreliminaryTable4
XC167 Interrupt Nodes (cont’d)
Control RegisterEOPICCCU6_T12ICCCU6_T13ICCCU6_EICCCU6_ICSSC1_TICSSC1_RICSSC1_EICCAN_0ICCAN_1ICCAN_2ICCAN_3ICCAN_4ICCAN_5ICCAN_6ICCAN_7ICRTC_IC---------VectorLocation1)xx’0130Hxx’0134Hxx’0138Hxx’013CHxx’0140Hxx’0144Hxx’0148Hxx’014CHxx’0150Hxx’0154Hxx’0158Hxx’015CHxx’0164Hxx’0168Hxx’016CHxx’0170Hxx’0174Hxx’012CHxx’00FCHxx’0160H
TrapNumber4CH / 76D4DH / 77D4EH / 78D4FH / 79D50H / 80D51H / 81D52H / 82D53H / 83D54H / 84D55H / 85D56H / 86D57H / 87D59H / 89D5AH / 90D5BH / 91D5CH / 92D5DH / 93D4BH / 75D3FH / 63D58H / 88D
Functional Description
Source of Interrupt or PECService RequestEnd of PEC Subch.CAPCOM6 Timer T12CAPCOM6 Timer T13CAPCOM6 EmergencyCAPCOM6SSC1 TransmitSSC1 ReceiveSSC1 ErrorCAN0CAN1CAN2CAN3CAN4CAN5CAN6CAN7RTC
Unassigned nodeUnassigned nodeUnassigned node
1)
Register VECSEG defines the segment where the vector table is located to.
Bitfield VECSC in register CPUCON1 defines the distance between two adjacent vectors. This tablerepresents the default setting, with a distance of 4 (two words) between two vectors.
Data Sheet26V1.1, 2003-06
XC167Derivatives
Preliminary
Functional Description
The XC167 also provides an excellent mechanism to identify and to process exceptionsor error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardwaretraps cause immediate non-maskable system reaction which is similar to a standardinterrupt service (branching to a dedicated vector table location). The occurence of ahardware trap is additionally signified by an individual bit in the trap flag register (TFR).Except when another higher prioritized trap service is in progress, a hardware trap willinterrupt any actual program execution. In turn, hardware trap services can normally notbe interrupted by standard or PEC interrupts.
Table5 shows all of the possible exceptions or error conditions that can arise during run-time:Table5
Hardware Trap Summary
TrapFlag–
RESETRESETRESET
NMISTKOFSTKUFSOFTBRKUNDOPCPACERPRTFLTILLOPA––
NMITRAPSTOTRAPSTUTRAPSBRKTRAPBTRAPBTRAPBTRAPBTRAP––
xx’0000Hxx’0000Hxx’0000Hxx’0008Hxx’0010Hxx’0018Hxx’0020Hxx’0028Hxx’0028Hxx’0028Hxx’0028H[2CH – 3CH]
00H00H00H02H04H06H08H0AH0AH0AH0AH[0BH – 0FH]
IIIIIIIIIIIIIIIIIIIII–CurrentCPU Priority
TrapVector
VectorLocation1)
TrapTrapNumberPriority
Exception ConditionReset Functions:–Hardware Reset–Software Reset
–W-dog Timer OverflowClass A Hardware Traps:–Non-Maskable Interrupt–Stack Overflow–Stack Underflow–Software BreakClass B Hardware Traps:–Undefined Opcode–PMI Access Error–Protected InstructionFault
–Illegal Word OperandAccessReserved
Software Traps–TRAP Instruction
AnyAny[xx’0000H – [00H – xx’01FCH]7FH]in stepsof 4H
1)
Register VECSEG defines the segment where the vector table is located to.
Data Sheet27V1.1, 2003-06
XC167Derivatives
Preliminary
Functional Description
3.5On-Chip Debug Support (OCDS)
The On-Chip Debug Support system provides a broad range of debug and emulationfeatures built into the XC167. The user software running on the XC167 can thus bedebugged within the target system environment.
The OCDS is controlled by an external debugging device via the debug interface,consisting of the IEEE-1149-conforming JTAG port and a break interface. The debuggercontrols the OCDS via a set of dedicated registers accessible via the JTAG interface.Additionally, the OCDS system can be controlled by the CPU, e.g. by a monitor program.An injection interface allows the execution of OCDS-generated instructions by the CPU.Multiple breakpoints can be triggered by on-chip hardware, by software, or by anexternal trigger input. Single stepping is supported as well as the injection of arbitraryinstructions and read/write access to the complete internal address space. A breakpointtrigger can be answered with a CPU-halt, a monitor call, a data transfer, or/and theactivation of an external signal.
Tracing data can be obtained via the JTAG interface or via the external bus interface forincreased performance.
The debug interface uses a set of 6 interface signals (4 JTAG lines, 2 break lines) tocommunicate with external circuitry. These interface signals use dedicated pins.Complete system emulation is supported by the New Emulation Technology (NET)interface. Via this full-featured emulation interface (including internal buses, control,status, and pad signals) the XC167 chip can be connected to a NET carrier chip.The use of the XC167 production chip together with the carrier chip provides superioremulation behavior, because the emulation system shows exactly the same functionalityas the production chip (use of the identical silicon).
Data Sheet28V1.1, 2003-06
XC167Derivatives
Preliminary
Functional Description
3.6Capture/Compare Units (CAPCOM1/2)
The CAPCOM units support generation and control of timing sequences on up to32channels with a maximum resolution of 1 system clock cycle (8 cycles in staggeredmode). The CAPCOM units are typically used to handle high speed I/O tasks such aspulse and waveform generation, pulse width modulation (PMW), Digital to Analog (D/A)conversion, software timing, or time recording relative to external events.
Four 16-bit timers (T0/T1, T7/T8) with reload registers provide two independent timebases for each capture/compare register array.
The input clock for the timers is programmable to several prescaled values of the internalsystem clock, or may be derived from an overflow/underflow of timer T6 in module GPT2.This provides a wide range of variation for the timer period and resolution and allowsprecise adjustments to the application specific requirements. In addition, external countinputs for CAPCOM timers T0 and T7 allow event scheduling for the capture/compareregisters relative to external events.
Both of the two capture/compare register arrays contain 16 dual purpose capture/compare registers, each of which may be individually allocated to either CAPCOM timerT0 or T1 (T7 or T8, respectively), and programmed for capture or compare function.All registers of each module have each one port pin associated with it which serves asan input pin for triggering the capture function, or as an output pin to indicate theoccurrence of a compare event.Table6Mode 0Mode 1Mode 2Mode 3
Double Register Mode
Single Event Mode
Compare Modes (CAPCOM1/2)
Function
Interrupt-only compare mode;
several compare interrupts per timer period are possiblePin toggles on each compare match;
several compare events per timer period are possibleInterrupt-only compare mode;
only one compare interrupt per timer period is generatedPin set ‘1’ on match; pin reset ‘0’ on compare timer overflow;only one compare event per timer period is generatedTwo registers operate on one pin;pin toggles on each compare match;
several compare events per timer period are possibleGenerates single edges or pulses;can be used with any compare mode
Compare Modes
Data Sheet29V1.1, 2003-06
XC167Derivatives
Functional DescriptionPreliminary
When a capture/compare register has been selected for capture mode, the current
contents of the allocated timer will be latched (‘captured’) into the capture/compareregister in response to an external event at the port pin which is associated with thisregister. In addition, a specific interrupt request for this capture/compare register isgenerated. Either a positive, a negative, or both a positive and a negative external signaltransition at the pin can be selected as the triggering event.
The contents of all registers which have been selected for one of the five compare modesare continuously compared with the contents of the allocated timers.
When a match occurs between the timer value and the value in a capture/compareregister, specific actions will be taken based on the selected compare mode.
Reload Reg. TxRELfSYSTxINGPT2 Timer T6Over/UnderflowCCzIO2n : 1TxInputControlCAPCOM Timer TxInterruptRequest(TxIR)Capture InputsCompare OutputsCCzIOModeControl(CaptureorCompare)16-BitCapture/CompareRegistersCapture/CompareInterrupt Requests(CCzIR)fSYSGPT2 Timer T6Over/Underflow2n : 1TyInputControlCAPCOM Timer TyInterruptRequest(TyIR)xynz====0,71,80/3 … 100 … 31Reload Reg. TyRELMCB02143_X1.VSDFigure5
Data Sheet
CAPCOM1/2 Unit Block Diagram
30
V1.1, 2003-06
XC167Derivatives
Preliminary
Functional Description
3.7The Capture/Compare Unit CAPCOM6
The CAPCOM6 unit supports generation and control of timing sequences on up to three16-bit capture/compare channels plus one independent 10-bit compare channel.
In compare mode the CAPCOM6 unit provides two output signals per channel whichhave inverted polarity and non-overlapping pulse transitions (deadtime control). Thecompare channel can generate a single PWM output signal and is further used tomodulate the capture/compare output signals.
In capture mode the contents of compare timer T12 is stored in the capture registersupon a signal transition at pins CCx.
Compare timers T12 (16-bit) and T13 (10-bit) are free running timers which are clockedby the prescaled system clock. ModeSelect RegisterCC6MSELCC Channel 0CC60ControlCC Channel 1CC61CC Channel 2CC62PortControlLogicPeriod RegisterT12PTrap RegisterCTRAPfCPUPrescalerOffset RegisterT12OFCompareTimer T1216-BitCC60COUT60CC61COUT61CC62COUT62COUT63Cntrol RegisterCTCONPrescalerfCPUCompareTimer T1310-BitCompare RegisterCMP13BlockCommutationControlCC6MCON.HCC6POS0CC6POS1CC6POS2MCB04109Period RegisterT13PThe timer registers (T12, T13) are not directly accessible.The period and offset registers are loading a value into the timer registers.Figure6CAPCOM6 Block Diagram
For motor control applications both subunits may generate versatile multichannel PWMsignals which are basically either controlled by compare timer T12 or by a typical hallsensor pattern at the interrupt inputs (block commutation).
Data Sheet31V1.1, 2003-06
XC167Derivatives
Preliminary
Functional Description
3.8General Purpose Timer (GPT12E) Unit
The GPT12E unit represents a very flexible multifunctional timer/counter structure whichmay be used for many different time related tasks such as event timing and counting,pulse width and duty cycle measurements, pulse generation, or pulse multiplication.The GPT12E unit incorporates five 16-bit timers which are organized in two separatemodules, GPT1 and GPT2. Each timer in each module may operate independently in anumber of different modes, or may be concatenated with another timer of the samemodule.
Each of the three timers T2, T3, T4 of module GPT1 can be configured individually forone of four basic modes of operation, which are Timer, Gated Timer, Counter, andIncremental Interface Mode. In Timer Mode, the input clock for a timer is derived fromthe system clock, divided by a programmable prescaler, while Counter Mode allows atimer to be clocked in reference to external events.
Pulse width or duty cycle measurement is supported in Gated Timer Mode, where theoperation of a timer is controlled by the ‘gate’ level on an external input pin. For thesepurposes, each timer has one associated port pin (TxIN) which serves as gate or clockinput. The maximum resolution of the timers in module GPT1 is 4 system clock cycles.The count direction (up/down) for each timer is programmable by software or mayadditionally be altered dynamically by an external signal on a port pin (TxEUD) tofacilitate e.g. position tracking.
In Incremental Interface Mode the GPT1 timers (T2, T3, T4) can be directly connectedto the incremental position sensor signals A and B via their respective inputs TxIN andTxEUD. Direction and count signals are internally derived from these two input signals,so the contents of the respective timer Tx corresponds to the sensor position. The thirdposition sensor signal TOP0 can be connected to an interrupt input.
Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer over-flow/underflow. The state of this latch may be output on pin T3OUT e.g. for time outmonitoring of external hardware components. It may also be used internally to clocktimers T2 and T4 for measuring long time periods with high resolution.
In addition to their basic operating modes, timers T2 and T4 may be configured as reloador capture registers for timer T3. When used as capture or reload registers, timers T2and T4 are stopped. The contents of timer T3 is captured into T2 or T4 in response to asignal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2or T4 triggered either by an external signal or by a selectable state transition of its togglelatch T3OTL. When both T2 and T4 are configured to alternately reload T3 on oppositestate transitions of T3OTL with the low and high times of a PWM signal, this signal canbe constantly generated without software intervention.
Data Sheet32V1.1, 2003-06
XC167Derivatives
Preliminary
Functional Description
fSYST2INT2EUD2n : 1GPT1 Timer T2T2ModeControlU/DReloadCaptureInterruptRequest(T2IR)fSYST3IN2n : 1T3ModeControlToggle FFGPT1 Timer T3U/DT3OTLInterruptRequest(T3IR)T6OUTT3EUDCaptureReloadT4ModeControlInterruptRequest(T4IR)fSYST4INT4EUD2n : 1GPT1 Timer T4U/Dn = 2 … 12Figure7
Block Diagram of GPT1
Mct04825_xc.vsdWith its maximum resolution of 2 system clock cycles, the GPT2 module providesprecise event control and time measurement. It includes two timers (T5, T6) and acapture/reload register (CAPREL). Both timers can be clocked with an input clock whichis derived from the CPU clock via a programmable prescaler or with external signals. Thecount direction (up/down) for each timer is programmable by software or mayadditionally be altered dynamically by an external signal on a port pin (TxEUD).Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6,which changes its state on each timer overflow/underflow.
The state of this latch may be used to clock timer T5, and/or it may be output on pinT6OUT. The overflows/underflows of timer T6 can additionally be used to clock theCAPCOM1/2 timers, and to cause a reload from the CAPREL register.
The CAPREL register may capture the contents of timer T5 based on an external signaltransition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared
Data Sheet
33
V1.1, 2003-06
XC167Derivatives
Preliminary
Functional Description
after the capture procedure. This allows the XC167 to measure absolute time differencesor to perform pulse multiplication without software overhead.
The capture trigger (timer T5 to CAPREL) may also be generated upon transitions ofGPT1 timer T3’s inputs T3IN and/or T3EUD. This is especially advantageous when T3operates in Incremental Interface Mode.
fSYST5INT5EUD2n : 1T5ModeControlGPT2 Timer T5U/DClearCaptureInterruptRequest(T5IR)T3IN/T3EUDCAPINGPT2 CAPRELMUXInterruptRequest(CRIR)InterruptRequest(T6IR)CT3ClearfSYST6INT6EUDMcb03999_xc.vsdToggle FF2n : 1T6ModeControlGPT2 Timer T6U/DT6OTLT6OUTOtherModulesn = 1 … 11Figure8
Block Diagram of GPT2
Data Sheet34V1.1, 2003-06
XC167Derivatives
Preliminary
Functional Description
3.9Real Time Clock
The Real Time Clock (RTC) module of the XC167 is directly clocked via a separate clockdriver either with the on-chip auxiliary oscillator frequency (fRTC = fOSCa) or with theprescaled on-chip main oscillator frequency (fRTC = fOSCm/32). It is thereforeindependent from the selected clock generation mode of the XC167.The RTC basically consists of a chain of divider blocks:
•a selectable 8:1 divider (on - off)•the reloadable 16-bit timer T14
•the 32-bit RTC timer block (accessible via registers RTCH and RTCL), made of:–a reloadable 10-bit timer–a reloadable 6-bit timer–a reloadable 6-bit timer–a reloadable 10-bit timerAll timers count up. Each timer can generate an interrupt request. All requests arecombined to a common node request. Additionally, T14 can generate a separate noderequest.
RUNPREfRTC81MUX0Interrupt Sub NodeCNTINT0CNTINT1CNTINT2CNTINT3RTCINTREL-RegisterT14REL10 Bits6 Bits6 Bits10 BitsT14T14-Register10 Bits6 Bits6 Bits10 BitsCNT-Registermcb04805_xc.vsdFigure9RTC Block Diagram
Note:The registers associated with the RTC are not affected by a reset in order tomaintain the correct system time even when intermediate resets are executed.Data Sheet35V1.1, 2003-06
XC167Derivatives
Preliminary
The RTC module can be used for different purposes:
•System clock to determine the current time and date,
optionally during idle mode, sleep mode, and power down mode
•Cyclic time based interrupt, to provide a system time tick independent of CPUfrequency and other resources, e.g. to wake up regularly from idle mode.•48-bit timer for long term measurements (maximum timespan is >100 years).Functional Description
•Alarm interrupt for wake-up on a defined time
Data Sheet36V1.1, 2003-06
XC167Derivatives
Preliminary
Functional Description
3.10A/D Converter
For analog signal measurement, a 10-bit A/D converter with 16 multiplexed inputchannels and a sample and hold circuit has been integrated on-chip. It uses the methodof successive approximation. The sample time (for loading the capacitors) and theconversion time is programmable (in two modes) and can thus be adjusted to theexternal circuitry. The A/D converter can also operate in 8-bit conversion mode, wherethe conversion time is further reduced.
Overrun error detection/protection is provided for the conversion result register(ADDAT): either an interrupt request will be generated when the result of a previousconversion has not been read from the result register at the time the next conversion iscomplete, or the next conversion is suspended in such a case until the previous resulthas been read.
For applications which require less analog input channels, the remaining channel inputscan be used as digital input port pins.
The A/D converter of the XC167 supports four different conversion modes. In thestandard Single Channel conversion mode, the analog level on a specified channel issampled once and converted to a digital result. In the Single Channel Continuous mode,the analog level on a specified channel is repeatedly sampled and converted withoutsoftware intervention. In the Auto Scan mode, the analog levels on a prespecifiednumber of channels are sequentially sampled and converted. In the Auto ScanContinuous mode, the prespecified channels are repeatedly sampled and converted. Inaddition, the conversion of a specific channel can be inserted (injected) into a runningsequence without disturbing this sequence. This is called Channel Injection Mode.The Peripheral Event Controller (PEC) may be used to automatically store theconversion results into a table in memory for later evaluation, without requiring theoverhead of entering and exiting interrupt routines for each data transfer.
After each reset and also during normal operation the ADC automatically performscalibration cycles. This automatic self-calibration constantly adjusts the converter tochanging operating conditions (e.g. temperature) and compensates process variations.These calibration cycles are part of the conversion cycle, so they do not affect the normaloperation of the A/D converter.
In order to decouple analog inputs from digital noise and to avoid input trigger noisethose pins used for analog input can be disconnected from the digital IO or input stagesunder software control. This can be selected for each pin separately via register P5DIDIS(Port5 Digital Input Disable).
The Auto-Power-Down feature of the A/D converter minimizes the power consumptionwhen no conversion is in progress.
Data Sheet37V1.1, 2003-06
XC167Derivatives
Preliminary
Functional Description
3.11Asynchronous/Synchronous Serial Interfaces (ASC0/ASC1)
The Asynchronous/Synchronous Serial Interfaces ASC0/ASC1 (USARTs) provide serialcommunication with other microcontrollers, processors, terminals or external peripheralcomponents. They are upward compatible with the serial ports of the Infineon 8-bitmicrocontroller families and support full-duplex asynchronous communication and half-duplex synchronous communication. A dedicated baud rate generator with a fractionaldivider precisely generates all standard baud rates without oscillator tuning. Fortransmission, reception, error handling, and baudrate detection 5 separate interruptvectors are provided.
In asynchronous mode, 8- or 9-bit data frames (with optional parity bit) are transmittedor received, preceded by a start bit and terminated by one or two stop bits. Formultiprocessor communication, a mechanism to distinguish address from data bytes hasbeen included (8-bit data plus wake-up bit mode). IrDA data transmissions up to115.2kbit/s with fixed or programmable IrDA pulse width are supported.
In synchronous mode, bytes (8 bits) are transmitted or received synchronously to a shiftclock which is generated by the ASC0/1. The LSB is always shifted first.
In both modes, transmission and reception of data is FIFO-buffered. An autobauddetection unit allows to detect asynchronous data frames with its baudrate and modewith automatic initialization of the baudrate generator and the mode control bits.A number of optional hardware error detection capabilities has been included to increasethe reliability of data transfers. A parity bit can automatically be generated ontransmission or be checked on reception. Framing error detection allows to recognizedata frames with missing stop bits. An overrun error will be generated, if the lastcharacter received has not been read out of the receive buffer register at the time thereception of a new character is complete.Summary of Features
•Full-duplex asynchronous operating modes
–8- or 9-bit data frames, LSB first, one or two stop bits, parity generation/checking–Baudrate from 2.5 Mbit/s to 0.6 bit/s (@ 40 MHz)
–Multiprocessor mode for automatic address/data byte detection
–Support for IrDA data transmission/reception up to max. 115.2 kbit/s (@ 40 MHz)–Loop-back capability–Auto baudrate detection
•Half-duplex 8-bit synchronous operating mode at 5 Mbit/s to 406.9 bit/s (@ 40 MHz)•Buffered transmitter/receiver with FIFO support (8 entries per direction)•Loop-back option available for testing purposes
•Interrupt generation on transmitter buffer empty condition, last bit transmittedcondition, receive buffer full condition, error condition (frame, parity, overrun error),start and end of an autobaud detection
Data Sheet38V1.1, 2003-06
XC167Derivatives
Preliminary
Functional Description
3.12High Speed Synchronous Serial Channels (SSC0/SSC1)
The High Speed Synchronous Serial Channels SSC0/SSC1 support full-duplex and half-duplex synchronous communication. It may be configured so it interfaces with seriallylinked peripheral components, full SPI functionality is supported.
A dedicated baud rate generator allows to set up all standard baud rates withoutoscillator tuning. For transmission, reception and error handling three separate interruptvectors are provided.
The SSC transmits or receives characters of 2 … 16 bits length synchronously to a shiftclock which can be generated by the SSC (master mode) or by an external master (slavemode). The SSC can start shifting with the LSB or with the MSB and allows the selectionof shifting and latching clock edges as well as the clock polarity.
A number of optional hardware error detection capabilities has been included to increasethe reliability of data transfers. Transmit error and receive error supervise the correcthandling of the data buffer. Phase error and baudrate error detect incorrect serial data.Summary of Features••••
Master or Slave mode operationFull-duplex or Half-duplex transfers
Baudrate generation from 20 Mbit/s to 305.18 bit/s (@40MHz)Flexible data format
–Programmable number of data bits: 2 to 16 bits–Programmable shift direction: LSB-first or MSB-first–Programmable clock polarity: idle low or idle high
–Programmable clock/data phase: data shift with leading or trailing clock edge•Loop back option available for testing purposes
•Interrupt generation on transmitter buffer empty condition, receive buffer full condition,error condition (receive, phase, baudrate, transmit error)•Three pin interface with flexible SSC pin configuration
Data Sheet39V1.1, 2003-06
XC167Derivatives
Preliminary
Functional Description
3.13TwinCAN Module
The integrated TwinCAN module handles the completely autonomous transmission andreception of CAN frames in accordance with the CAN specification V2.0 part B (active),i.e. the on-chip TwinCAN module can receive and transmit standard frames with 11-bitidentifiers as well as extended frames with 29-bit identifiers.
Two Full-CAN nodes share the TwinCAN module’s resources to optimize the CAN bustraffic handling and to minimize the CPU load. The module provides up to 32messageobjects, which can be assigned to one of the CAN nodes and can be combined to FIFO-structures. Each object provides separate masks for acceptance filtering.
The flexible combination of Full-CAN functionality and FIFO architecture reduces theefforts to fulfill the real-time requirements of complex embedded control applications.Improved CAN bus monitoring functionality as well as the number of message objectspermit precise and comfortable CAN bus traffic handling.
Gateway functionality allows automatic data exchange between two separate CAN bussystems, which reduces CPU load and improves the real time behavior of the entiresystem.
The bit timing for both CAN nodes is derived from the master clock and is programmableup to a data rate of 1Mbit/s. Each CAN node uses two pins of Port4, Port7, or Port9 tointerface to an external bus transceiver. The interface pins are assigned via software. TwinCAN Module KernelClockControlfCANCANNode ACANNode BTXDCARXDCAAddressDecoderMessageObjectBufferPortControlTXDCBRXDCBInterruptControlTwinCAN ControlMCB04515Figure10TwinCAN Module Block Diagram
Data Sheet40V1.1, 2003-06
XC167Derivatives
Preliminary
Summary of Features•••••
CAN functionality according to CAN specification V2.0 B active.Data transfer rate up to 1Mbit/s
Flexible and powerful message transfer control and error handling capabilitiesFull-CAN functionality and Basic CAN functionality for each message object32 flexible message objects
–Assignment to one of the two CAN nodes
–Configuration as transmit object or receive object
–Concatenation to a 2-, 4-, 8-, 16-, or 32-message buffer with FIFO algorithm–Handling of frames with 11-bit or 29-bit identifiers
–Individual programmable acceptance mask register for filtering for each object–Monitoring via a frame counter
–Configuration for Remote Monitoring Mode
•Up to eight individually programmable interrupt nodes can be used•CAN Analyzer Mode for bus monitoring is implemented
Functional Description
Note:When a CAN node has the interface lines assigned to Port4, the segment addressoutput on Port4 must be limited. CS lines can be used to increase the total amountof addressable external memory.3.14IIC Bus Module
The integrated IIC Bus Module handles the transmission and reception of frames overthe two-line IIC bus in accordance with the IIC Bus specification. The IICModule canoperate in slave mode, in master mode or in multi-master mode. It can receive andtransmit data using 7-bit or 10-bit addressing. Up to 4 send/receive data bytes can bestored in the extended buffers.
Several physical interfaces (port pins) can be established under software control. Datacan be transferred at speeds up to 400 kbit/sec.
Two interrupt nodes dedicated to the IIC module allow efficient interrupt service and alsosupport operation via PEC transfers.
Note:The port pins associated with the IIC interfaces must be switched to open drainmode, as required by the IIC specification.Data Sheet41V1.1, 2003-06
XC167Derivatives
Preliminary
Functional Description
3.15Watchdog Timer
The Watchdog Timer represents one of the fail-safe mechanisms which have beenimplemented to prevent the controller from malfunctioning for longer periods of time.The Watchdog Timer is always enabled after a reset of the chip, and can be disableduntil the EINIT instruction has been executed (compatible mode), or it can be disabledand enabled at any time by executing instructions DISWDT and ENWDT (enhancedmode). Thus, the chip’s start-up procedure is always monitored. The software has to bedesigned to restart the Watchdog Timer before it overflows. If, due to hardware orsoftware related failures, the software fails to do so, the Watchdog Timer overflows andgenerates an internal hardware reset and pulls the RSTOUT pin low in order to allowexternal hardware components to be reset.
The Watchdog Timer is a 16-bit timer, clocked with the system clock divided by 2/4/128/256. The high byte of the Watchdog Timer register can be set to a prespecified reloadvalue (stored in WDTREL) in order to allow further variation of the monitored timeinterval. Each time it is serviced by the application software, the high byte of theWatchdog Timer is reloaded and the low byte is cleared. Thus, time intervals between13µs and 419ms can be monitored (@ 40MHz).
The default Watchdog Timer interval after reset is 3.28ms (@ 40MHz).
Data Sheet42V1.1, 2003-06
XC167Derivatives
Preliminary
Functional Description
3.16Clock Generation
The Clock Generation Unit uses a programmable on-chip PLL with multiple prescalersto generate the clock signals for the XC167 with high flexibility. The master clock fMC isthe reference clock signal, and is used for TwinCAN and is output to the external system.The CPU clock fCPU and the system clock fSYS are derived from the master clock eitherdirectly (1:1) or via a 2:1 prescaler (fSYS = fCPU = fMC / 2). See also Section5.1.The on-chip oscillator can drive an external crystal or accepts an external clock signal.The oscillator clock frequency can be multiplied by the on-chip PLL (by a programmablefactor) or can be divided by a programmable prescaler factor.
If the bypass mode is used (direct drive or prescaler) the PLL can deliver an independentclock to monitor the clock signal generated by the on-chip oscillator. This PLL clock isindependent from the XTAL1 clock. When the expected oscillator clock transitions aremissing the Oscillator Watchdog (OWD) activates the PLL Unlock / OWD interrupt nodeand supplies the CPU with an emergency clock, the PLL clock signal. Under thesecircumstances the PLL will oscillate with its basic frequency.
The oscillator watchdog can be disabled by switching the PLL off. This reduces powerconsumption, but also no interrupt request will be generated in case of a missingoscillator clock.
Note:At the end of an external reset (EA = ‘0’) the oscillator watchdog may be disabledvia hardware by (externally) pulling the RD line low upon a reset, similar to thestandard reset configuration.3.17Parallel Ports
The XC167 provides up to 103 I/O lines which are organized into nine input/output portsand one input port. All port lines are bit-addressable, and all input/output lines areindividually (bit-wise) programmable as inputs or outputs via direction registers. The I/Oports are true bidirectional ports which are switched to high impedance state whenconfigured as inputs. The output drivers of some I/O ports can be configured (pin by pin)for push/pull operation or open-drain operation via control registers. During the internalreset, all port pins are configured as inputs (except for pin RSTOUT).The edge characteristics (shape) and driver characteristics (output current) of the portdrivers can be selected via registers POCONx.
The input threshold of some ports is selectable (TTL or CMOS like), where the specialCMOS like input threshold reduces noise sensitivity due to the input hysteresis. Theinput threshold may be selected individually for each byte of the respective ports.All port lines have programmable alternate input or output functions associated withthem. All port lines that are not used for these alternate functions may be used as generalpurpose IO lines.
Data Sheet
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V1.1, 2003-06
XC167Derivatives
PreliminaryTable7PortPORT0PORT1
Summary of the XC167’s Parallel PortsControlPad driversPad drivers
Alternate Functions
Address/Data lines or data lines1)Address lines2)Capture inputs or compare outputs,Serial interface lines
Port 2
Pad drivers,Open drain,Input thresholdPad drivers, Open drain,Input thresholdPad drivers, Open drain,Input threshold---Open drain,Input thresholdOpen drain,Input thresholdPad drivers, Open drain,Input thresholdPad drivers, Open drain
Capture inputs or compare outputs,Timer control signal,
Fast external interrupt inputs
Timer control signals, serial interface lines,Optional bus control signal BHE/WRH,System clock output CLKOUT (or FOUT)Segment address lines3)CAN interface lines4)Analog input channels to the A/D converter,Timer control signals
Capture inputs or compare outputs,
Bus arbitration signals BREQ, HLDA, HOLD,Optional chip select signalsCapture inputs or compare outputs,CAN interface lines4)
Capture inputs or compare outputsCAN interface lines4),IIC bus interface lines4)
Bus control signals RD, WR/WRL, READY, ALE,External access enable pin EA,Reset indication output RSTOUTFunctional Description
Port 3
Port 4
Port 5Port 6
Port 7Port 9
Port 20
1)2)3)4)
For multiplexed bus cycles.For demultiplexed bus cycles.
For more than 64Kbytes of external resources.Can be assigned by software.
Data Sheet44V1.1, 2003-06
XC167Derivatives
Preliminary
Functional Description
3.18Power Management
The XC167 provides several means to control the power it consumes either at a giventime or averaged over a certain timespan. Three mechanisms can be used (partly inparallel):
•Power Saving Modes switch the XC167 into a special operating mode (control viainstructions).
Idle Mode stops the CPU while the peripherals can continue to operate.
Sleep Mode and Power Down Mode stop all clock signals and all operation (RTC mayoptionally continue running). Sleep Mode can be terminated by external interruptsignals.
•Clock Generation Management controls the distribution and the frequency ofinternal and external clock signals. While the clock signals for currently inactive partsof logic are disabled automatically, the user can reduce the XC167’s CPU clockfrequency which drastically reduces the consumed power.
External circuitry can be controlled via the programmable frequency output FOUT.•Peripheral Management permits temporary disabling of peripheral modules (controlvia register SYSCON3). Each peripheral can separately be disabled/enabled.The on-chip RTC supports intermittend operation of the XC167 by generating cyclicwake-up signals. This offers full performance to quickly react on action requests whilethe intermittend sleep phases greatly reduce the average power consumption of thesystem.
Data Sheet45V1.1, 2003-06
XC167Derivatives
Preliminary
Functional Description
3.19Instruction Set Summary
Table8 lists the instructions of the XC167 in a condensed way.
The various addressing modes that can be used with a specific instruction, the operationof the instructions, parameters for conditional execution of instructions, and the opcodesfor each instruction can be found in the “Instruction Set Manual”.This document also provides a detailled description of each instruction.Table8
Instruction Set Summary
Description
Add word (byte) operands
Add word (byte) operands with CarrySubtract word (byte) operands
Subtract word (byte) operands with Carry
(Un)Signed multiply direct GPR by direct GPR (16-16-bit)(Un)Signed divide register MDL by direct GPR (16-/16-bit)(Un)Signed long divide reg. MD by direct GPR (32-/16-bit)Complement direct word (byte) GPRNegate direct word (byte) GPRBitwise AND, (word/byte operands)
Bitwise (exclusive)OR, (word/byte operands)Clear/Set direct bit
Move (negated) direct bit to direct bitAND/OR/XOR direct bit with direct bit
Compare direct bit to direct bit
Bitwise modify masked high/low byte of bit-addressable direct word memory with immediate dataCompare word (byte) operands
Compare word data to GPR and decrement GPR by 1/2Compare word data to GPR and increment GPR by 1/2Determine number of shift cycles to normalize directword GPR and store result in direct word GPRShift left/right direct word GPRRotate left/right direct word GPR
Arithmetic (sign bit) shift right direct word GPRMove word (byte) data
Move byte operand to word op. with sign/zero extension
46
MnemonicADD(B)ADDC(B)SUB(B)SUBC(B)MUL(U)DIV(U)DIVL(U)CPL(B)NEG(B)AND(B)(X)OR(B)BCLR / BSETBMOV(N)
BAND / BOR / BXORBCMP
BFLDH / BFLDLCMP(B)CMPD1/2CMPI1/2PRIORSHL / SHRROL / RORASHRMOV(B)MOVBS/Z
Data Sheet
Bytes2 / 42 / 42 / 42 / 4222222 / 42 / 4244442 / 42 / 42 / 422222 / 42 / 4
V1.1, 2003-06
XC167Derivatives
PreliminaryTable8MnemonicJMPA/I/RJMPSJB(C)JNB(S)CALLA/I/RCALLSPCALLTRAP
PUSH / POPSCXTRET(P)
RETSRETISBRKSRSTIDLEPWRDNSRVWDT
DISWDT/ENWDTEINITATOMICEXTREXTP(R)EXTS(R)NOP
CoMUL / CoMACCoADD / CoSUBCo(A)SHR/CoSHLCoLOAD/STORECoCMP/MAX/MINCoABS / CoRNDCoMOV/NEG/NOP
Data Sheet
Functional Description
Instruction Set Summary (cont’d)
Description
Jump absolute/indirect/relative if condition is metJump absolute to a code segment
Jump relative if direct bit is set (and clear bit)Jump relative if direct bit is not set (and set bit)
Call absolute/indirect/relative subroutine if condition is metCall absolute subroutine in any code segment
Push direct word register onto system stack and callabsolute subroutine
Call interrupt service routine via immediate trap numberPush/pop direct word register onto/from system stackPush direct word register onto system stack and updateregister with word operand
Return from intra-segment subroutine
(and pop direct word register from system stack)Return from inter-segment subroutineReturn from interrupt service subroutineSoftware BreakSoftware ResetEnter Idle Mode
Enter Power Down Mode (supposes NMI-pin being low)Service Watchdog Timer
Disable/Enable Watchdog Timer
Signify End-of-Initialization on RSTOUT-pinBegin ATOMIC sequence
Begin EXTended Register sequence
Begin EXTended Page (and Register) sequenceBegin EXTended Segment (and Register) sequenceNull operation
Multiply (and accumulate)Add / Subtract
(Arithmetic) Shift right / Shift left
Load accumulator / Store MAC registerCompare (maximum/minimum)
Absolute value / Round accumulator
Data move / Negate accumulator / Null operation
47
Bytes44444442242222444444222 / 42 / 424444444
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XC167Derivatives
Preliminary
Electrical Parameters
4
4.1
Table9Parameter
Electrical Parameters
Absolute Maximum Ratings
Absolute Maximum Rating Parameters
Symbol
-65-40-0.5-0.5-0.5-10–
Limit Valuesmin.
max.1501503.256.2
°C°CVVVmAmA
–
under bias–––––
Unit
Notes
TSTTJJunction temperature
Voltage on VDDI pins with VDDIrespect to ground (VSS)
Voltage on VDDP pins with VDDPrespect to ground (VSS)Voltage on any pin with VINrespect to ground (VSS)
Storage temperatureInput current on any pin during overload conditionAbsolute sum of all input currents during overload condition
––
+ 0.510|100|
VDDP
Note:Stresses above those listed under “Absolute Maximum Ratings” may causepermanent damage to the device. This is a stress rating only and functionaloperation of the device at these or any other conditions above those indicated inthe operational sections of this specification is not implied. Exposure to absolutemaximum rating conditions for extended periods may affect device reliability.During absolute maximum rating overload conditions (VIN>VDDP or VIN Package Properties Package Parameters (P-TQFP-144-19) Symbol Limit Valuesmin. max.0.832 48 UnitWK/W Notes– Chip-Ambient V1.1, 2003-06 Power dissipationThermal Resistance Data Sheet PDISSRTHA –– XC167Derivatives Preliminary Electrical Parameters 4.3Operating Conditions The following operating conditions must not be exceeded to ensure correct operation ofthe XC167. All parameters specified in the following sections refer to these operatingconditions, unless otherwise noticed.Table11Parameter Digital supply voltage for the core Digital supply voltage for IO pads Digital ground voltageOverload current Operating Condition Parameters Symbol Limit Valuesmin. max.2.75.5–0 -5-2 Overload current coupling KOVAfactor for analog inputs6) Overload current coupling KOVDfactor for digital I/O pins6) Absolute sum of overload Σ|IOV|currentsExternal Load CapacitanceAmbient temperature ––––––0-40-40 1)2) UnitNotesVVVVmAmA Active mode,fCPU = fCPUmax1)Active mode2) VDDIVDDP 2.354.4-0.5 Supply Voltage Difference∆VDD VDDP - VDDI3)Reference voltagePer IO pin4)5)Per analog input pin4)5) VSSIOV 55 1.0 × 10-4–1.5 × 10-3–5.0 × 10-3–1.0 × 10-2–50507085125 mApF°C°C°C IOV > 0IOV < 0IOV > 0IOV < 0 5)CLTA Pin drivers indefault mode7)SAB-XC167…SAF-XC167…SAK-XC167… fCPUmax = 40MHz for devices marked …40F, fCPUmax = 20MHz for devices marked …20F. External circuitry must guarantee low level at the RSTIN pin at least until both power supply voltages havereached the operating range. This limitation must be fulfilled under all operating conditions including power-ramp-up, power-ramp-down, andpower-save modes. 3) Data Sheet49V1.1, 2003-06 XC167Derivatives Preliminary 4) Electrical Parameters Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pinexceeds the specified range: VOV>VDDP + 0.5V (IOV>0) or VOV Not 100% tested, guaranteed by design and characterization. An overload current (IOV) through a pin injects a certain error current (IINJ) into the adjacent pins. This errorcurrent adds to the respective pin’s leakage current (IOZ). The amount of error current depends on the overloadcurrent and is defined by the overload coupling factor KOV. The polarity of the injected error current is inversecompared to the polarity of the overload current that produces it. The total current through a pin is |ITOT| = |IOZ| + (|IOV| × KOV). The additional error current may distort the inputvoltage on analog inputs. The timing is valid for pin drivers operating in default current mode (selected after reset). Reducing the outputcurrent may lead to increased delays or reduced driving capability (CL). 5)6) 7) 4.4Parameter Interpretation The parameters listed in the following partly represent the characteristics of the XC167and partly its demands on the system. To aid in interpreting the parameters right, whenevaluating them for a design, they are marked in column “Symbol”: CC (Controller Characteristics): The logic of the XC167 will provide signals with the respective characteristics. SR (System Requirement): The external system must provide signals with the respective characteristics to theXC167. Data Sheet50V1.1, 2003-06 XC167Derivatives Preliminary Electrical Parameters 4.5 DC Parameters DC Characteristics (Operating Conditions apply)1)Parameter Input low voltage TTL (all except XTAL1, XTAL3)Input low voltage forXTAL1, XTAL32)Input low voltage(Special Threshold)Input high voltage TTL(all except XTAL1, XTAL3)Input high voltage XTAL1, XTAL32) Input high voltage(Special Threshold)Input Hysteresis(Special Threshold)Output low voltageOutput high voltage6)Symbol Limit Valuesmin. max.0.2×VDDPV- 0.10.3 ×VDDIV0.45× VDDP VVVVV –– 3) UnitTest Condition VILSRVILCSRVILSSRVIHSRVIHCSRVIHSSR HYS -0.5-0.5-0.5 0.2×VDDPVDDP + 0.9+ 0.50.7 × VDDI ––– VDDI + 0.5 0.8×VDDPVDDP - 0.2+ 0.50.04 × VDDP–– – VDDP in [V], Series resistance = 0Ω 1.00.45––±300±200 VVVVnAnAnAµAµA VOLCC VOHCCVDDP - 1.0 IOL ≤ IOLmax4)IOL ≤ IOLnom4) 5)IOH ≥ IOHmax4)IOH ≥ IOHnom4) 5) 0V < VIN < VDDP,TA ≤ 125°C0V < VIN < VDDP,TA ≤ 85°C13) VDDP - 0.45 Input leakage current (Port 5)7) IOZ1CC– Input leakage current(all other)7) IOZ2CC– – ±500-10– Configuration pull-up current8)ICPUH9)ICPUL10)-100 VDDP VIN = VIHminVIN = VILmax 0.45V XC167Derivatives Preliminary DC Characteristics (cont’d)(Operating Conditions apply)1)Parameter Configuration pull-down current11) Level inactive hold current12)Level active hold current12)XTAL1, XTAL3 input currentPin capacitance13) (digital inputs/outputs) 1) Electrical Parameters SymbolLimit Valuesmin. max.10–-10–±2010 UnitTest ConditionµAµAµAµAµApF ICPDL9)–ICPDH10)120ILHI9)–ILHA10)-100IILCC–CIOCC– VIN = VILmaxVIN = VIHminVOUT = 0.5 × VDDPVOUT = 0.45 V0V 2)3)4) If XTAL3 is driven by a crystal, reaching an amplitude (peak to peak) of 0.25 × VDDI is sufficient. This parameter is tested for P2, P3, P4, P6, P7, P9. The maximum deliverable output current of a port driver depends on the selected output driver mode, see Table12, Current Limits for Port Output Drivers. The limit for pin groups must be respected. As a rule, with decreasing output current the output levels approach the respective supply level (VOL→VSS,VOH→VDDP). However, only the levels for nominal output currents are guaranteed.This specification is not valid for outputs which are switched to open drain mode. In this case the respectiveoutput will float and the voltage results from the external circuitry. An additional error current (IINJ) will flow if an overload current flows through an adjacent pin. Please refer tothe definition of the overload coupling factor KOV. This specification is valid during Reset for configuration on RD, WR, EA, PORT0.The pull-ups on RD and WR (WRL/WRH) are also active during bus hold.The maximum current may be drawn while the respective signal line remains inactive.The minimum current must be drawn to drive the respective signal line active.This specification is valid during Reset for configuration on ALE.The pull-down on ALE is also active during bus hold. This specification is valid during Reset for pins P6.4-0, which can act as CS outputs.The pull-ups on CS outputs are also active during bus hold.Not 100% tested, guaranteed by design and characterization. 5) 6) 7) 8) 9)10)11) 12) 13) Data Sheet52V1.1, 2003-06 XC167Derivatives PreliminaryTable12 Current Limits for Port Output Drivers Maximum Output Current (IOLmax, -IOHmax)1)10 mA4.0 mA0.5 mA Nominal Output Current (IOLnom, -IOHnom)2.5 mA1.0 mA0.1 mA Electrical Parameters Port Output Driver ModeStrong driverMedium driverWeak driver 1) An output current above |IOXnom| may be drawn from up to three pins at the same time. For any group of 16 neighboring port output pins the total output current in each direction (ΣIOL and Σ-IOH)must remain below 50mA. Power Consumption XC167(Operating Conditions apply)Parameter Power supply current (active)with all peripherals activePad supply currentIdle mode supply currentwith all peripherals activeSleep and Power-down mode supply current caused by leakage4) Sleep and Power-down mode supply current caused by leakage and the RTC running, clocked by the main oscillator4) Symbol Limit Valuesmin. max. 15 +mA2.6 × fCPU5 mA 15 +mA1.2 × fCPU128,000× e-α mA 1)UnitTest Condition IDDIIDDPIIDXIPDL5)–––– fCPU in [MHz]2) 3) fCPU in [MHz]2)VDDI=VDDImax6)TJ in [°C] α = 4670/(273+TJ) IPDM7) – 0.6 +mA0.02×fOSC+ IPDL0.1+ IPDL mA VDDI=VDDImaxfOSC in [MHz]VDDI=VDDImax Sleep and Power-down mode IPDAsupply current caused by leakage and the RTC running, clocked by the auxiliary oscillator at 32kHz4) 1)2) – During Flash programming or erase operations the supply current is increased by max. 5mA. The supply current is a function of the operating frequency. This dependency is illustrated in Figure11. These parameters are tested at VDDImax and maximum CPU clock frequency with all outputs disconnected andall inputs at VIL or VIH. Data Sheet53V1.1, 2003-06 XC167Derivatives Preliminary 3) Electrical Parameters The pad supply voltage pins (VDDP) mainly provides the current consumed by the pin output drivers. A smallamount of current is consumed even though no outputs are driven, because the drivers’ input stages areswitched and also the Flash module draws some power from the VDDP supply. The total supply current in Sleep and Power-down mode is the sum of the temperature dependent leakagecurrent and the frequency dependent current for RTC and main oscillator or auxiliary oscillator (if active).This parameter is determined mainly by the transistor leakage currents. This current heavily depends on thejunction temperature (see Figure13). The junction temperature TJ is the same as the ambient temperature TAif no current flows through the port output drivers. Otherwise, the resulting temperature difference must betaken into account. All inputs (including pins configured as inputs) at 0V to 0.1V or at VDDP - 0.1V to VDDP, all outputs (includingpins configured as outputs) disconnected. This parameter is tested at 25°C and is valid for TJ ≥ 25°C.This parameter is determined mainly by the current consumed by the oscillator switched to low gain mode (seeFigure12). This current, however, is influenced by the external oscillator circuitry (crystal, capacitors). Thegiven values refer to a typical circuitry and may change in case of a not optimized external oscillator circuitry. 4) 5) 6) 7) Data Sheet54V1.1, 2003-06 XC167Derivatives Preliminary Electrical Parameters I [mA]IDDImax140120IDDItyp10080IIDXmax60IIDXtyp402010Figure11 203040fCPU [MHz]Supply/Idle Current as a Function of Operating Frequency Data Sheet55V1.1, 2003-06 XC167Derivatives Preliminary Electrical Parameters I [mA]3.02.01.0IPDMmaxIPDMtypIPDAmax4812160.132 kHzFigure12 fOSC [MHz]Sleep and Power Down Supply Current due to RTC and Oscillator running, as a Function of Oscillator Frequency IPDO [mA]1.5 1.0 0.5 -50 Figure13 050100150 TJ [°C] Sleep and Power Down Leakage Supply Current as a Function of Temperature Data Sheet56V1.1, 2003-06 XC167Derivatives Preliminary Electrical Parameters 4.6 Table13Parameter A/D Converter Characteristics A/D Converter Characteristics(Operating Conditions apply) Symbol Limit Valuesmin. max. 4.5SRSR UnitTest ConditionV 1)Analog reference supplyAnalog reference groundAnalog input voltage rangeBasic clock frequencyConversion time for 10-bit result4) Conversion time for 8-bit result4) Calibration time after resetTotal unadjusted errorTotal capacitanceof an analog inputSwitched capacitanceof an analog inputResistance of the analog input pathTotal capacitanceof the reference inputSwitched capacitanceof the reference inputResistance of the reference input path VAREFVAGNDVAINfBCtC10PtC10tC8PtC8tCALCAINTCAINSRAIN VDDP + 0.1 VSS - 0.1VSS + 0.1VVAREF 20 VMHz 2)3) SRVAGND 0.5 CC52×tBC + tS + 6×tSYS–CC40×tBC + tS + 6×tSYS–CC44×tBC + tS + 6×tSYS–CC32×tBC + tS + 6×tSYS–CC484 –CC –CC –CC –––CC 20151 pFpFkΩ 2 kΩ 10 pF 11,696±215 Post-calibr. onPost-calibr. offPost-calibr. onPost-calibr. off 5)1)6)6)tBC LSBpF TUECC– 6)6)6)CAREFT CCCC 6)CAREFSRAREF Data Sheet57V1.1, 2003-06 XC167Derivatives Preliminary 1) Electrical Parameters TUE is tested at VAREF=VDDP+0.1V, VAGND=0V. It is guaranteed by design for all other voltages withinthe defined voltage range. If the analog reference supply voltage drops below 4.5V (i.e. VAREF≥4.0V) or exceeds the power supplyvoltage by up to 0.2V (i.e. VAREF=VDDP+0.2V) the maximum TUE is increased to ±3LSB. This range is not100% tested. The specified TUE is guaranteed only, if the absolute sum of input overload currents on Port5 pins (see IOVspecification) does not exceed 10mA, and if VAREF and VAGND remain stable during the respective period oftime. During the reset calibration sequence the maximum TUE may be ±4LSB. 2) VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will be X000H or X3FFH, respectively. The limit values for fBC must not be exceeded when selecting the peripheral frequency and the ADCTC setting.This parameter includes the sample time tS, the time for determining the digital result and the time to load theresult register with the conversion result (tSYS = 1 / fSYS). Values for the basic clock tBC depend on programming and can be taken from Table14.When the post-calibration is switched off, the conversion time is reduced by 12 x tBC The actual duration of the reset calibration depends on the noise on the reference signal. Conversionsexecuted during the reset calibration increase the calibration time. The TUE for those conversions may beincreased. Not 100% tested, guaranteed by design and characterization. The given parameter values cover the complete operating range. Under relaxed operating conditions(temperature, supply voltage) reduced values can be used for calculations. At room temperature and nominalsupply voltage the following typical values can be used: CAINTtyp = 12pF, CAINStyp = 7pF, RAINtyp = 1.5kΩ, CAREFTtyp = 15pF, CAREFStyp = 13pF, RAREFtyp = 0.7kΩ. 3)4) 5) 6) RSourceVAINCExtRAIN, OnCAINT - CAINSA/D Converter=CAINSmcs04879_p.vsdFigure14Equivalent Circuitry for Analog Inputs Data Sheet58V1.1, 2003-06 XC167Derivatives Preliminary Electrical Parameters Sample time and conversion time of the XC167’s A/D Converter are programmable. Incompatibility mode, the above timing can be calculated using Table14.The limit values for fBC must not be exceeded when selecting ADCTC.Table14 A/D Converter Computation Table1) A/D ConverterBasic Clock fBC ADCON.13|12Sample time(ADSTC)tS00011011 ADCON.15|14 (ADCTC)00011011 1) fSYS / 4fSYS / 2fSYS / 16fSYS / 8tBC × 8tBC × 16tBC × 32tBC × 64 These selections are available in compatibility mode. An improved mechanism to control the ADC input clockcan be selected. Converter Timing Example:Assumptions:Basic clockSample timeConversion 10-bit:With post-calibr.Post-calibr. offConversion 8-bit:With post-calibr.Post-calibr. off fSYSfBCtS = 40MHz (i.e. tSYS = 25ns), ADCTC = ‘01’, ADSTC = ‘00’.= fSYS / 2 = 20MHz, i.e. tBC = 50ns.= tBC × 8 = 400ns. tC10P= 52 × tBC + tS + 6 × tSYS = (2600 + 400 + 150) ns = 3.15µs.tC10= 40 × tBC + tS + 6 × tSYS = (2000 + 400 + 150) ns = 2.55µs.tC8PtC8 = 44 × tBC + tS + 6 × tSYS = (2200 + 400 + 150) ns = 2.75µs.= 32 × tBC + tS + 6 × tSYS = (1600 + 400 + 150) ns = 2.15µs. Data Sheet59V1.1, 2003-06 XC167Derivatives Preliminary Timing Parameters 5 5.1 Timing Parameters Definition of Internal Timing The internal operation of the XC167 is controlled by the internal master clock fMC.The master clock signal fMC can be generated from the oscillator clock signal fOSC viadifferent mechanisms. The duration of master clock periods (TCMs) and their variation(and also the derived external timing) depend on the used mechanism to generate fMC.This influence must be regarded when calculating the timings for the XC167. Phase Locked Loop Operation (1:N) fOSCfMC TCM Direct Clock Drive (1:1) fOSCfMC TCM Prescaler Operation (N:1) fOSCfMC TCM Figure15Generation Mechanisms for the Master Clock Note:The example for PLL operation shown in Figure15 refers to a PLL factor of 1:4,the example for prescaler operation refers to a divider factor of 2:1.The used mechanism to generate the master clock is selected by register PLLCON.CPU and EBC are clocked with the CPU clock signal fCPU. The CPU clock can have thesame frequency as the master clock (fCPU = fMC) or can be the master clock divided bytwo: fCPU = fMC / 2. This factor is selected by bit CPSYS in register SYSCON1.The specification of the external timing (AC Characteristics) depends on the period of theCPU clock, called “TCP”. The other peripherals are supplied with the system clock signal fSYS which has the samefrequency as the CPU clock signal fCPU. Data Sheet 60 V1.1, 2003-06 XC167Derivatives PreliminaryBypass Operation When bypass operation is configured (PLLCTRL=0xB) the master clock is derived fromthe internal oscillator (input clock signal XTAL1) through the input- and output-prescalers: Timing Parameters fMC = fOSC / ((PLLIDIV+1)×(PLLODIV+1)). If both divider factors are selected as ’1’ (PLLIDIV = PLLODIV = ’0’) the frequency of fMCdirectly follows the frequency of fOSC so the high and low time of fMC is defined by theduty cycle of the input clock fOSC. The lowest master clock frequency is achieved by selecting the maximum values for bothdivider factors: fMC = fOSC / ((3+1)×(14+1)) = fOSC / 60. Phase Locked Loop (PLL) When PLL operation is configured (PLLCTRL = 11B) the on-chip phase locked loop isenabled and provides the master clock. The PLL multiplies the input frequency by thefactor F (fMC = fOSC × F) which results from the input divider, the multiplication factor,and the output divider (F = PLLMUL+1 / (PLLIDIV+1 × PLLODIV+1)). The PLL circuitsynchronizes the master clock to the input clock. This synchronization is done smoothly,i.e. the master clock frequency does not change abruptly. Due to this adaptation to the input clock the frequency of fMC is constantly adjusted so itis locked to fOSC. The slight variation causes a jitter of fMC which also affects the durationof individual TCMs. The timing listed in the AC Characteristics refers to TCPs. Because fCPU is derived fromfMC, the timing must be calculated using the minimum TCP possible under the respectivecircumstances. The actual minimum value for TCP depends on the jitter of the PLL. As the PLL isconstantly adjusting its output frequency so it corresponds to the applied input frequency(crystal or oscillator) the relative deviation for periods of more than one TCP is lower thanfor one single TCP (see formula and Figure16). This is especially important for bus cycles using waitstates and e.g. for the operation oftimers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse traingeneration or measurement, lower baudrates, etc.) the deviation caused by the PLL jitteris negligible. The value of the accumulated PLL jitter depends on the number of consecutive VCOoutput cycles within the respective timeframe. The VCO output clock is divided by theoutput prescaler (K = PLLODIV+1) to generate the master clock signal fMC. Therefore,the number of VCO cycles can be represented as K×N, where N is the number ofconsecutive fMC cycles (TCM). Data Sheet61V1.1, 2003-06 XC167Derivatives Preliminary Timing Parameters For a period of N×TCM the accumulated PLL jitter is defined by the deviation DN:DN [ns] = ±(1.5 + 6.32×N/fMC); fMC in [MHz], N = number of consecutive TCMs.So, for a period of 3TCMs @ 20MHz and K=12: D3 = ±(1.5 + 6.32×3/20) = 2.448 ns.This formula is applicable for K×N < 95. For longer periods the K×N=95 value can beused. This steady value can be approximated by: DNmax [ns] = ±(1.5 + 600/(K×fMC)). Acc. jitter DNns±8±7±6±5±4±3±2±1010 MHzK=15K=12K=10K=8K=6K=5HzM 20Hz40 M1510152025Nmcb04413_xc.vsdFigure16Approximated Accumulated PLL Jitter Note:The bold lines indicate the minimum accumulated jitter which can be achieved byselecting the maximum possible output prescaler factor K.Different frequency bands can be selected for the VCO, so the operation of the PLL canbe adjusted to a wide range of input and output frequencies: Table1500011011 1) VCO Bands for PLL Operation1) Base Frequency Range20 … 80 MHz40 … 130 MHz60 … 180 MHz 100 … 150 MHz150 … 200 MHz200 … 250 MHzReserved PLLCON.PLLVBVCO Frequency Range Values guaranteed by design characterisation. Data Sheet62V1.1, 2003-06 XC167Derivatives Preliminary Timing Parameters 5.2 Table16Parameter External Clock Drive XTAL1 External Clock Drive Characteristics(Operating Conditions apply) Symbol Limit Valuesmin. max.2501)––88 nsnsnsnsns 2066–– Unit Oscillator periodHigh time2)Low time2)Rise time2)Fall time2) 1)2) tOSCt1t2t3t4 SRSRSRSRSR The maximum limit is only relevant for PLL operation to ensure the minimum input frequency for the PLL.The clock input signal must reach the defined levels VILC and VIHC. t10.5VDDIt3t4VIHCVILCt2tOSCMCT05138Figure17External Clock Drive XTAL1 Note:If the on-chip oscillator is used together with a crystal or a ceramic resonator, theoscillator frequency is limited to a range of 4MHz to 16MHz.It is strongly recommended to measure the oscillation allowance (negativeresistance) in the final target system (layout) to determine the optimumparameters for the oscillator operation. Please refer to the limits specified by thecrystal supplier.When driven by an external clock signal it will accept the specified frequencyrange. Operation at lower input frequencies is possible but is guaranteed bydesign only (not 100% tested).Data Sheet63V1.1, 2003-06 XC167Derivatives Preliminary Timing Parameters 5.3Testing Waveforms Input signal(driven by tester)Output signal(measured)2.0 V0.8 V0.45 VFigure18Input Output Waveforms VLoad+ 0.1 VTimingReferencePointsVOH- 0.1 VVLoad- 0.1 VVOL+ 0.1 VFor timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs,but begins to float when a 100 mV change from the loadedVOH/VOLlevel occurs (IOH/IOL= 20 mA).MCA00763Figure19Float Waveforms Data Sheet64V1.1, 2003-06 XC167Derivatives Preliminary Timing Parameters 5.4 Table17Parameter AC Characteristics CLKOUT Reference Signal Symbol min. Limits max. nsnsnsnsns ––4440/30/251)86–– Unit CLKOUT cycle timeCLKOUT high timeCLKOUT low timeCLKOUT rise timeCLKOUT fall time 1) tc5 CCtc6 CCtc7 CCtc8 CCtc9 CC The CLKOUT cycle time is influenced by the PLL jitter (given values apply to fCPU = 25/33/40 MHz).For longer periods the relative deviation decreases (see PLL deviation formula). tc5CLKOUTtc6tc7tc8tc9MCT04415Figure20CLKOUT Signal Timing Data Sheet65V1.1, 2003-06 XC167Derivatives Preliminary Variable Memory Cycles External bus cycles of the XC167 are executed in five subsequent cycle phases (AB, C,D, E, F). The duration of each cycle phase is programmable (via the TCONCSxregisters) to adapt the external bus cycles to the respective external module (memory,peripheral, etc.). The duration of the access phase can optionally be controlled by the external module viathe READY handshake input. This table provides a summary of the phases and the respective choices for theirduration. Table18 Programmable Bus Cycle Phases (see timing diagrams) Parameter Valid ValuesUnit1 … 2 (5) TCP Bus Cycle Phase Timing Parameters Address setup phase, the standard duration of this tpAB phase (1 … 2 TCP) can be extended by 0 … 3 TCP if the address window is changedCommand delay phase Write Data setup / MUX Tristate phaseAccess phase Address / Write Data hold phase tpCtpDtpEtpF 0 … 3 0 … 1 1 … 32 0 … 3 TCPTCPTCPTCP Note:The bandwidth of a parameter (minimum and maximum value) covers the wholeoperating range (temperature, voltage) as well as process variations. Within agiven device, however, this bandwidth is smaller than the specified range. This isalso due to interdependencies between certain parameters. Some of theseinterdependencies are described in additional notes (see standard timing). Data Sheet66V1.1, 2003-06 XC167Derivatives PreliminaryTable19Parameter Output valid delay for:RD, WR(L/H)Output valid delay for:A23…A16, BHE, ALEOutput valid delay for:A15…A0 (on PORT1)Output valid delay for:A15…A0 (on PORT0)Output valid delay for:CSOutput valid delay for:D15…D0 (write data, mux-mode)Output valid delay for:D15…D0 (write data, demux-mode)Output hold time for:RD, WR(L/H)Output hold time for:A23…A16, BHE, ALEOutput hold time for:A15…A0 (on PORT0)Output hold time for:CSOutput hold time for:D15…D0 (write data)Input setup time for:READY, D15…D0 (read data)Input hold timeREADY, D15…D0 (read data)1) 1) Timing Parameters External Bus Cycle Timing (Operating Conditions apply) Symbol Limitsmin. max.13716161417173813313–– nsnsnsnsnsnsnsnsnsnsnsnsnsnsUnit tc10 CC1tc11 CC-1tc12 CC1tc13 CC3tc14 CC1tc15 CC3tc16 CC3tc20 CC-3tc21 CC0tc23 CC1tc24 CC-3tc25 CC1tc30 SR24tc31 SR-5 Read data are latched with the same (internal) clock edge that triggers the address change and the rising edgeof RD. Therefore address changes before the end of RD have no impact on (demultiplexed) read cycles. Readdata can be removed after the rising edge of RD.Note:The shaded parameters have been verified by characterization.They are not 100% tested.Data Sheet67V1.1, 2003-06 XC167Derivatives Preliminary tpAB CLKOUT tc11 ALE tc21tpC tpD tpE tpF Timing Parameters A23-A16,BHE, CSxtc11|tc14High Addresstc10 RDWR(L/H)tc13 AD15-AD0 (read) tc13 AD15-AD0 (write) Low AddressLow Addresstc23 tc30 tc20 tc31 Data Intc15 Data Outtc25 Figure21Multiplexed Bus Cycle Data Sheet68V1.1, 2003-06 XC167Derivatives Preliminary tpAB CLKOUT tc11 ALE tc21tpC tpD tpE tpF Timing Parameters A23-A0,BHE, CSxtc11|tc14Addresstc10 RDWR(L/H)tc30 D15-D0(read) tc16 D15-D0(write) tc20 tc31 Data Intc25 Data OutFigure22Demultiplexed Bus Cycle Data Sheet69V1.1, 2003-06 XC167Derivatives Preliminary Bus Cycle Control via READY Input The duration of an external bus cycle can be controlled by the external circuitry via theREADY input signal. The polarity of this input signal can be selected. Synchronous READY permits the shortest possible bus cycle but requires the inputsignal to be synchronous to the reference signal CLKOUT. Asynchronous READY puts no timing constraints on the input signal but incurs onewaitstate minimum due to the additional synchronization stage. The minimum durationof an asynchronous READY signal to be safely synchronized must be one CLKOUTperiod plus the input setup time. An active READY signal can be deactivated in response to the trailing (rising) edge ofthe corresponding command (RD or WR).If the next following bus cycle is READY-controlled, an active READY signal must bedisabled before the first valid sample point for the next bus cycle. This sample pointdepends on the programmed phases of the next following cycle. Timing Parameters Data Sheet70V1.1, 2003-06 XC167Derivatives Preliminary tpDCLKOUTtpEtpRDYtpFTiming Parameters tc10RD, WRtc20tc30D15-D0(read)Data Intc31tc25D15-D0(write)Data Outtc30tc31tc30tc31READYSynchronousNot RdyReadytc30tc31tc30tc31READYAsynchron.Not RdyReadyFigure23READY Timing Note:If the READY input is sampled inactive at the indicated sampling point (“Not Rdy”)a READY-controlled waitstate is inserted (tpRDY),sampling the READY input active at the indicated sampling point (“Ready”)terminates the currently running bus cycle.Note the different sampling points for synchronous and asynchronous READY.This example uses one mandatory waitstate (see tpE) before the READY input isevaluated.Data Sheet71V1.1, 2003-06 XC167Derivatives Preliminary External Bus ArbitrationTable20ParameterInput setup time for:HOLD inputOutput delay rising edge for:HLDA, BREQOutput delay falling edge for:HLDABus Arbitration Timing (Operating Conditions apply) Symbol min. Limits max.–610 nsnsns 1511 Unit Timing Parameters tc40SRtc41CCtc42CC Data Sheet72V1.1, 2003-06 XC167Derivatives Preliminary Timing Parameters CLKOUTtc40HOLDtc42HLDABREQ2)tc10|tc14CSx, RD,WR(L/H)3)Addr, Data,BHE1)Figure24External Bus Arbitration, Releasing the Bus Notes1) The XC167 will complete the currently running bus cycle before granting bus access.2)This is the first possibility for BREQ to get active.3) The control outputs will be resistive high (pullup) after being driven inactive (ALE will be low). Data Sheet73V1.1, 2003-06 XC167Derivatives Preliminary 3)Timing Parameters CLKOUTtc40HOLDtc41HLDAtc41BREQ1)tc10|tc14CSx, RD,WR(L/H)2)tc11|tc12|tc13|tc15|tc16Addr, Data,BHEFigure25External Bus Arbitration, (Regaining the Bus) Notes1) This is the last chance for BREQ to trigger the indicated regain-sequence.Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going high.Please note that HOLD may also be deactivated without the XC167 requesting the bus.2) The control outputs will be resistive high (pullup) before being driven inactive (ALE will be low).3)The next XC167 driven bus cycle may start here. Data Sheet74V1.1, 2003-06 XC167Derivatives Preliminary Packaging 6Packaging P-TQFP-144-19(Plastic Metric Quad Flat Package)0.1±0.051.4±0.051.6 MAX.0.12-+00..0038H0.6±0.150.50.22±0.052)17.5C0.08MA-BDC144x22201)0.080.2A-BD144x0.2A-BDH4xDAB201)1441Index Marking1)2)Does not include plastic or metal protrusion of 0.25 max. per sideDoes not include dambar protrusion of 0.08 max. per sideFigure26 Package Outlines P-TQFP-144-19 Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted DeviceData Sheet 75 22Dimensions in mm V1.1, 2003-06 7˚MAX.http://www.infineon.com Published by Infineon Technologies AG 因篇幅问题不能全部显示，请点此查看更多更全内容