MNL-1100 | 2021.03.09
23.3.1. Clocks
Table 199.
Timers Clock Characteristics
Timers
System timer 0System timer 1SP timer 0SP timer 1
System Clock
Notes_
sys_timer0sys_timer1sp_timer0sp_timer1
l4_sys_free_clk
l4_sp_clk
Timers must be disabledif clock frequencychanges
The timers above are labeled according to the clock they receive. The system timersare connected to the L4_SYS bus and clocked by the l4_sys_free_clk. The SPtimers are connected to the L4_SP bus and clocked by l4_sp_clk.
SP timer 0 and SP timer 1 must be disabled before l4_sp_clk is changed to anotherfrequency. You can then re-enable the timer once the clock frequency change takeseffect.
Related Information
Clock Manager on page 154
For more information about clock performance, refer to the Clock Manager chapter.
23.3.2. Resets
The timers are reset by a cold or warm reset. Resetting the timers produces thefollowing results in the following order:1.2.3.4.
The timer is disabled.The interrupt is enabled.
The timer enters free-running mode.
The timer count load register value is set to zero.
23.3.3. Interrupts
The timer1 interrupt status (timer1intstat) and timer1 end of interrupt
(timer1eoi) registers handle the interrupts. The timer1intstat register allowsyou to read the status of the interrupt. Reading from the timer1eoi register clearsthe interrupt. †
The timer1 control register (timer1controlreg) contains the timer1 interrupt maskbit (timer1_interrupt_mask) to mask the interrupt. In both the free-running anduser-defined count modes of operation, the timer generates an interrupt signal whenthe timer count reaches zero and the interrupt mask bit of the control register is high.If the timer interrupt is set, then it is cleared when the timer is disabled.
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23.Timers
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23.4. Timers Programming Model
23.4.1. Initialization
To initialize the timer, perform the following steps: †1.
Initialize the timer through the timer1controlreg register: †—
Disable the timer by writing a 0 to the timer1 enable bit (timer1_enable) ofthe timer1controlreg register. †
Note: Before writing to a timer1 load count register (timer1loadcount), you
must disable the timer by writing a 0 to the timer1_enable bit of the
timer1controlreg register to avoid potential synchronization problems. †—
Program the timer mode:———
user-defined count—write 1 to the timer1 mode bit (timer1_mode) of thetimer1controlreg register. †
free-running—write 0 to the timer1 mode bit (timer1_mode) of thetimer1controlreg register. †
Set the interrupt mask as either masked or not masked by writing a 1 or 0,respectively, to the timer1_interrupt_mask bit of thetimer1controlreg register. †
2.3.
Load the timer counter value into the timer1loadcount register. †Enable the timer by writing a 1 to the timer1_enable bit of thetimer1controlreg register. †
23.4.2. Enabling the Timers
When a timer transitions to the enabled state, the current value oftimer1loadcount register is loaded into the timer counter. †1.
To enable the timer, write a 1 to the timer1_enable bit of thetimer1controlreg register.
23.4.3. Disabling the Timers
When the timer enable bit is cleared to 0, the timer counter and any associatedregisters in the timer clock domain, are asynchronously reset. †1.
To disable the timer, write a 0 to the timer1_enable bit. †
23.4.4. Loading the Timers Countdown Value
When a timer counter is enabled after being reset or disabled, the count value isloaded from the timer1loadcount register; this occurs in both free-running anduser-defined count modes. †
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When a timer counts down to 0, it loads one of two values, depending on the timeroperating mode: †•
User-defined count mode—timer loads the current value of the
timer1loadcount register. Use this mode if you want a fixed, timed interrupt.Designate this mode by writing a 1 to the timer1_mode bit of thetimer1controlreg register. †
Free-running mode—timer loads the maximum value (0xFFFFFFFF). The timer maxcount value allows for a maximum amount of time to reprogram or disable thetimer before another interrupt occurs. Use this mode if you want a single timedinterrupt. Enable this mode by writing a 0 to the timer1_mode bit of thetimer1controlreg register. †
•
23.4.5. Servicing Interrupts
23.4.5.1. Clearing the Interrupt
An active timer interrupt can be cleared in two ways.1.
If you clear the interrupt at the same time as the timer reaches 0, the interruptremains asserted. This action happens because setting the timer interrupt takesprecedence over clearing the interrupt. †
To clear an active timer interrupt, read the timer1eoi register or disable thetimer. When the timer is enabled, its interrupt remains asserted until it is clearedby reading the timer1eoi register. †
2.
23.4.5.2. Checking the Interrupt Status
You can query the interrupt status of the timer without clearing its interrupt.1.
To check the interrupt status, read the timer1intstat register. †
23.4.5.3. Masking the Interrupt
The timer interrupt can be masked using the timer1controlreg register.To mask an interrupt, write a 1 to the timer1_interrupt_mask bit of thetimer1controlreg register. †
23.5. Timers Address Map and Register Definitions
You can access the complete HPS address map and register definitions through thefollowing:••
Intel Agilex Hard Processor System Address Map and Register Definitions (HTML)Intel Agilex Hard Processor System Address Map and Register Definitions (ZIP)
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