电气专业英语论文

院系名称： 电气工程学院 专业班级: 电气F1103班 学生姓名： 学 号：

附 件： 1.中文论文；2.外文论文。 成绩评定： 年 月 日

绝缘栅双极晶体管

亚历克斯问黄

1(1.弗吉尼亚理工学院暨州立大学，美国 弗吉尼亚州)

摘要：通过对门极可关断晶闸管的产生背景，物理结构及其基本的工作原理的进一步探讨和研究，可 以得出门极可关断晶闸管具有在门极施加负的脉冲电流使其关断的性能，并证明它是全控型器件。 关键词：门极可关断晶闸管； 工作原理； 单位关断增益； 动态特性； 静态特性；

1 引言

在20世纪50年代发明的可控硅整流器（SCR）【1】是第一个被投入使用的功率半导体开关。SCR是一个闭锁装置，只有ON和OFF两个稳定状态。通过很小的门极触发电流使其从OFF状态转换成ON状态的正反馈过程来启动装置。由于电子和空穴的注入，提供了强有力地电导调制，使得SCR能很好地权衡正向压降和阻断电压。另外从制造的角度看，SCR的结构很简单，因为它的门极可以被放置在一个小的区域，因此单一的SCR可以很容易地被扩展以增加设备的电流能力而没有太多的处理问题。然而可控硅不能通过门极控制其关断。

由于SCR的关断可控性的限制，门极可关断晶闸管（GTO）【2】后来得到发展。正如它的名称所表示的，GTO是一种通过门极控制其关断的装置。它的基本结构与SCR非常相似。然而在GTO中许多门极被放置在阴极的周围，这样在关断期间，闩锁机制可以通过门极控制来解除。因此GTO是全控型器件。到今天为止，GTO具有最高的额定功率和在阻断电压及任何全控开关导通损耗的最佳折衷。然而其动态性能很差，GTO在导通和关断时不快。它缺乏FBSOA且RBSOA较差，因此它需要缓冲器控制关断转换期间dv/dt的和导通转变期间的di/dt。

GTO晶闸管是全控型的功率半导体开关之一。它的功率应用范围从早期的低功率（低于100W）到数百兆瓦的高功率。一个最先进的GTO可在硅片上制成6英寸大小。其电流高达6.0KA，电压高达6.0KV.【3】该等级高于其他全控设备等级。

GTO的静态参数很好：具有传导低损耗，高阻断电压且由于集成化成本很低。但其动态性能很差。其关断和开通运行期间分别对dv/dt和di/dt

缓冲的要求及最小量的开通和关断次数使得GTO难以使用。要提高GTO的动态性能，同时保持其良好的静态性能，很好地了解GTO的结构是必要的。在本章节我们将总结和讨论GTO的基本工作原理，其优点和缺点及决定其性能的结构。然后引入一个新的门极驱动概念，即单位关断增益。并分析和讨论这种新的驱动方法的优点。最后将总结已知的这种特殊驱动技术的使用方法。

2正文

2.1GTO的正向传导

图1.75a为一个典型的高功率GTO的微型结构和掺杂分布。图1.75b显示了两个晶体管GTO模型图。图1.75c是一幅4英寸的GTO图片。这是一个三端四层的PNPN结构。外部的p+层上的电极成为阳极，其电流通常流入设备。外部n+层上的电极称为阴极，内部的p层上的电极称为门极，被用作控制。

图1.75：（a）GTO元的结构和它的掺杂分布（b）晶闸管的双晶体管

模型 (c)4英寸GTO的外形

通过图1.75b所示的等效电路模型来理解GTO的工作原理。PNP晶体管代表GTO的最高三层，而NPN晶体管代表GTO底部的三层。由于n层作为pnp型的基极，npn型的集电极和内部的p层作为npn型的基极，pnp型的集电极使得两个晶体管交叉耦合。这种结构具有两个稳定状态：ON和OFF，这是由门控制。当电流从门-阴极注入GTO时，npn结构导通，它的集电极电流通过J1结流入GTO的阳极。由于J1是pnp结构的发射结，PNP型的集电极电流是npn的基极电流。因此，两个晶体管提供基极电流给对方，形成正反馈。直到他们达到自我维持的状态，俗称闭锁。高层次的少数载流子的注入可在锁定状态下从阳极到阴极，使得所有三个pn结正向偏置。因此，从阳极到阴极存在高导电性，使高电流从阳极流动到阴极。图1.76所示为其导通过程。

图1.76 GTO导通及电流维持过程

在芯片级，J3结导通导致电子注入p基区。这些电子从p基极扩散，大多由反向偏置连接点J2结收集。为保持电流的连续性，结点J1处将供给电流，通过将空穴注入n区域。这些空穴的一部分，将扩散的n-区，并被J2结收集，导致在J3结流入更多的电子。当两个晶体管工作在足够的电流增益，一个正反馈机制是足以导致闭锁。

让npn和pnp的基极电流增益分别为apnp和anpn。通常情况，αpnp低于anpn。因为pnp是宽基结构。电流流进GTO如图1.77所示。在J2结，电流由阴极侧注入是npnIK；由阳极侧注入是pnpIA。漏电流为IL。

图1.77 驱动电流流进GTO图

晶闸管结构可以维持其本身的阳极电流，只要两个晶体管共同的基极电流增益（αpnp +

αnpn）之和趋近一致。对GTO ，αnpn设计的低，通常是为IG ，以确保其门极关断能力。这将在稍后讨论。与此自持能力，GTO的栅极并不需要提供很多电流，不需要非常接近其阴极不像在双极结型晶体（BJT）设计是必要的。一个典型的GTO元，示于图1.75.其维数是100〜150 微米宽。这相比微米和/或亚微米工艺被用于现代化的MOSFET和绝缘栅双极型晶体管（IGBT）是非常大的 。大细胞大小的设计是符合成本效益的，并且使得可以制造大单芯片器件，以提高他们目前的能力。一个国家的最先进的GTO模具的直径是6英寸大。其关断电流能力可达6.0KV【4】。图1.75显示的巨大的GTO是由ABB制造的。显示的GTO是一个4英寸硅晶片由成千上万的如图1.75所示的GTO元和所谓的压装或曲棍球冰球包中打包组成。

GTO的大细胞结构在开通过渡期间带来了电流扩展问题。当注入门极电流，首先发生在导通的门极附近。导通区域扩散在阴极的其余部分。这可以由称为扩展速度【5】的驱动速度定性。实验测量【6】出典型的扩展速度是5000厘米/秒。该速度也依赖于对GTO的设计参数，注入门极的导通电流及diG/dt。

由于这个扩展的速度，整个GTO元导通需要一段时间。为了避免过分强调首先开启的单元格的部分，阳极电流的增加率应加以限制。给GTO设定最大导通di / dt的限制。

GTO的主要优点是它的低正向压降和高电压阻断能力。这些可以被理解为两端的少数载流子注入机制的主要好处。对于高电压的GTO，厚且轻掺杂n基极是必要的（见图1.75）。正向电压在这种情况下，主要取决于由电阻电压降的电压阻挡区少数载流子发挥了重要作用。

图1.78（a）GTO和（b）IGBT电压阻挡区导通状态的少数载流子分布

图1.78a所示是GTO中n-区的少数载流子的分

布。 图1.78b是一个IGBT的情况。对于设计相同的阻断电压，它们的n区应该有类似厚度和掺杂。由于只有一个晶体管的IGBT结构中，少数载流子的只能从一侧注入，因此，比对GTO在n-区的电导率调制弱。在GTO，因为有两个晶体管，少数载流子被注入两端，使得整个区域中的更均匀的等离子体分布。对于4.5千伏状态的的艺术GTO，其正向压降为50 A/cm2的电流密度可低至2.0 V[7]如果一个常数栅极电流注入呈现。图1.79显示了一个国家的最先进的GTO的通态特性由ABB生产的。正向电压降是在2000A只有大约1.5 V，4.5千伏GTO。此结果是典型的低导通损耗GTO。

2.2 GTO元之间的非均匀关断过程

对于高功率GTO，实验获得的关断瞬间功率，可以承受远远低于动态雪崩击穿所设置的值如式（1.21）。所以从GTO需要的dV / dt缓冲来塑造其关断的I-V的轨迹，如图1.72示，可以应用降低最大平均瞬时功率的外部电路。非均匀的电流分布或电流丝[在GTO元中受到关断运行的限制。电流丝在关断开始时形成，这是由存储时间的差异，或在关断时的电压和电流都高的动态雪崩所造成的结果。

参考文献

1. S.K. Gandhi, Semiconductor Power Devices, Wiley,

New York, 1977.

2. E.D. Wolley, Gate Turn-Off in P-N-P-N devices, IEEE Trans. Electron Devices, ED-13, 590–597, 1966. 3. Mitsubishi GTO FG6000AU-120D data sheet. 4. B.J. Baliga, Power Semiconductor Devices, PWS Publishing Company, Boston, 1996.

5. W.H. Dodson and R.L. Longini, Probed determination of turn-on spread of large area thyristors,

IEEE Trans. Electron Devices, ED-13, 478–484, 1966. 6. H.J. Ruhl, Spreading velocity of the active area

boundary in a thyristor, IEEE Trans. Electron Devices, ED-17, 672–680,1970.

Gate Turn-Off Thyristors

Alex Q. Huang

(1. Virginia Polytechnic Institute and State University，America Virginia) Abstract- Through the background of the gate turn-off (GTO) thyristor, the physical structure and basic working principle of further exploration and research, it can be concluded that a GTO is a device that can be turned off through its gate injecting a gate negative pulse current. It is proved to be a full-controlled device.

Key words: Gate Turn-Off Thyristor; Unity-gain turn-off; Basic working; Dynamic characteristic; Static performance 门极可关断晶闸管 单位关断增益 基本工作原理 动态特性 静态特性

I.

INTRODUCTION

The first power semiconductor switch that was put in use was the silicon controllable rectifier (SCR) [1] invented in 1950s. The SCR is a latch-up device with only two stable states: ON and OFF. It does not have FBSOA. It can be switched from OFF to ON by issuing a command in the form of a small gatetriggering current. This will initiate a positive-feedback process that will eventually turn the device on.. The SCR has a good trade-off between its forward voltage drop and blocking voltage because of the strong conductivity modulation provided by the injections of both electrons and holes. Moreover, the structure of an SCR is very simple from a manufacturing point of view because its gate can be placed at one small region. The size of a single SCR can therefore be easily expanded to increase the current capability of the device without too many processing problems. There are 8.0 kA/10.0 kV SCRs commercially available that use a 6-in. silicon wafer for current conduction. However, SCRs cannot be turned off through their gate controls.

Because of the limitation of the turn-off controllability of the SCR, the gate turn-off (GTO) thyristor [2] was subsequently developed. As its name denotes, a GTO is a device that can be turned off through its gate control. Its basic structure is very similar to that of an SCR. However, many gate fingers are placed in the GTO surrounding its cathode. During a turn-off operation, the latch-up mechanism can be broken through the gate control. A GTO is thus a device with full gate control and similar high current–voltage rating of an SCR. To date, the GTO has the highest power rating and the best trade-off between the blocking voltage and the conduction loss of any fully controllable switch. However, the dynamic performance of GTOs is poor.

A GTO is slow in both turn-on and turn-off. It lacks FBSOA and has poor RBSOA so it requires snubbers to control dV/dt during the turn-off transition and dI/dt during turn-on transition.

The GTO thyristor was one of the very first power semiconductor switches with full gate control. It has served many power applications ranging from low power (below 100 W) in its early years to high power up to hundreds of megawatts. A state-of-the-art GTO can be fabricated on a silicon wafer as big as 6 in. and can be rated up to 6.0 kA and 6.0 kV [3]. This rating is much higher than the ratings of any other fully controllable devices.

The GTO static parameters are excellent: low conduction loss due to its double-sided minority carrier injection, high blocking voltage, and low cost due to its fabrication on a large single wafer. However, its dynamic performance is poor. The requirements of a dV/dt snubber during turn-off operation, a dI/dt snubber during turn-on operation, and minimum on and off times make the GTO difficult to use. To improve the dynamic performance of the GTO while keeping its good static performance, a better understanding of the mechanism of the GTO is necessary. In this section, the basic operating principle of the GTO, its advantages and disadvantages, and the mechanism that determines its performance are summarized and discussed. A new gate-driving concept, namely, unity-gain turn-off, is then introduced. The advantages of this special driving method are analyzed and discussed. Finally, all known approaches that make use of this special driving technique are summarized.

II.

GTO FORWARD CONDUCTION

Figure 1.75a illustrates the cell structure and

the doping profile of a typical high power GTO. Figure 1.75b shows the two-transistor GTO model; and Fig. 1.75c is a photograph of a 4-in. GTO along with its gate lead. The structure is a three-terminal, four-layer pnpn structure with a lightly doped n− voltage-blocking layer in the center [4]. The electrode on the external p+ layer is called the anode where the current normally flows into the device. The electrode on the external n+ layer is called the cathode from where the current normally flows out. The electrode on the internal p layer (p-base) is called the gate, which is used for control.

FIGURE 1.75 (a) GTO cell structure and its doping profile; (b) The two-transistor GTO model; (c) a photograph of a 4-in.

GTO along with its gate lead.

The operating principle of a GTO can be understood through its equivalent circuit model shown in Fig. 1.75b. The pnp transistor represents the top three layers of the GTO, whereas the npn transistor represents the bottom three layers of the GTO. Since the n− layer serves as the base of the pnp and the collector of the npn, and the internal p layer serves as the base of the npn and the collector of the pnp, the two transistors are cross-coupled. This structure has two stable states: ON and OFF, which are determined by its gate control. When a current is injected into the GTO from its gate to its cathode, the npn structure is turned on and its collector current flows from the anode of the GTO through J1 junction. Since J1 is the emitter junction of the pnp structure, the collector current of the pnp is then the base current of the npn. The two transistors therefore provide base currents to each other, forming a positive feedback among them until they reach a self-sustaining state commonly known as latch-up

or latched. Under the latched condition, high-level minority carrier injections are available from the anode to the cathode, with all three pn junctions forward-biased. A high conductivity therefore exists from anode to cathode, allowing high current to flow from the anode to the cathode. Figure 1.76 illustrates this turn on process.

FIGURE 1.76 Turn-on and current-sustaining process in

a GTO.

At the silicon level, the turn-on of junction J3 results in the injection of electrons into the p-base region. These electrons diffuse across the p-base and are mostly collected by the reverse biased junction J2. To maintain the continuity of the current, junction J1 will supply a current by injecting holes into the n− region. Part of these holes will diffuse across the n− region and are collected by junction J2, resulting in more electron injection from junction J3. When both transistors operate at sufficient current gain, a positive feedback mechanism is sufficient to result in latch-up.

Let the common base current gain of the pnp and npn be αpnp and αnpn, respectively. Normally, αpnpP is lower than αnpn since the pnp is a wide-base structure. The current flow inside a GTO is illustrated in Fig. 1.77. At junction J2, the current due to cathode side injection is αnpnIK; the current due to anode side injection is αpnpIA; and the leakage current is IL. According to Kirchhoff’s law.

FIGURE 1.77 Current flow in a GTO with gate drive

current.

This equation shows that the thyristor structure can sustain its anode current by itself

once the sum of the common base current gain (αpnp + αnpn) of both transistors is approaching unity. For a GTO, αnpn is designed low and is normally depending on IG to ensure its gate turn-off capability. This will be discussed later. With this self-sustaining capability, the gate of a GTO does not need to supply a lot of current and does not need to be very close to its cathode as is necessary in a bipolar junction transistor (BJT) design. The dimension of a typical GTO cell shown in Fig. 1.75 is 100 to 150 μm wide. This is very large compared with the micron and/or even submicron process used for modern MOSFETs and insulated gate bipolar transistors (IGBTs). The large cell size design is cost-effective and makes it possible to fabricate large single-die devices to boost their current capability. A state-of-the-art GTO die is as large as 6-in. in diameter with a turn-off current capability of up to 6.0 kA [3]. Figure 1.75c shows a large GTO fabricated by ABB. The GTO shown is fabricated on a 4-in. silicon wafer consisting of thousands of cells like the one shown in Fig. 1.75 and packaged in a so-called press-pack or hockey-puck package.

The large cell structure in the GTO introduces a current spreading problem during the turn-on

transition of a GTO. When a gate current is injected, the turn-on occurs first in the vicinity of the gate contact. The conduction area then spreads across the rest of the cathode area. This can be characterized by a propagation velocity called the spreading velocity [5]. Experimental measurements [6] have shown a typical spreading velocity of 5000 cm/s. This velocity also depends on the GTO design parameters, the gate turn-on injection current, and its dIG/dt.

Because of this spreading velocity, it takes time for the whole GTO cell to turn on. To avoid overstressing the part of the cell that is turned on first, the increasing rate of the anode current should be limited. This sets the maximum turn-on dI/dt limitation for a GTO.

The major advantages of the GTO are its low forward voltage drop and high-voltage blocking capability. These can be understood as the major benefits of its double-side minority carrier injection mechanism. For high-voltage GTO, a thick and lightly doped n-base is needed (see Fig. 1.75). The forward voltage drop in this case is mainly determined by the resistive voltage drop in the voltage-blocking region where minority carriers play an important role.

FIGURE 1.78 On-state minority carrier distribution in the

voltage blocking region for (a) GTO and (b) IGBTi.

Figure 1.78a shows the minority carrier distribution in the n− region of a GTO and Fig. 1.78b shows the case of an IGBT (see Section 1.9). For the same blocking voltage design, their n− regions should have similar thickness and doping. Since there is only one transistor in the IGBT structure, minority carriers can only be injected from one side; therefore, the conductivity modulation in the n− region is weaker than that of the GTO. In the GTO, since there are two transistors, minority carriers can be injected from both ends, making a more uniform plasma distribution in the whole area. For a 4.5-kV state-of-the-art GTO, its forward voltage drop at a current density of 50 A/cm2 can be as low as 2.0 V [7] if a constant gate current injection presents. Figure 1.79 shows the on-state characteristics of a state-of-the-art GTO manufactured by ABB . The forward voltage drop at 2000 A is only about 1.5 V for this 4.5-kV GTO. This result is typical of a low conduction loss GTO.

Ⅲ Non-Uniform Turn-Off Process among GTO Cells

For a high-power GTO, the experimentally

obtained instant turn-off power it can withstand is far below the value set by the dynamic avalanche breakdown shown in Eq. (1.21). So a GTO needs help from a dV/dt snubber to shape its turn-off I–V trajectory, as is shown in Fig. 1.72, and to lower the maximum average instant power the external circuit can apply. Non-uniform current distribution or current filament among GTO cells during the turn-off operation accounts for this limitation. The current filament can be formed at the beginning of the turn-off due to differences in storage times or caused by the onset of the

dynamic avalanche during the turn-off when the voltage and current are both high.

REFERENCES

1. S.K. Gandhi, Semiconductor Power Devices, Wiley, New York, 1977. 2. E.D. Wolley, Gate Turn-Off in P-N-P-N devices, IEEE Trans. Electron Devices, ED-13, 590–597, 1966.

3. Mitsubishi GTO FG6000AU-120D data sheet.

4. B.J. Baliga, Power Semiconductor Devices, PWS Publishing Company, Boston, 1996.

5. W.H. Dodson and R.L. Longini, Probed determination of turn-on spread of large area thyristors,

IEEE Trans. Electron Devices, ED-13, 478–484, 1966.

6. H.J. Ruhl, Spreading velocity of the active area boundary in a thyristor, IEEE Trans. Electron Devices, ED-17, 672–680, 1970.