Methods and structures for metal interconnections

专利名称：Methods and structures for metal

interconnections in integrated circuits

发明人：Kie Y. Ahn,Leonard Forbes,Paul A. Farrar申请号：US10338178申请日：20030107

公开号：US20030209775A1公开日：20031113

专利附图：

摘要：A typical integrated-circuit fabrication requires interconnecting millions ofmicroscopic transistors and resistors with metal wires. Making the metal wires flush, orcoplanar, with underlying insulation requires digging trenches in the insulation, and thenfilling the trenches with metal to form the wires. The invention provides a new “trench-less” or “self-planarizing” method of making coplanar metal wires. Specifically, oneembodiment forms a first layer that includes silicon and germanium; oxidizes a region ofthe first layer to define an oxidized region and a non-oxidized region; and reacts

aluminum or an aluminum alloy with the non-oxidized region. The reaction substitutes, orreplaces, the non-oxidized region with aluminum to form a metallic wire coplanar with thefirst layer. Another step removes germanium oxide from the oxidized region to form aporous insulation having a very low dielectric constant, thereby reducing capacitance.

申请人：MICRON TECHNOLOGY, INC.

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