W320-03H资料

W320-03

200 MHz Spread Spectrum Clock Synthesizer/Driver

with Differential CPU Outputs

Features

•Compliant with Intel® CK-Titan Clock Synthe-sizer/Driver Specifications

•Multiple output clocks at different frequencies•Three pairs of differential CPU outputs, up to 200MHz•Ten synchronous PCI clocks, three free-running•Six 3V66 clocks•Two 48 MHz clocks

•One reference clock at 14.318 MHz•One VCH clock

•Spread Spectrum clocking (down spread)•Power-down features (PCI_STOP#, CPU_STOP# PWR_DWN#)

•Three Select inputs (Mode select & IC Frequency Select)

•OE and Test Mode support

•56-pin SSOP package and 56-pin TSSOP packageBenefits

•Supports next-generation Pentium® processors using differential clock drivers•Motherboard clock generator•Support Multiple CPUs and a chipset•Support for PCI slots and chipset

•Supports AGP, DRCG reference and Hub Link •Supports USB host controller and graphic controller•Supports ISA slots and I/O chip

•Enables reduction of electromagnetic interference (EMI) and overall system cost•Enables ACPI-compliant designs

•Supports up to four CPU clock frequencies•Enables ATE and “bed of nails” testing

•Widely available, standard package enables lower cost

Logic Block DiagramX1X2Pin ConfigurationsSSOP & TSSOPTop ViewVDD_REFPWRXTALOSCREFVDD_REFXTAL_INXTAL_OUTGND_REFPCI_F0PCI_F1PCI_F2VDD_PCIGND_PCIPCI0PCI1PCI2PCI3VDD_PCIGND_PCIPCI4PCI5PCI6VDD_3V66GND_3V6666BUFF0/3V66_266BUFF1/3V66_366BUFF2/3V66_466IN/3V66_5PWR_DWN#VDD_COREGND_COREPWR_GD#12345678910115655545352515049484746REFS1S0CPU_STOP#CPU0CPU#0VDD_CPUCPU1CPU#1GND_CPUVDD_CPUCPU2CPU#2MULT0IREFGND_IREFS2USB DOTVDD_ 48 MHzGND_ 48 MHz3V66_1/VCHPCI_STOP#3V66_0VDD_3V66GND_3V66SCLKSDATA PLL Ref FreqPLL 1S0:2PWR_GD#CPU_STOP#GateDividerNetworkPWRStopClockControlVDD_CPUCPU0:2CPU#0:2PWRStopClockControlVDD_PCIPCI_F0:2PCI0:6W320-0312131415161718192021222324252627284544434241403938373635343332313029PCI_STOP#/2PWR_DWN#VDD_3V663V66_0PWRPWR3V66_2:4/ 66BUFF0:2 3V66_5/ 66INPLL 2VDD_48MHzPWRUSB (48MHz)DOT (48MHz)VCH_CLK/ 3V66_1SDATASCLKSMBusLogicRev1.0,November 25, 2006

2200 Laurelwood Road, Santa Clara, CA 95054

Tel:(408) 855-0555

Fax:(408) 855-0550

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W320-03Pin Summary

NameREFXTAL_INXTAL_OUTCPU, CPU# [0:2]3V66_03V66_1/VCH66IN/3V66_566BUFF [2:0] /3V66 [4:2]PCI_F [0:2] PCI [0:6]USBDOTS2S1, S0IREFMULT0PWR_DWN#PCI_STOP#CPU_STOP#PWRGD#Pins5623Description3.3V 14.318 MHz clock output14.318 MHz crystal input14.318 MHz crystal input44, 45, 48, 49, 51, Differential CPU clock outputs5233352421, 22, 235, 6, 7,3.3V 66 MHz clock output3.3V selectable through SMBus to be 66 MHz or 48 MHz66 MHz input to buffered 66BUFF and PCI or 66 MHz clock from internal VCO66 MHz buffered outputs from 66Input or 66 MHz clocks from internal VCO33 MHz clocks divided down from 66Input or divided down from 3V6610, 11, 12, 13, 16, PCI clock outputs divided down from 66Input or divided down from 3V6617, 1839384054, 55424325345328Fixed 48 MHz clock outputFixed 48 MHz clock outputSpecial 3.3V 3 level input for Mode selection3.3V LVTTL inputs for CPU frequency selectionA precision resistor is attached to this pin which is connected to the internal current reference3.3V LVTTL input for selecting the current multiplier for the CPU outputs3.3V LVTTL input for Power_Down# (active LOW)3.3V LVTTL input for PCI_STOP# (active LOW)3.3V LVTTL input for CPU_STOP# (active LOW)3.3V LVTTL input is a level sensitive strobe used to determine when S[2:0] and MULTI0 inputs are valid and OK to be sampled (Active LOW). Once PWRGD# is sampled LOW, the status of this output will be ignored.SMBus compatible SDATASMBus compatible SclkSDATASCLK2930VDD_REF, VDD_PCI, 1, 8, 14, 19, 32, 46, 3.3V power supply for outputsVDD_3V66, 50VDD_CPUVDD_48 MHzVDD_CORE 37263.3V power supply for 48 MHz3.3V power supply for PLLGND_REF, GND_PCI, 4, 9, 15, 20, 31, 36, Ground for outputsGND_3V66, 41, 47GND_IREF, VDD_CPUGND_CORE27Ground for PLLRev 1.0,November 25, 2006Page 2 of 16

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W320-03Function Table [1]

S211110000MidMidMidMidS1001100110011010101010101S0CPU(MHz)66 MHz100 MHz200 MHz133 MHz66 MHz100 MHz200 MHz133 MHzHi-ZTCLK/2ReservedReserved3V66[0:1]66BUFF[0:2]/366IN/3V66_5 (MHz)V66[2:4] (MHz)(MHz)66 MHz66 MHz66 MHz66 MHz66 MHz66 MHz66 MHz66 MHzHi-ZTCLK/4ReservedReserved66 IN66 IN66 IN66 IN66 MHz66 MHz66 MHz66 MHzHi-ZTCLK/4ReservedReserved66 MHz Input66 MHz Input66 MHz Input66 MHz Input66 MHz 66 MHz66 MHz 66 MHz Hi-ZTCLK/4ReservedReservedPCI_F/PCI(MHz)66 IN/266 IN/266 IN/266 IN/233 MHz33 MHz33 MHz33 MHzHi-ZTCLK/8ReservedReservedREF0(MHz)USB/DOT (MHz)Notes2, 3, 42, 3, 42, 3, 42, 3, 42, 3, 42, 3, 42, 3, 42, 3, 41, 56, 7, 8––14.318 MHz48 MHz14.318 MHz48 MHz14.318 MHz48 MHz14.318 MHz48 MHz14.318 MHz48 MHz14.318 MHz48 MHz14.318 MHz48 MHz14.318 MHz48 MHzHi-ZTCLKReservedReservedHi-ZTCLK/2ReservedReservedSwing Select Functions

Mult001

Board TargetTrace/Term Z

60:50:

Reference R, IREF =

VDD/(3*Rr)Rr = 221 1%,IREF = 5.00 mARr = 475 1%,IREF = 2.32 mA

Output CurrentIOH = 4*IREFIOH = 6*IREF

VOH @ Z1.0V @ 500.7V @ 50

Clock Driver Impedances

Impedance

Buffer NameCPU, CPU#REF

PCI, 3V66, 66BUFFUSBDOT

3.135–3.4653.135–3.4653.135–3.4653.135–3.465VDD Range

Buffer TypeType X1Type 3Type 5Type 3AType 3B

20121212Minimum

:

Typical:5040303030

60555555Maximum

:

Clock Enable Configuration

PWR_DWN#CPU_STOP#PCI_STOP#

01111

X0011

X0101

CPUIREF*2IREF*2IREF*2ONON

CPU#FLOATFLOATFLOATONON

3V66LOWONONONON

66BUFFLOWONONONON

PCI_FLOWONONONON

PCILOWOFFONOFFON

USB/DOTLOWONONONON

VCOS/OSCOFFONONONON

Notes:

1.TCLK is a test clock driven in on the XTALIN input in test mode.2.“Normal” mode of operation.

3.Range of reference frequency allowed is min. = 14.316 nominal = 14.31818 MHz, max = 14.32 MHz.4.Frequency accuracy of 48 MHz must be +167PPM to match USB default.

5.Mid is defined a Voltage level between 1.0V and 1.8V for 3 level input functionality. Low is below 0.8V. High is above 2.0V.6.TCLK is a test clock over driven on the XTAL_IN input during test mode.7.Required for DC output impedance verification.

8.These modes are to use the SAME internal dividers as the CPU = 200-MHz mode. The only change is to slow down the internal VCO to allow under clock margining.

Rev 1.0,November 25, 2006Page 3 of 16

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W320-03Serial Data Interface (SMBus)

To enhance the flexibility and function of the clock synthesizer,a two signal SMBus interface is provided according to theSMBus specification. Through the Serial Data Interface (SDI),various device functions such as individual clock outputbuffers, etc can be individually enabled or disabled. W320-03support both block read and block write operations.

The registers associated with the SDI initialize to their defaultsetting upon power-up, and therefore use of this interface isoptional. Clock device register changes are normally madeupon system initialization, if any are required. The interfacecan also be used during system operation for powermanagement functions. Data Protocol

The clock driver serial protocol accepts only block writes fromthe controller. The bytes must be accessed in sequential orderfrom lowest to highest byte, (most significant bit first) with the

ability to stop after any complete byte has been transferred.Indexed bytes are not allowed.

A block write begins with a slave address and a WRITEcondition. The R/W bit is used by the SMBus controller as adata direction bit. A zero indicates a WRITE condition to theclock device. The slave receiver address is 11010010 (D2h). A command code of 0000 0000 (00h) and the byte count bytesare required for any transfer. After the command code, thecore logic issues a byte count which describes number ofadditional bytes required for the transfer, not including thecommand code and byte count bytes. For example, if the hosthas 20 data bytes to send, the first byte would be the number20 (14h), followed by the 20 bytes of data. The byte count byteis required to be a minimum of one byte and a maximum of 32bytes It may not be 0. Figure1 shows an example of a blockwrite.

A transfer is considered valid after the acknowledge bit corre-sponding to the byte count is read by the controller.

Start Slave AddressR/Wbit1 1 0 1 0 0 1 00/11 bit7 bits1ACommand Code0 0 0 0 0 0 0 08 bitsAByte Count = AData Byte 0AN18 bits18 bits1. . . Data Byte N-1AStop bit8 bits11 bit1From Master to SlaveFrom Slave to Master

Figure 1. An Example of a Block Write

Data Byte Configuration Map

Data Byte 0: Control Register (0 = Enable, 1 = Disable)BitBit 7

Affected Pin#

Name

Description

Spread Spectrum Enable0 = Spread Off, 1 = Spread OnTBD

VCH Select 66 MHz/48 MHz0 = 66 MHz, 1 = 48 MHz

CPU_STOP#

Reflects the current value of the external CPU_STOP# pinPCI_STOP#

(Does not affect PCI_F [2:0] pins)

S2

Reflects the value of the S2 pin sampled on Power-upS1

Reflects the value of the S1 pin sampled on Power-upS0

Reflects the value of the S1 pin sampled on Power-up

TypeR/W

Power On Default0

5, 6, 7, 10, 11, PCI [0:6]12, 13, 16, 17, CPU[2:0]18, 33, 353V66[1:0]–35

TBD3V66_1/VCH

Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0

RR/WRR/WRRR

00N/AN/AN/AN/AN/A

44, 45, 48, 49, CPU [2:0]51, 52CPU# [2:0]10, 11, 12, 13, PCI [6:0] 16, 17, 18–––

–––

Rev 1.0,November 25, 2006Page 4 of 16

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W320-03Data Byte 1

BitBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Data Byte 2

BitBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Data Byte 3

BitBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0

Pin#3839765765

DOTUSBPCI_F2PCI_F1PCI_F0PCI_F2PCI_F1PCI_F0

Name

Pin Description

DOT 48-MHz Output EnableUSB 48-MHz Output Enable

Allow control of PCI_F2 with assertion of PCI_STOP#0 = Free running; 1 = Stopped with PCI_STOP#Allow control of PCI_F1 with assertion of PCI_STOP#0 = Free running; 1 = Stopped with PCI_STOP#Allow control of PCI_F0 with assertion of PCI_STOP#0 = Free running; 1 = Stopped with PCI_STOP#PCI_F2 Output EnablePCI_F1Output EnablePCI_F0 Output Enable

TypeR/WR/WR/WR/WR/WR/WR/WR/W

Power On Default11000111

Pin#–18171613121110

N/APCI6PCI5PCI4PCI3PCI2PCI1PCI0

Name

N/A

PCI6 Output Enable

1 = Enabled; 0 = DisabledPCI5 Output Enable

1 = Enabled; 0 = DisabledPCI4 Output Enable

1 = Enabled; 0 = DisabledPCI3 Output Enable

1 = Enabled; 0 = DisabledPCI2 Output Enable

1 = Enabled; 0 = DisabledPCI1 Output Enable

1 = Enabled; 0 = DisabledPCI0 Output Enable

1 = Enabled; 0 = Disabled

Pin Description

TypeRR/WR/WR/WR/WR/WR/WR/W

Power On Default01111111

Pin#––44, 4548, 4951, 5244, 4548, 4951, 52

N/AN/ACPU2CPU2#CPU1CPU1#CPU0CPU0#CPU2CPU2#CPU1CPU1#CPU0CPU0#

Name

CPU Mult0 ValueTBD

Allow Control of CPU2 with assertion of CPU_STOP#0 = Not free running; 1 = Free running

Allow Control of CPU1 with assertion of CPU_STOP#0 = Not free running;1 = Free running

Allow Control of CPU0 with assertion of CPU_STOP#0= Not free running; 1 = Free runningCPU2 Output Enable

1 = Enabled; 0 = DisabledCPU1Output Enable

1 = Enabled; 0= DisabledCPU0 Output Enable

1 = Enabled; 0 = Disabled

Description

TypeRRR/WR/WR/WR/WR/WR/W

Power On DefaultN/A0000111

Rev 1.0,November 25, 2006Page 5 of 16

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W320-03Data Byte 4

BitBit 7Bit 6Bit 5Bit 4Bit 3

Pin#----333524

TBDTBD3V66_03V66_1/VCH66IN/3V66_5

Name

N/AN/A

3V66_0 Output Enable1 = Enabled; 0 = Disabled3V66_1/VCH Output Enable1 = Enabled; 0 = Disabled

Pin Description

TypeRRR/WR/W

Power On Default00111

R/W3V66_5 Output Enable

1 = Enable; 0 = Disable

NOTE: THIS BIT SHOULD BE USED WHEN PIN 24 IS CONFIGURED AS 3V66_5 OUTPUT. DO NOT CLEAR THIS BIT WHEN PIN 24 IS CONFIGURED AS 66IN INPUT.66-MHz Buffered 2 Output Enable1 = Enabled; 0 = Disabled66-MHz Buffered 1 Output Enable1 = Enabled; 0 = Disabled66-MHz Buffered 0 Output Enable1 = Enabled; 0 = Disabled

R/WR/WR/W

Bit 2Bit 1Bit 0Data Byte 5

BitBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0

232221

66BUFF266BUFF166BUFF0

111

Pin#

N/AN/A

Name

N/AN/A

Pin DescriptionTypeRRR/WR/WR/WR/WR/WR/W

Power On Default00000000

66BUFF [2:0]66BUFF [2:0]DOTDOTUSBUSB

Tpd 66IN to 66BUFF propagation delay controlDOT edge rate controlUSB edge rate control

Byte 6: Vendor ID

Bit

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0

Revision Code Bit 3Revision Code Bit 2Revision Code Bit 1Revision Code Bit 0Vendor ID Bit 3Vendor ID Bit 2Vendor ID Bit 1Vendor ID Bit 0

Description

RRRRRRRR

Type

00010100

Power On Default

Rev 1.0,November 25, 2006Page 6 of 16

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W320-03Maximum Ratings

(Above which the useful life may be impaired. For user guide-lines, not tested.)

Supply Voltage..................................................–0.5 to +7.0VInput Voltage..............................................–0.5V to VDD+0.5

Storage Temperature

(Non-condensing)........................................–65qC to +150qCMax. Soldering Temperature (10 sec)....................... +260qCJunction Temperature................................................ +150qCPackage Power Dissipation...............................................1:Static Discharge Voltage

(per MIL-STD-883, Method 3015)........................... > 2000V

Operating Conditions Over which Electrical Parameters are Guaranteed[9]

Parameter

VDD_REF, VDD_PCI,VDD_CORE,VDD_3V66, VDD_CPU, VDD_48 MHz TACinCXTALCL

Description

3.3V Supply Voltages48-MHz Supply Voltage

Operating Temperature, AmbientInput Pin CapacitanceXTAL Pin CapacitanceMax. Capacitive Load onUSBCLK, REFPCICLK, 3V66

Reference Frequency, Oscillator Nominal Value

14.318Min.3.1352.850

Max.3.4653.46570522.5203014.318

MHzUnitVVqCpFpFpF

f(REF)

Electrical Characteristics Over the Operating Range

ParameterVIHVILVOHVOLIIHIILIOH

Description

High-level Input VoltageLow-level Input VoltageHigh-level Output VoltageLow-level Output VoltageInput High CurrentInput Low CurrentHigh-level Output Current

Except Crystal PadsUSB, REF, 3V66PCI

USB, REF, 3V66PCI

0 < VIN < VDD0 < VIN < VDD

CPU

For IOH =6*IRef ConfigurationREF, DOT, USB3V66, DOT, PCI

IOL

Low-level Output Current

REF, DOT, USB3V66, PCI

IOZIDD3IDDPD3

Output Leakage Current

Three-state

Type X1, VOH = 0.65VType X1, VOH = 0.74VType 3, VOH = 1.00VType 3, VOH = 3.135VType 5, VOH = 1.00VType 5, VOH = 3.135VType 3, VOL = 1.95VType 3, VOL = 0.4VType 5, VOL =1.95 VType 5, VOL = 0.4V

3.3V Power Supply CurrentVDD_CORE/VDD3.3 = 3.465V, FCPU = 133 MHz3.3V Shutdown CurrentVDD_CORE/VDD3.3 = 3.465V

30

381036020

mAmAmA

29

27

–33

–33

mA

–29

–23

IOH = –1 mAIOH = –1 mAIOL = 1 mAIOL = 1 mA

–5–512.9

14.92.42.4

0.40.5555

Test Conditions

Except Crystal Pads. Threshold voltage for crystal pads = VDD/2

Min.Max.Unit2.0

0.8

VVVVVVmAmAmA

Note:

9.Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.

Rev 1.0,November 25, 2006Page 7 of 16

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W320-03Switching Characteristics[10] Over the Operating Range

Parametert1t3t3t5t5t6t7t9t9t9t9t2t3t4t8VohVolVcrossovert2t3t4t8AllPCI,3V663V66[0:1]66BUFF[0:2]PCI3V66,PCI3V66USB, DOTPCIREFCPUCPUCPUCPUCPUCPUCPUCPUCPUCPUCPUCPUCPUVohVolVcrossoverCPUCPUCPUOutputDescriptionOutput Duty Cycle[11]Falling Edge Rate3V66-3V66 Skew66BUFF-66BUFF SkewPCI-PCI Skew3V66-PCI Clock JitterCycle-Cycle Clock JitterCycle-Cycle Clock JitterCycle-Cycle Clock JitterCycle-Cycle Clock JitterRiseTimeFall TimeCPU-CPU SkewCycle-Cycle Clock JitterRise/Fall MatchingHigh-level Output Voltageincluding overshootLow-level Output Voltage including undershootCrossover VoltageRiseTimeFall TimeCPU-CPU SkewCycle-Cycle Clock JitterRise/Fall MatchingHigh-level Output Voltage including overshootLow-level Output Voltage including undershootCrossover VoltageTest ConditionsMeasured at 1.5VBetween 2.4V and 0.4VBetween 2.4V and 0.4VMeasured at 1.5VMeasured at 1.5VMeasured at 1.5V3V66 leads. Measured at 1.5VMeasured at 1.5V t9= t9A – t9BMeasured at 1.5V t9= t9A – t9BMeasured at 1.5V t9= t9A – t9BMeasured at 1.5V t9= t9A – t9BMeasured differential waveform from –0.35V to +0.35VMeasured differential waveform from –0.35V to +0.35VMeasured at CrossoverMeasured at Crossover t8 = t8A – t8BMeasured with test loads[12]Measured with test loads[12]Measured with test loads[12]Measured with test loads[12]Measured single ended waveform from 0.175V to 0.525VMeasured single ended waveform from 0.175V to 0.525VMeasured at CrossoverMeasured at Crossover t8= t8A – t8BWith all outputs running Measured with test loads[13, 14]Measured with test loads[14]Measured with test loads[14]Measured with test loads[14]–0.150.280.430.92–0.20.511751751751751.5Min.450.51.0Max.552.04.05001755003.525035050010004674671501503251.450.350.76700700150150200.85Unit%psV/nspspspsnspspspspspspspspsmVVVVpspspsps%VVVUSB, REF, DOTFalling Edge RateCPU 1.0V Switching CharacteristicsCPU 0.7V Switching CharacteristicsNotes: 10.All parameters specified with loaded outputs.11.Duty cycle is measured at 1.5V when VDD = 3.3V. When VDD = 2.5V, duty cycle is measured at 1.25V.12.The 1.0V test load is shown on test circuit page.13.Determined as a fraction of 2*(Trp – Trn)/(Trp +Trn) Where Trp is a rising edge and Trp is an intersecting falling edge.14.The 0.7V test load is Rs = 33.2:, Rp = 49.9: in test circuit.Rev 1.0,November 25, 2006Page 8 of 16

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W320-03Definition and Application of PWRGD# Signal

Vtt

VRM8.5PWRGD#CPUBSEL0BSEL13.3V3.3VNPN3.3VPWRGD#CLOCKGENERATORS010K10KGMCHS110K10KRev 1.0,November 25, 2006Page 9 of 16

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W320-03Switching Waveforms

Duty Cycle Timing(Single Ended Output)t1Bt1ADuty Cycle Timing (CPU Differential Output)t1Bt1AAll Outputs Rise/Fall TimeVDDt2t30VOUTPUTCPU-CPU Clock SkewHost_bHostHost_bHostt43V66-3V66 Clock Skew3V663V66t5PCI-PCI Clock SkewPCIPCIt6Rev 1.0,November 25, 2006Page 10 of 16

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W320-03Switching Waveforms (continued)

3V66-PCI Clock Skew3V66PCIt7CPU Clock Cycle-Cycle Jittert8AHost_bHostt8BCycle-Cycle Clock Jittert9At9BCLKPWRDWN# Assertion[15]

66BUFFPCI

PCI_F (APIC)PWR_DWN#CPUCPU#3V6666INUSBREF

UNDEFPower Down Rest of GeneratorNote:

15.PCI_STOP# asserted LOW.

Rev 1.0,November 25, 2006Page 11 of 16

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W320-03PWRDWN# Deassertion[15]

10-30 Ps min.100-200 Ps max.<3ms66BUFF1/GMCH66BUFF0,2PCI

PCI_F (APIC)PWR_DWN#CPUCPU#3V6666INUSBREF

PWRGD# Timing Diagrams

GND VRM 5/12V

PWRGD#VID [3:0]BSEL [1:0]PWRGD# FROM

VRMPWRGD# FROMNPN

VCC CPU COREPWRGD#

VCC W320 CLOCK GEN

CLOCK STATE

State 0OFFCLOCK VCO

OFFCLOCK OUTPUTSON0.2 – 0.3 msWait fordelayPWRGD#SampleBSELSPossible glitch while Clock VCC is comingup. Will be gone in 0.2–0.3 ms delay.State 1State 2State 3ONFigure 2. CPU Power BEFORE Clock PowerRev 1.0,November 25, 2006Page 12 of 16

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W320-03GND VRM 5/12V

PWRGD#VID [3:0]BSEL [1:0]PWRGD# FROM

VRMPWRGD# FROM

VCC CPU COREPWRGD#

VCC W320 CLOCK GEN

CLOCK STATE

State 0OFFCLOCK VCO

OFFCLOCK OUTPUTSONON0.2 – 0.3 msdelayWait forPWRGD#SampleBSELSState 1State 2State 3Figure 3. CPU Power AFTER Clock Power

Rev 1.0,November 25, 2006Page 13 of 16

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W320-03Layout Example

+3.3V SupplyFBVDDQ310 PF

0.005󰀃PFC1GGGG12345678911121314151617181920212223242526272810VGGGVGGGVGGVGGGVGG5655545352G51V50G4948G47V46G45444342G4140393837G363534G33V32G3130G29GGGFB = Dale ILB1206 - 300 or 2TDKACB2012L-120 or 2 Murata BLM21B601SCeramic CapsC1 = 10–22 µF

C2 = 0.005 PFC5 = 0.1 PF C6 = 10 PF

G= VIA to GND plane layer V=VIA to respective supply plane layerNote: Each supply plane or strip should have a ferrite bead and capacitors

W320-03VDDQ3󰀛:C5GGC6GRev 1.0,November 25, 2006Page 14 of 16

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W320-03Test Circuit[16, 17]

VDD_REF, VDD_PCI, VDD_3V66, VDD_COREVDD_48 MHz, VDD_CPU0.7V Test Load9, 15, 20, 27, 31, 36, 41, 471, 8, 14, 26, 32, 37, 46, 50W320-03RpRsCPUTest Node20 pFRef,USB Outputs2 pFOUTPUTSPCI,3V66 OutputsRsTestNodes2 pFTest Node30 pFRpVDD_REF, VDD_PCI, VDD_3V66, VDD_COREVDD_48 MHz, VDD_CPU9, 15, 20, 27, 31, 36, 41, 471, 8, 14, 26, 32, 37, 46, 501.0V Test Load332 pFTest Node20 pFRef,USB OutputsW320-03CPU475OUTPUTSPCI,3V66 Outputs63.433TestNodes2 pFTest Node

30 pF63.41.0V AmplitudeOrdering Information

Ordering CodeW320-03HW320-03HTW320-03XW320-03XTLead-freeCYW320OXC-3CYW320OXC-3T56-pin SSOP56-pin SSOP - Tape and ReelCommercialCommercial56-pin SSOP56-pin SSOP - Tape and Reel56-pin TSSOP56-pin TSSOP - Tape and ReelPackage TypeOperating RangeCommercialCommercialCommercialCommercialNotes: 16.Each supply pin must have an individual decoupling capacitor.17.All capacitors must be placed as close to the pins as is physically possible. 0.7V amplitude: RS = 33: RP = 50:.Rev 1.0,November 25, 2006Page 15 of 16

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W320-03Package Diagrams

56-leadShrunkSmallOutlinePackageO56

56-Lead Thin Shrunk Small Outline Package, Type II (6 mm x 12 mm) Z560.249[0.009]281DIMENSIONSINMM[INCHES]MIN.MAX.7.950[0.313]8.255[0.325]5.994[0.236]6.198[0.244]REFERENCEJEDECMO-153PACKAGEWEIGHT0.42gmsPART#Z5624STANDARDPKG.ZZ5624LEADFREEPKG.295613.894[0.547]14.097[0.555]1.100[0.043]MAX.GAUGEPLANE0.25[0.010]0.20[0.008]0.851[0.033]0.950[0.037]0.500[0.020]BSC0.051[0.002]0.152[0.006]SEATINGPLANE0°-8°0.508[0.020]0.762[0.030]0.170[0.006]0.279[0.011]0.100[0.003]0.200[0.008]While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any cir-cuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use innormal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other applica-tion requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additionalprocessing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change anycircuitry or specification without notice.

Rev1.0,November 25, 2006Page 16 of 16