SC3015B;中文规格书,Datasheet资料

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Quartz SAW Frequency Stability Fundamental Fixed Frequency

Very Low Jitter and Power ConsumptionRugged, Miniature, Surface-Mount CaseLow-Voltage Power Supply (3.3 VDC)

This digital clock is designed for use with high-speed CPUs and digitizers. Fundamental-mode oscillation is made possible by surface-acoustic-wave (SAW) technology. The design results in low jitter, compact size, and low power consumption. Differential outputs provide a sine wave that is capable of driving 50Ω loads.

550.0 MHzDifferential Sine-Wave Clock

Absolute Maximum RatingsRatingPower Supply Voltage (VCC at Terminal 1)Input Voltage (ENABLE at Terminal 8)Case Temperature (Powered or Storage)Value0 to +4.00 to +4.0-40 to +85UnitsVDCVDC°CElectrical Characteristics CharacteristicOutput FrequencyQ and Q OutputAbsolute FrequencyTolerance from 400.000 MHzOperating Load VSWRSymmetryHarmonic SpuriousNonharmonic SpuriousQ and Q Period JitterOutput (Disabled)No Noise on VCC200 mVP-P from 1 MHz to ½ fO on Amplitude into 50 ΩOutput DC Resistance (between Q & Q)ENABLE (Terminal 14)Input HIGH VoltageInput LOW VoltageInput HIGH CurrentInput LOW CurrentPropagation DelayDC Power SupplyOperating VoltageOperating CurrentOperating Ambient TemperatureLid Symbolization (YY = Year, WW = Week) SMC-8B Case SymfOΔfONotes1, 21, 33, 4, 53, 4, 63, 4, 6, 73, 4, 7, 83, 93Minimum9.0.6049Typical550.0Maximum 550.11±2001.12:151-30-60UnitsMHzppmVP-P%dBcdBcpsP-PpsP-PmVP-PKΩVVmAmAmsVDCmA°CVoltage into 50Ω (VSWR ≤ 1.2) VO1530357550VCC-0.10.0VCC3VCC+0.10.205-11+3.130+3.3020RFM SC3015B 550.00 MHz YYWW+3.4740+70VIHVILIIHIILtPDVCCICCTA1, 31, 33, 9CAUTION: Electrostatic Sensitive Device. Observe precautions for handling.

NOTES:

1.2.3.4.5.

Unless otherwise noted, all specifications include any combination of loadVSWR, VCC, and TA. In addition, Q and Q are terminated into 50Ω loads toground. (See: Typical Test Circuit.)

One or more of the following United States patents apply: 4,616,197; 4,670,681;4,760,352.

The design, manufacturing process, and specifications of this device are subjectto change without notice.

Only under the nominal conditions of 50Ω load impedance with VSWR ≤ 1.2 andnominal power supply voltage.

Symmetry is defined as the pulse width (in percent of total period) measured atthe 50% points of Q or Q. (See: Timing Definitions.)6.

Jitter and other spurious outputs induced by externally generated electrical noiseon VCC or mechanical vibration are not included. Dedicated external voltageregulation and careful PCB layout are recommended for optimum performance.Applies to period jitter of Q and Q. Measurements are made with the TektronixCSA803 signal analyzer with at least 1000 samples.

Period jitter measured with a 200mVP-P sine wave swept from 1MHz to one-halfof fO at the VCC power supply terminal.

The outputs are enabled when Terminal 8 is at logic HIGH. Propagation delay isdefined as the time from the 50% point on the rising edge of ENABLE to the 90%point on the rising edge of the output amplitude or as the fall time from the 50%point to the 10% point. (SEE: Timing Definitions.)

7.8.9.

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Electrical Connections

Footprint

Actual size footprint:

18 765TerminalNumber

12345678LID

Connection

VCCGroundNC or GroundQ OutputQ OutputGroundENABLEGround

234TOP VIEWTypical Printed Circuit Board Land Pattern

A typical land pattern for a circuit board is shown below. Grounding of the metallic center pad is optional.

Case Design

All pads consist of 30 microinches (min) electroless gold on 50 microinches (min) electroless nickel over base metal. The metallic center pad was designed for mechanical support. Grounding of this pad is optional.Lid symbolization, including terminal 1 locator dot, are in contrasting ink. Symbolization varies by model number. For purposes of illustration, only terminal 1 dot is shown.

Typically 0.01\" to 0.05\" or 0.25 mm to1.25 mm (8 Places)(The optimum value of this dimension isdependent on the PCB assembly processemployed.).

Typical Test Circuit

Vcc4.7 μH0.1 μFSine-WaveSignal GeneratorBCDEN(X8)AFMGL(X3)(X8)Vcc50 ΩQ50 ΩQ*TektronixCSA 803DigitizingOscilloscopeCh 1TriggerCh 2ClockUnder TestH(X2)ENABLE*KJ50 Ω*Power Splitter, Mini-Circuits ZFSC2-4Timing Definitions

Dimensions

ABCDEFGHJKLMN

MillimetersMinMax

13.469.14

13.979.66

InchesMin

0.5300.360

Propagation Delay:Max

0.5500.380

50%ENABLE50%2.05 Nominal3.56 Nominal2.24 Nominal1.27 Nominal2. Nominal3.05 Nominal1.93 Nominal5. Nominal4.32 Nominal4.83 Nominal0.50 Nominal

0.081 Nominal0.141 Nominal0.088 Nominal0.050 Nominal0.100 Nominal0.120 Nominal0.076 Nominal0.218 Nominal0.170 Nominal0.190 Nominal0.020 Nominal

Symmetry as% of PeriodPeriodSymmetry as% of Period50%50%Symmetry:Q or Q Output50%Q or Q OutputAmplitudeEnvelope90%10%tPDtPDwww.RFM.comE-mail: info@rfm.com©2008 by RF Monolithics, Inc.Page 2 of 2

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