SC3041B;中文规格书,Datasheet资料

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Quartz SAW Frequency Stability Fundamental Fixed FrequencyExcellent Jitter and Symmetry

Rugged, Miniature, Surface-Mount CaseLow-Voltage Power Supply (3.3 VDC)

Directive 2002/95/EC (ROHS) Compliant by June, 2006

This digital clock is designed for use in abrizio’s chipset for Terabit Router applications. Fundamental-mode oscillation is made possible by surface-acoustic-wave (SAW) technology. The design results in low jitter, compact size, and low power consumption. Differential outputs provide a sine wave that is made to drive 50Ω loads.

300.0 MHzDifferential Sine-Wave Clock

Absolute Maximum RatingsRatingPower Supply Voltage (VCC at Terminal 1)Input Voltage (ENABLE at Terminal 8)Case Temperature (Powered or Storage)

Value0 to +4.00 to +4.0-40 to +85

UnitsVDCVDC°C

SMC-8 Case Electrical Characteristics

CharacteristicOutput FrequencyQ and Q Output

Absolute FrequencyTolerance from 286.0 MHzOperating Load VSWRSymmetry

Harmonic SpuriousNonharmonic Spurious

Q and Q Period JitterOutput (Disabled)No Noise on VCC

200 mVP-P from 1 MHz to ½ fO on Amplitude into 50 ΩVIHVILIIHIILtPDVCCICCTA

1, 31, 3+3.130+3.3018

RFM SC3041B 300.00 MHz YYWW

3, 9

Output DC Resistance (between Q & Q)ENABLE (Terminal 14)Input HIGH VoltageInput LOW VoltageInput HIGH CurrentInput LOW CurrentPropagation Delay

DC Power SupplyOperating VoltageOperating Current

Operating Ambient TemperatureLid Symbolization (YY = Year, WW = Week)

Sym

fOΔfO

Notes1, 21, 33, 4, 53, 4, 63, 4, 6, 73, 4, 7, 83, 93

100VCC-0.10.0

3VCC

VCC+0.10.205-11+3.4740+70Minimum299.9400.9

-2515Typical

Maximum300.060±2004.52:151-20-60303575UnitsMHzppmdBm%dBcdBcpsP-PpsP-PmVP-PKΩVVmAmAmsVDCmA°CVoltage into 50Ω (VSWR ≤ 1.2) VO

CAUTION: Electrostatic Sensitive Device. Observe precautions for handling.NOTES:

1.2.3.4.5.6.

Unless otherwise noted, all specifications include any combination of load VSWR, VCC, and TA. In addition, Q and Q are terminated into 50Ω loads to ground. (See: Typical Test Circuit.)

One or more of the following United States patents apply: 4,616,197; 4,670,681; 4,760,352.

The design, manufacturing process, and specifications of this device are subject to change without notice.

Only under the nominal conditions of 50Ω load impedance with VSWR ≤ 1.2 and nominal power supply voltage.

Symmetry is defined as the pulse width (in percent of total period) measured at the 50% points of Q or Q. (See: Timing Definitions.)Jitter and other spurious outputs induced by externally generated

electrical noise on VCC or mechanical vibration are not included. Dedicated external voltage regulation and careful PCB layout are recommended for optimum performance.

Applies to period jitter of Q and Q. Measurements are made with the Tektronix CSA803 signal analyzer with at least 1000 samples.

Period jitter measured with a 200mVP-P sine wave swept from 1MHz to one-half of fO at the VCC power supply terminal.

The outputs are enabled when Terminal 8 is at logic HIGH.

Propagation delay is defined as the time from the 50% point on the rising edge of ENABLE to the 90% point on the rising edge of the output amplitude or as the fall time from the 50% point to the 10% point. (SEE: Timing Definitions.)Page 1 of 2

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Electrical Connections

Footprint

Actual size footprint:

TerminalNumber

12345678LIDConnection

VCCGroundNC or GroundQ OutputQ Output

12348 765TOP VIEWTypical Printed Circuit Board Land Pattern

A typical land pattern for a circuit board is shown below. Grounding of the metallic center pad is optional.

GroundENABLEGroundCase Design

All pads consist of 30 microinches (min) electroless gold on 50 microinches (min) electroless nickel over base metal. The metallic center pad was designed for mechanical support. Grounding of this pad is optional.Lid symbolization, including terminal 1 locator dot, are in contrasting ink. Symbolization varies by model number. For purposes of illustration, only terminal 1 dot is shown.

BTypically 0.01\" to 0.05\" or 0.25 mm to1.25 mm (8 Places)(The optimum value of this dimension isdependent on the PCB assembly processemployed.).

Typical Test Circuit

Vcc4.7 μH0.1 μFSine-WaveSignal GeneratorCDENA(X8)F(X8)MGL(X3)VccH(X2)50 ΩQ50 ΩQ*TektronixCSA 803DigitizingOscilloscopeCh 1TriggerCh 2ClockUnder TestENABLE*KJ50 ΩDimensions

ABCDEFGHJKLMN

MillimetersMinMax

13.469.14

13.979.66

InchesMin

0.5300.360

*Power Splitter, Mini-Circuits ZFSC2-4Max

0.5500.380

Timing Definitions

2.05 Nominal3.56 Nominal2.24 Nominal1.27 Nominal2. Nominal3.05 Nominal1.93 Nominal5. Nominal4.32 Nominal4.83 Nominal0.50 Nominal

0.081 Nominal0.141 Nominal0.088 Nominal0.050 Nominal0.100 Nominal0.120 Nominal0.076 Nominal0.218 Nominal0.170 Nominal0.190 Nominal0.020 Nominal

Propagation Delay:ENABLE50%50%Q or Q OutputAmplitudeEnvelope90%10%tPDSymmetry:tPDMaterials

Solder Pad Ter-Au plating 30 - 60 µinches (76.2-152 µm) over 80-200 minationµinches (203-508 µm) Ni.LidBody

Fe-Ni-Co Alloy Electroless Nickel Plate (8-11% Phos-phorus) 100-200 µinches ThickAl2O3 Ceramic

Q or Q Output50%50%50%Symmetry as% of PeriodPeriodSymmetry as% of Periodwww.RFM.comE-mail: info@rfm.com©2008 by RF Monolithics, Inc.Page 2 of 2

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RFMSC3041B