专利名称：Bump-on-Trace (BOT) Structures and
Methods for Forming the Same
发明人：Chen-Hua Yu,Chien-Hsun Lee,Jiun Yi Wu申请号：US13789852申请日：20130308
公开号：US20140252596A1公开日：20140911
专利附图：
摘要：An integrated circuit structure includes a package component, which includes adielectric layer and a metal trace over and in contact with the dielectric layer. Thedielectric layer includes a first dielectric material and a second dielectric material in the
first dielectric material. The first dielectric material is a flowable and curable material. Thesecond dielectric material comprises a functional group selected from the groupconsisting essentially of (—C—N—), (—C—O—), (—N—C═O), and combinations thereof.
申请人：TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
地址：US
国籍：US
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