Philips SemiconductorsProduct data sheetParallel bus to I2C-bus controllerPCA9564DESCRIPTIONThe PCA9564 is an integrated circuit designed in CMOS technologythat serves as an interface between most standard parallel-busmicrocontrollers/microprocessors and the serial I2C-bus and allowsthe parallel bus system to communicate bi-directionally with theI2C-bus. The PCA9564 can operate as a master or a slave and canbe a transmitter or receiver. Communication with the I2C-bus iscarried out on a byte-wise basis using interrupt or polled handshake.The PCA9564 controls all the I2C-bus specific sequences, protocol,arbitration and timing with no external timing element required.FEATURES•Parallel-bus to I2C-bus protocol converter and interfaceThe PCA9564 is similar to the PCF8584 but operates at lowervoltages and higher I@C frequencies. Other enhancements•Both master and slave functionsrequested by design engineers have also been incorporated.•Multi-master capabilityCharacteristicPCA9564PCF8584Comments•Internal oscillator reduces external componentsVoltage range2.3–3.6 V4.5–5.5 VPCA9564 is 5 V•tolerantOperating supply voltage 2.3 V to 3.6 V•Maximum360 kHz90 kHzFaster I2C interface5 V tolerant I/Osmaster mode•I2C frequencyStandard and fast mode I2C capable and compatible with SMBus•Maximum slave400 kHz100 kHzFaster I2C interfaceESD protection exceeds 2000 V HEM per JESD22-A114,mode I2C200 V MM per JESD22-A115, and 1000 V CDM perfrequencyJESD22-C101Clock sourceInternalExternalLess expensive and•Latch-up testing is done to JEDEC Standard JESD78 whichmore flexible withexceed 100 mA.internal oscillator•Packages offered: DIP20, SO20, TSSOP20, HVQFN20ParallelFastSlowCompatible withinterface50 MHzfaster processorsAPPLICATIONS•While the PCF8584 supported most parallel-bus microcontrollers/Add I2C-bus port to controllers/processors that do not have onemicroprocessors including the Intel 8049/8051, Motorola•Add additional I2C-bus ports to controllers/processors that need6800/68000 and the Zilog Z80, the PCA9564 has been designed tomultiple I2C-bus portsbe very similar to the Philips standard 80C51 microcontroller I2C•hardware so the devices are not code compatible. Additionally, theHigher frequency, lower voltage migration path for the PCF8584PCA9564 does not support the bus monitor “Snoop” mode nor the•Converts 8 bits of parallel data to serial data stream to preventlong distance mode and is not footprint compatible with thehaving to run a large number of traces across the entire PC boardPCF8584.ORDERING INFORMATIONPACKAGESTEMPERATURE RANGEORDER CODETOPSIDE MARKDRAWING NUMBER20-Pin Plastic DIP–40 °C to +85 °CPCA9564NPCA9564NSOT146-120-Pin Plastic SO–40 °C to +85 °CPCA9564DPCA9564DSOT163-120-Pin Plastic TSSOP–40 °C to +85 °CPCA9564PWPCA9564SOT360-120-Pin Plastic HVQFN–40 °C to +85 °CPCA9564BS9564SOT662-1whole wafer–40 °C to +85 °CPCA9564Un/an/aStandard packing quantities and other packaging data are available at www.standardics.philips.com/packaging.2006 Sep 01 2Philips SemiconductorsProduct data sheetParallel bus to I2C-bus controllerPCA9564PIN CONFIGURATION — DIP, SO, TSSOPPIN CONFIGURATION — HVQFNDAD0120VDD210DDDDDVSD1219SDA0987621111D2318SCLD3115SCLD3417RESETD4214RESETD4516INTD53D5615A1TOP VIEW13INTD6412A1D6714A0D7813CED7511A0DNU912RD678901USRDEVSS1011WRNDVSWRCSW02260SW02261PIN DESCRIPTIONPIN NUMBERPINDIP, SO, TSSOPHVQFNSYMBOLTYPENAME AND FUNCTION1, 2, 3, 4, 1, 2, 3, 4, 5,D0–D7I/OData Bus: Bi-directional 3-State data bus used to transfer commands, data and5, 6, 7, 818, 19, 20status between the controller and the CPU. D0 is the least significant bit.96DNUDo not use: must be left floating (pulled LOW internally)1071VSSPwrGround118WRIWrite Strobe: When LOW and CE is also LOW, the contents of the data bus isloaded into the addressed register. The transfer occurs on the rising edge of thesignal.129RDIRead Strobe: When LOW and CE is also LOW, causes the contents of theaddressed register to be presented on the data bus. The read cycle begins on thefalling edge of RD.1310CEIChip Enable: Active-LOW input signal. When LOW, data transfers between the CPUand the controller are enabled on D0–D7 as controlled by the WR, RD and A0–A1inputs. When HIGH, places the D0–D7 lines in the 3-State condition.14, 1511, 12A0, A1IAddress Inputs: Selects the controller internal registers and ports for read/writeoperations.1613INTOInterrupt Request: Active-LOW, open-drain, output. This pin requires a pull-updevice.1714RESETIReset: A LOW level clears internal registers resets the I2C state machine.1815SCLI/OI2C-bus serial clock input/output (open-drain).1916SDAI/OI2C-bus serial data input/output (open-drain).2017VDDPwrPower Supply: 2.3 to 3.6 VNOTES:1.HVQFN package die supply ground is connected to both VSS pin and exposed center pad. VSS pin must be connected to supply ground forproper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the boardusing a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated inthe PCB in the thermal pad region.2006 Sep 01 3Philips SemiconductorsProduct data sheetParallel bus to I2C-bus controllerPCA9564DATAD7D6D5D4D3D2D1D0PCA9564SDAFILTERBUS BUFFERA1A0SDA CONTROLSD7SD6SD5SD4SD3SD2SD1SD001I2CDAT – DATA REGISTER – READ/WRITETETO6TO5TO4TO3TO2TO1TO0AAENSIOSTASTOSI00I2CTO – TIMEOUT REGISTER – WRITE ONLYSCLFILTERBIT7BIT6BIT5BIT4BIT3BIT2BIT1BIT010SCL CONTROLI2CADR – OWN ADDRESS – READ/WRITEST7ST6ST5ST4ST3ST2ST1ST000I2CSTA – STATUS REGISTER – READ ONLYENSIOSTASTOSIAAENSIOSTASTOSICR2CR1CR011I2CCON – CONTROL REGISTER – READ/WRITECR0CLOCK SELECTORCR1CONTROL BLOCKCR2INTERRUPT CONTROLPOWER–ONRESETOSCILLATORCEWRRDINTRESETA1A0VDDCONTROL SIGNALSSW02262Figure 1. Block diagram2006 Sep 01 4Philips SemiconductorsProduct data sheetParallel bus to I2C-bus controllerPCA9564FUNCTIONAL DESCRIPTIONThe Address Register, I2CADR: I2CADR is not affected by theSIO hardware. The contents of this register are irrelevant when SIOGeneralis in a master mode. In the slave modes, the seven most significantThe PCA9564 acts as an interface device between standardbits must be loaded with the microcontroller’s own slave address.high-speed parallel buses and the serial I2C-bus. On the I2C-bus, itcan act either as master or slave. Bidirectional data transfer between76543210the I2C-bus and the parallel-bus microcontroller is carried out on aI2CADRBIT7BIT6BIT5BIT4BIT3BIT2BIT10byte-wise basis, using either an interrupt or polled handshake.own slave addressInternal OscillatorThe most significant bit corresponds to the first bit received from theThe PCA9564 contains an internal 9 MHz oscillator which is usedI2C-bus after a start condition. A logic 1 in I2CADR corresponds to afor all I2C timing. The oscillator requires up to 500 µs to start-upHIGH level on the I2C-bus, and a logic 0 corresponds to a LOWafter ENSIO bit is set to “1”.level on the bus. The least significant bit is not used but should beRegistersprogrammed with a ‘0’.The PCA9564 contains four registers which are used to configureThe Data Register, I2CDAT: I2CDAT contains a byte of serial datathe operation of the device as well as to send and receive serial data.to be transmitted or a byte which has just been received. In mastermode, this includes the slave address that the master wants to sendThe registers are selected by setting pins A0 and A1 to theout on the I2C-bus, with the most significant bit of the slave addressappropriate logic levels before a read or write operation is executed.in the SD7 bit position and the Read/Write bit in the SD0 bit position.CAUTION:Do not write to I2C registers while the I2C-bus is busyThe CPU can read from and write to this 8-bit register while it is notand the SIO is in master or addressed slave mode.in the process of shifting a byte. This occurs when SIO is in adefined state and the serial interrupt flag is set. Data in I2CDATREGISTERREGISTERremains stable as long as SI is set. Whenever the SIO generates anNAMEFUNCTIONA1A0READ/WRITEDEFAULTinterrupt, the I2CDAT registers contain the data byte that was justI2CSTAStatus00RF8htransferred on the I2C-bus.I2CTOTime-out00WFFhNOTE: The I2CDAT register will capture the serial address as dataI2CDATData01R/W00hwhen addressed via the serial bus. Also, the data register willcontinue to capture data from the serial bus during 38H so theI2CADROwn address10R/W00hI2CDAT register will need to be reloaded when the bus becomesI2CCONControl11R/W00hfree.76543210The Time-out Register, I2CTO: The time-out register is used todetermine the maximum time that SCL is allowed to be LOW beforeI2CDATSD7SD6SD5SD4SD3SD2SD1SD0the I2C state machine is reset.When the I2C interface is operating, I2CTO is loaded in the time-out•SD7 - SD0:counter at every SCL transition.Eight bits to be transmitted or just received. A logic 1 in I2CDATcorresponds to a HIGH level on the I2C-bus, and a logic 076543210corresponds to a LOW level on the bus.I2CTOTETO6TO5TO4TO3TO2TO1TO0The Control Register, I2CCON: The microcontroller can read fromTime-out valueand write to this 8-bit register. Two bits are affected by the SIOhardware: the SI bit is set when a serial interrupt is requested, andThe most significant bit of I2CTO (TE) is used as a time-outthe STO bit is cleared when a STOP condition is present on theenable/disable. A “1” will enable the time-out function. The time-outI2C-bus. A write to the I2CCON register clears the SI bit and causesperiod = (I2CTO[6:0] + 1) × 113.7 µs. The time-out value may varythe Serial Interrupt line to be de–asserted and the next clock pulsesome and is an approximate value.on the SCL line to be generated. Since none of the registers shouldThe time-out register can be used in the following cases:be written to via the parallel interface once the Serial Interrupt linehas been de-asserted, all the other registers that need to be1.When the SIO, in the master mode, wants to send a STARTmodified should be written to before the content of the I2CCONcondition and the SCL line is held LOW by some other device.register is modified.The SIO waits a time period equivalent to the time-out value forthe SCL to be released. In case it is not released, the SIO76543210concludes that there is a bus error, loads 90H in the I2CSTAI2CCONAAENSIOSTASTOSICR2CR1CR0register, generates an interrupt signal and releases the SCL andSDA lines. After the microcontroller reads the status register, it•ENSIO, THE SIO ENABLE BITneeds to send an external reset in order to reset the SIO.ENSIO = “0”: When ENSIO is “0”, the SDA and SCL outputs are in ahigh impedance state. SDA and SCL input signals are ignored, SIO2.In the master mode, the time-out feature starts every time the SCLis in the “not addressed” slave state.goes LOW. If SCL stays LOW for a time period equal to or greaterthan the time-out value, the SIO concludes there is a bus errorENSIO = “1”: When ENSIO is “1”, SIO is enabled.and behaves in the manner described above.After the ENSIO bit is set, it takes 500 µs for the internal oscillator to3.In case of a forced access to the I2C-bus. (See more details onstart up, therefore, the PCA9564 will enter either the master or thepage 15.)slave mode after this time. ENSIO should not be used to temporarily2006 Sep 01 5Philips SemiconductorsParallel bus to I2C-bus controllerrelease the PCA9564 from the I2C-bus since, when ENSIO is reset,the I2C-bus status is lost. The AA flag should be used instead (seedescription of the AA flag in the following text).In the following text, it is assumed that ENSIO = “1”.•STA, THE START FLAGSTA = “1”: When the STA bit is set to enter a master mode, the SIOhardware checks the status of the I2C-bus and generates a STARTcondition if the bus is free. If the bus is not free, then SIO waits for aSTOP condition (which will free the bus) and generates a STARTcondition after the minimum buffer time (tBUF) has elapsed.If STA is set while SIO is already in a master mode and one or morebytes are transmitted or received, SIO transmits a repeated STARTcondition. STA may be set at any time. STA may also be set whenSIO is an addressed slave.STA = “0”: When the STA bit is reset, no START condition orrepeated START condition will be generated.•STO, THE STOP FLAGSTO = “1”: When the STO bit is set while SIO is in a master mode, aSTOP condition is transmitted to the I2C-bus. When the STOPcondition is detected on the bus, the SIO hardware clears the STOflag.If the STA and STO bits are both set, then a STOP condition istransmitted to the I2C-bus if SIO is in a master mode. SIO thentransmits a START condition.STO = “0”: When the STO bit is reset, no STOP condition will begenerated.•SI, THE SERIAL INTERRUPT FLAGSI = “1”: When the SI flag is set, then, if the ENSIO bit is also set, aserial interrupt is requested. SI is set by hardware when one of 24 ofthe 25 possible SIO states is entered. The only state that does notcause SI to be set is state F8H, which indicates that no relevantstate information is available.While SI is set, the LOW period of the serial clock on the SCL line isstretched, and the serial transfer is suspended. A HIGH level on theSCL line is unaffected by the serial interrupt flag. SI must be resetby writing “0” to the SI bit. The SI bit cannot be set by the user.SI = “0”: When the SI flag is reset, no serial interrupt is requested,and there is no stretching of the serial clock on the SCL line.•AA, THE ASSERT ACKNOWLEDGE FLAGAA = “1”: If the AA flag is set, an acknowledge (LOW level to SDA)will be returned during the acknowledge clock pulse on the SCL linewhen:–The “own slave address” has been received–A data byte has been received while SIO is in the master receivermode–A data byte has been received while SIO is in the addressedslave receiver modeAA = “0”: if the AA flag is reset, a not acknowledge (HIGH level toSDA) will be returned during the acknowledge clock pulse on SCLwhen:–A data byte has been received while SIO is in the master receivermode2006 Sep 01Product data sheetPCA9564–A data byte has been received while SIO is in the addressedslave receiver mode–“Own slave address” has been receivedWhen SIO is in the addressed slave transmitter mode, state C8Hwill be entered after the last serial is transmitted (see Figure 5).When SI is cleared, enters the not addressed slave receiver mode,and the SDA line remains at a HIGH level. In state C8H, the AA flagcan be set again for future address recognition.When SIO is in the not addressed slave mode, its own slaveaddress is ignored. Consequently, no acknowledge is returned, anda serial interrupt is not requested. Thus, SIO can be temporarilyreleased from the I2C-bus while the bus status is monitored. WhileSIO is released from the bus, START and STOP conditions aredetected, and serial data is shifted in. Address recognition can beresumed at any time by setting the AA flag.•THE CLOCK RATE BITS, CR2, CR1, AND CR0Three bits determine the serial clock frequency when SIO is inmaster mode. The various serial rates are shown in Table 1.The clock frequencies only take the HIGH and LOW times intoconsideration. The rise and fall time will cause the actual measuredfrequency to be lower than expected.The frequencies shown in Table 1 are unimportant when SIO is in aslave mode. In the slave modes, SIO will automatically synchronizewith any clock frequency up to 400 kHz.Table 1. Serial Clock RatesCR2CR1CR0SERIAL CLOCK FREQUENCY(kHz)000330001288010217011146100881101591104411136NOTE:1.The clock frequency values are approximate and may varywith temperature, supply voltage, process, and SCL outputloading. If normal mode I2C parameters must be strictly followed(SCL < 100kHz), it is recommended not to use CR[2:0] = 100 (SCL = 88kHz) since the clock frequency might beslightly higher than 100 kHz under certain temperature, voltage,and process conditions and use CR[2:0] = 101 (SCL = 59 kHz)instead.The Status Register, I2CSTA: I2CSTA is an 8-bit read-only register.The three least significant bits are always zero. The five mostsignificant bits contain the status code. There are 25 possible statuscodes. When I2CSTA contains F8H, no relevant state information isavailable and no serial interrupt is requested. All other I2CSTAvalues correspond to defined SIO states. When each of these statesis entered, a serial interrupt is requested (SI = “1”). 6Philips SemiconductorsParallel bus to I2C-bus controllerMore Information on SIO Operating ModesThe four operating modes are:–Master Transmitter–Master Receiver–Slave Receiver–Slave TransmitterData transfers in each mode of operation are shown in Figures 2–5.These figures contain the following abbreviations:AbbreviationExplanationSStart conditionSLA7-bit slave addressRRead bit (HIGH level at SDA)WWrite bit (LOW level at SDA)AAcknowledge bit (LOW level at SDA)ANot acknowledge bit (HIGH level at SDA)Data8-bit data bytePStop conditionIn Figures 2-5, circles are used to indicate when the serial interruptflag is set. A serial interrupt is not generated when I2CSTA = F8H.This happens on a stop condition. The numbers in the circles showthe status code held in the I2CSTA register. At these points, a serviceroutine must be executed to continue or complete the serial transfer.These service routines are not critical since the serial transfer issuspended until the serial interrupt flag is cleared by software.When a serial interrupt routine is entered, the status code in I2CSTAis used to branch to the appropriate service routine. For each statuscode, the required software action and details of the following serialtransfer are given in Tables 2-6.Master Transmitter Mode: In the master transmitter mode, anumber of data bytes are transmitted to a slave receiver (seeFigure 2). Before the master transmitter mode can be entered,I2CCON must be initialized as follows:76543210I2CCONAAENSIOSTASTOSICR2CR1CR0X1000bit rateENSIO must be set to logic 1 to enable SIO. If the AA bit is reset,SIO will not acknowledge its own slave address in the event ofanother device becoming master of the bus. In other words, if AA isreset, SIO cannot enter a slave mode. STA, STO, and SI must bereset.The master transmitter mode may now be entered by setting theSTA bit. The SIO logic will now test the I2C-bus and generate a startcondition as soon as the bus becomes free. When a STARTcondition is transmitted, the serial interrupt flag (SI) is set, and thestatus code in the status register (I2CSTA) will be 08H. This statuscode must be used to vector to an interrupt service routine thatloads I2CDAT with the slave address and the data direction bit(SLA+W). The SI bit in I2CCON must then be reset before the serialtransfer can continue.When the slave address and the direction bit have been transmittedand an acknowledgment bit has been received, the serial interruptflag (SI) is set again, and a number of status codes in I2CSTA arepossible. There are 18H, 20H, or 38H for the master mode and also68H, or B0H if the slave mode was enabled (AA = logic 1). Theappropriate action to be taken for each of these status codes isdetailed in Table 2. After a repeated start condition (state 10H). SIOmay switch to the master receiver mode by loading I2CDAT withSLA+R).Note that a master should never transmit its own slaveaddress.2006 Sep 01Product data sheetPCA9564Master Receiver Mode: In the master receiver mode, a number ofdata bytes are received from a slave transmitter (see Figure 3). Thetransfer is initialized as in the master transmitter mode. When thestart condition has been transmitted, the interrupt service routinemust load I2CDAT with the 7-bit slave address and the datadirection bit (SLA+R). The SI bit in I2CCON must then be clearedbefore the serial transfer can continue.When the slave address and the data direction bit have beentransmitted and an acknowledgment bit has been received, theserial interrupt flag (SI) is set again, and a number of status codes inI2CSTA are possible. These are 40H, 48H, or 38H for the mastermode and also 68H, or B0H if the slave mode was enabled (AA =logic 1). The appropriate action to be taken for each of these statuscodes is detailed in Table 3. ENSIO is not affected by the serialtransfer and are not referred to in Table 3. After a repeated startcondition (state 10H), SIO may switch to the master transmittermode by loading I2CDAT with SLA+W.Note that a master should not transmit its own slave address.Slave Receiver Mode: In the slave receiver mode, a number ofdata bytes are received from a master transmitter (see Figure 4). Toinitiate the slave receiver mode, I2CADR and I2CCON must beloaded as follows:76543210I2CADRBIT7BIT6BIT5BIT4BIT3BIT2BIT10own slave addressThe upper 7 bits are the address to which SIO will respond whenaddressed by a master.76543210I2CCONAAENSIOSTASTOSICR2CR1CR011000XXXENSIO must be set to logic 1 to enable SIO. The AA bit must be setto enable SIO to acknowledge its own slave address, STA, STO,and SI must be reset.When I2CADR and I2CCON have been initialized, SIO waits until itis addressed by its own slave address followed by the data directionbit which must be “0” (W) for SIO to operate in the slave receivermode. After its own slave address and the W bit have beenreceived, the serial interrupt flag (I) is set and a valid status codecan be read from I2CSTA. This status code is used to vector to aninterrupt service routine, and the appropriate action to be taken foreach of these status codes is detailed in Table 4. The slave receivermode may also be entered if arbitration is lost while SIO is in themaster mode (see status 68H).If the AA bit is reset during a transfer, SIO will return a notacknowledge (logic 1) to SDA after the next received data byte.While AA is reset, SIO does not respond to its own slave address.However, the I2C-bus is still monitored and address recognition maybe resumed at any time by setting AA. This means that the AA bitmay be used to temporarily isolate SIO from the I2C-bus. 7Philips SemiconductorsProduct data sheetParallel bus to I2C-bus controllerPCA9564MTSUCCESSFUL TRANSMISSIONTO A SLAVE RECEIVERSSLAWADATAAP08H18H28HF8NEXT TRANSFER STARTED WITH A REPEATED START CONDITIONSSLAW10HNOT ACKNOWLEDGE RECEIVED AFTER THE SLAVE ADDRESSAPR20HF8HTO MST/REC MODENOT ACKNOWLEDGE RECEIVED AFTER A DATA BYTEAENTRY = MRP30HF8HARBITRATION LOST IN SLAVE ADDRESS OR DATA BYTEA or AOTHER MSTCONTINUESA or AOTHER MSTCONTINUES38H38HARBITRATION LOST AND ADDRESSED AS SLAVEAOTHER MSTCONTINUES68HTO CORRESPONDING STATES INSLAVE RECEIVER MODEFROM MASTER TO SLAVEB0HTO CORRESPONDING STATES INSLAVE TRANSMITTER MODEFROM SLAVE TO MASTERDataAANY NUMBER OF DATA BYTES AND THEIR ASSOCIATED ACKNOWLEDGE BITSnTHIS NUMBER (CONTAINED IN I2CSTA) CORRESPONDS TO A DEFINED STATE OF THE I2C BUS. SEE TABLE 2.NOTE: THE MASTER SHOULD NEVER TRANSMIT ITS OWN SLAVE ADDRESSSW00816Figure 2. Format and states in the master transmitter mode2006 Sep 01 8Philips SemiconductorsProduct data sheetParallel bus to I2C-bus controllerPCA9564MRSUCCESSFUL RECEPTIONFROM A SLAVE TRANSMITTERSSLARADATAADATAAP08H40H50H58HF8HNEXT TRANSFER STARTED WITH AREPEATED START CONDITIONSSLAR10HNOT ACKNOWLEDGE RECEIVEDAFTER THE SLAVE ADDRESSAPW48HF8HTO MST/TRX MODEENTRY = MTARBITRATION LOST IN SLAVE ADDRESSOTHER MSTOR ACKNOWLEDGE BITA or AOTHER MSTCONTINUESACONTINUES38H38HARBITRATION LOST AND ADDRESSED AS SLAVEAOTHER MSTCONTINUES68HTO CORRESPONDING STATES INSLAVE RECEIVER MODEB0HTO CORRESPONDING STATES INSLAVE TRANSMITTER MODEFROM MASTER TO SLAVEFROM SLAVE TO MASTERDATAAANY NUMBER OF DATA BYTES AND THEIR ASSOCIATED ACKNOWLEDGE BITSnTHIS NUMBER (CONTAINED IN I2CSTA) CORRESPONDS TO A DEFINED STATE OF THE I2C BUS. SEE TABLE 3.SW00817Figure 3. Format and states in the master receiver mode2006 Sep 01 9Philips SemiconductorsProduct data sheetParallel bus to I2C-bus controllerPCA9564RECEPTION OF THE OWN SLAVE ADDRESSAND ONE OR MORE DATA BYTESSSLAWADATAADATASLAAP or SALL ARE ACKNOWLEDGED.60H80H80HA0HLAST DATA BYTE RECEIVED ISNOT ACKNOWLEDGEDAP or S88HF8HARBITRATION LOST AS MST ANDON STOPADDRESSED AS SLAVEA68HFROM MASTER TO SLAVEP or SFROM SLAVE TO MASTERF8ON STOPDataAANY NUMBER OF DATA BYTES AND THEIR ASSOCIATED ACKNOWLEDGE BITSnTHIS NUMBER (CONTAINED IN I2CSTA) CORRESPONDS TO A DEFINED STATE OF THE I2C BUS. SEE TABLE 4.SW00814Figure 4. Format and states in the slave receiver modeRECEPTION OF THEOWN SLAVE ADDRESSAND TRANSMISSIONSSLARADATAADATAAP or SOF ONE OR MOREDATA BYTESA8HB8HC0HF8HON STOPARBITRATION LOST AS MSTAND ADDRESSED AS SLAVEAFROM MASTER TO SLAVEB0HLAST DATA BYTE TRANSMITTED.SWITCHED TO NOT ADDRESSEDAAll “1”sP or SSLAVE (AA BIT IN I2CCON = “0”)FROM SLAVE TO MASTERC8HF8HDATAAANY NUMBER OF DATA BYTES AND THEIR ASSOCIATED ACKNOWLEDGE BITSON STOPnTHIS NUMBER (CONTAINED IN I2CSTA) CORRESPONDS TO A DEFINED STATE OF THE I2C BUS. SEE TABLE 5.SW00815Figure 5. Format and states of the slave transmitter mode2006 Sep 01 10Philips SemiconductorsProduct data sheetParallel bus to I2C-bus controllerPCA9564Table 2. Master Transmitter ModeSTATUSSTATUS OF THESTATUSOFTHEAPPLICATION SOFTWARE RESPONSECODEI2C BUS ANDNEXT ACTION TAKEN BY SIO HARDWARE(I2CSTA)SIOSIO HARDWAREHARDWARETO/FROMTO/FROM I2CDATI2CDATTO I2CCONSTASTOSIAA08HA START condition hasLoad SLA+WXX0XSLA+W will be transmitted;been transmittedACK bit will be received10HA repeated STARTLoad SLA+W orXX0XAs abovecondition has beenditihbtransmittedLoad SLA+RXX0XSLA+R will be transmitted;SIO will be switched to MST/REC mode18HSLA+W has been Load data byte or000XData byte will be transmitted;transmitted; ACK hasACK bit will be receivedbbeen receivedidno I2CDAT action or100XRepeated START will be transmitted;no I2CDAT action or010XSTOP condition will be transmitted;STO flag will be resetno I2CDAT action110XSTOP condition followed by a START condition will be transmitted;STO flag will be reset20HSLA+W has been Load data byte or000XData byte will be transmitted;transmitted; NOT ACKACK bit will be receivedhhas been receivedbidno I2CDAT action or100XRepeated START will be transmitted;no I2CDAT action or010XSTOP condition will be transmitted;STO flag will be resetno I2CDAT action110XSTOP condition followed by a START condition will be transmitted;STO flag will be reset28HData byte in I2CDATLoad data byte or000XData byte will be transmitted;has been transmitted;ACK bit will be receivedACKACK has been receivedhbidno I2CDAT action or100XRepeated START will be transmitted;no I2CDAT action or010XSTOP condition will be transmitted;STO flag will be resetno I2CDAT action110XSTOP condition followed by a START condition will be transmitted;STO flag will be reset30HData byte in I2CDATLoad data byte or000XData byte will be transmitted;has been transmitted;ACK bit will be receivedNOTNOT ACK has beenACKhbreceivedno I2CDAT action or100XRepeated START will be transmitted;no I2CDAT action or010XSTOP condition will be transmitted;STO flag will be resetno I2CDAT action110XSTOP condition followed by a START condition will be transmitted;STO flag will be reset38HArbitration lost in No I2CDAT action or000XI2C-bus will be released;SLA+W ornot addressed slave will be enteredDData bytesbNo I2CDAT action100XA START condition will be transmitted when thebus becomes free (STOP or SCL and SDA high)2006 Sep 01 11Philips SemiconductorsProduct data sheetParallel bus to I2C-bus controllerPCA9564Table 3. Master Receiver ModeSTATUSSTATUS OF THE STATUSAPPLICATION SOFTWARE RESPONSECODE2OFTHEIC BUS AND NEXT ACTION TAKEN BY SIO HARDWARE(I2CSTA)SIOSIO HARDWAREHARDWARETO/FROMTO/FROM I2CDATI2CDATTO I2CCONSTASTOSIAA08HA START condition hasLoad SLA+RXX0XSLA+R will be transmitted;been transmittedACK bit will be received10HA repeated STARTLoad SLA+R orXX0XAs abovecondition has been ditihbtransmittedLoad SLA+WXX0XSLA+W will be transmitted;SIO will be switched to MST/TRX mode38HArbitration lost in No I2CDAT action or000XI2C-bus will be released;NOT ACK bitSIO will enter a slave modeNo I2CDAT action100XA START condition will be transmitted when thebus becomes free40HSLA+R has been No I2CDAT action or0000Data byte will be received;transmitted; ACK hasNOT ACK bit will be returnedbbeen receivedidno I2CDAT action0001Data byte will be received;ACK bit will be returned48HSLA+R has been No I2CDAT action or100XRepeated START condition will be transmittedttransmitted; NOT ACKittdNOTACKhas been receivedno I2CDAT action or010XSTOP condition will be transmitted;STO flag will be resetno I2CDAT action110XSTOP condition followed by a START condition will be transmitted;STO flag will be reset50HData byte has been Read data byte or0000Data byte will be received;received; ACK has beenNOT ACK bit will be returnedreturneddread data byte0001Data byte will be received;ACK bit will be returned58HData byte has been Read data byte or100XRepeated START condition will be transmittedreceived; NOT ACK hasidNOTACKhbeen returnedread data byte or010XSTOP condition will be transmitted;STO flag will be resetread data byte110XSTOP condition followed by a START condition will be transmitted;STO flag will be reset38HArbitration lost in No I2CDAT action or000XI2C-bus will be released;SLA+Rnot addressed slave will be enteredNo I2CDAT action100XA START condition will be transmitted when thebus becomes free2006 Sep 01 12Philips SemiconductorsProduct data sheetParallel bus to I2C-bus controllerPCA9564Table 4. Slave Receiver ModeSTATUSSTATUS OF THESTATUSOFTHEAPPLICATION SOFTWARE RESPONSECODEI2C BUS ANDNEXT ACTION TAKEN BY SIO HARDWARE(I2CSTA)SIOSIO HARDWAREHARDWARETO/FROMTO/FROM I2CDATI2CDATTO I2CCONSTASTOSIAA60HOwn SLA+W hasNo I2CDAT actionXX00Data byte will be received and NOT ACK will bebeen received; ACKorreturnedhhas been returnedbdno I2CDAT actionXX01Data byte will be received and ACK will be returned68HArbitration lost inNo I2CDAT actionXX00Data byte will be received and NOT ACK will beSLA+R/W as master;orreturnedOwn SLA+W hasbeen received, ACKreturnedno I2CDAT actionXX01Data byte will be received and ACK will be returned80HPreviously addressedRead data byte orXX00Data byte will be received and NOT ACK will bewith own SLVreturnedaddress; DATA hasbeen received; ACKhas been returnedread data byteXX01Data byte will be received and ACK will be returned88HPreviously addressedRead data byte or0X00Switched to not addressed SLV mode; no recognitionwith own SLA; DATAof own SLAbbyte has beenhbreceived; NOT ACKread data byte or0X01Switched to not addressed SLV mode; Own SLA willhas been returnedhasbeenreturnedbe recognizedread data byte or1X00Switched to not addressed SLV mode; no recognitionof own SLA. A START condition will be transmittedwhen the bus becomes freeread data byte1X01Switched to not addressed SLV mode; Own SLA willbe recognized. A START condition will be transmittedwhen the bus becomes free.A0HA STOP condition orNo I2CDAT action0X00Switched to not addressed SLV mode; no recognitionrepeated STARTorof own SLAcondition has beendiihbreceived while stillNo I2CDAT action0X01Switched to not addressed SLV mode; Own SLA willaddressedaddressed asasorbe recognizedSLV/RECNo I2CDAT action1X00Switched to not addressed SLV mode; no recognitionorof own SLA. A START condition will be transmittedwhen the bus becomes freeNo I2CDAT action1X01Switched to not addressed SLV mode; Own SLA willbe recognized. A START condition will be transmittedwhen the bus becomes free.2006 Sep 01 13Philips SemiconductorsProduct data sheetParallel bus to I2C-bus controllerPCA9564Table 5. Slave Transmitter ModeSTATUSSTATUS OF THESTATUSAPPLICATION SOFTWARE RESPONSECODE2OFTHEIC BUS ANDTO I2CCONNEXT ACTION TAKEN BY SIO HARDWARE(I2CSTA)SIOSIO HARDWAREHARDWARETO/FROMTO/FROM I2CDATI2CDATSTASTOSIAAA8HOwn SLA+R hasLoad data byte orXX00Last data byte will be transmitted and ACK bit will bebeen received; ACKreceivedhhas been returnedbdload data byteXX01Data byte will be transmitted; ACK will be receivedB0HArbitration lost inLoad data byte orXX00Last data byte will be transmitted and ACK bit will beSLA+R/W as master;receivedOwnOwn SLA+R hasSLA+Rhasbeen received, ACKload data byteXX01Data byte will be transmitted; ACK bit will behas been returnedreceivedB8HData byte in I2CDATLoad data byte orXX00Last data byte will be transmitted and ACK bit will behas been transmitted;receivedACKACK has beenhbreceivedload data byteXX01Data byte will be transmitted; ACK bit will bereceivedC0HData byte in I2CDATNo I2CDAT action0X00Switched to not addressed SLV mode; no recognitionhas been transmitted;orof own SLANOTNOT ACK has beenACKhbreceivedno I2CDAT action or0X01Switched to not addressed SLV mode; Own SLA willbe recognizedno I2CDAT action or1X00Switched to not addressed SLV mode; no recognitionof own SLA. A START condition will be transmittedwhen the bus becomes freeno I2CDAT action1X01Switched to not addressed SLV mode; Own SLA willbe recognized. A START condition will be transmittedwhen the bus becomes free.C8HLast data byte inNo I2CDAT action0X00Switched to not addressed SLV mode; no recognitionI2CDAT has beenorof own SLAtransmitted (AA = 0);id(AA0)ACK has beenno I2CDAT action or0X01Switched to not addressed SLV mode; Own SLA willreceivedbe recognizedno I2CDAT action or1X00Switched to not addressed SLV mode; no recognitionof own SLA. A START condition will be transmittedwhen the bus becomes freeno I2CDAT action1X01Switched to not addressed SLV mode; Own SLA willbe recognized. A START condition will be transmittedwhen the bus becomes free.Table 6. Miscellaneous StatesSTATUSSTATUS OF THESTATUSAPPLICATION SOFTWARE RESPONSE2OFTHECODEIC BUS ANDNEXT ACTION TAKEN BY SIO HARDWARE(I2CSTA)SIOSIO HARDWAREHARDWARETO/FROMTO/FROM I2CDATI2CDATTO I2CCONSTASTOSIAAF8HOn reset or STOPNo I2CDAT action1X0XGo into master mode; send STARTNo I2CDAT action0X00No recognition of own SLANo I2CDAT action0X01Will recognize own SLA70HBus errorReset SIO (Requires reset to return to state F8H)SDA stuck LOW90HBus errorReset SIO (Requires reset to return to state F8H)SCL stuck LOW00HBus error duringReset SIO (Requires reset to return to state F8H)master or slavemode, due to illegalSTART or STOPcondition2006 Sep 01 14Philips SemiconductorsProduct data sheetParallel bus to I2C-bus controllerPCA9564Slave Transmitter Mode: In the slave transmitter mode, a numberI2CSTA = 90H:of data bytes are transmitted to a master receiver (see Figure 5).This status code indicates that the SCL line is stuck LOW.Data transfer is initialized as in the slave receiver mode. WhenI2CADR and I2CCON have been initialized, SIO waits until it isSome Special Cases: The SIO hardware has facilities to handle theaddressed by its own slave address followed by the data directionfollowing special cases that may occur during a serial transfer:bit which must be “1” (R) for SIO to operate in the slave transmitter•SIMULTANEOUS REPEATED START CONDITIONS FROM TWO MASTERSmode. After its own slave address and the R bit have been received,A repeated START condition may be generated in the masterthe serial interrupt flag (SI) is set and a valid status code can betransmitter or master receiver modes. A special case occurs ifread from I2CSTA. This status code is used to vector to an interruptanother master simultaneously generates a repeated STARTservice routine, and the appropriate action to be taken for each ofcondition (see Figure 6). Until this occurs, arbitration is not lost bythese status codes is detailed in Table 5. The slave transmitter modeeither master since they were both transmitting the same data.may also be entered if arbitration is lost while SIO is in the mastermode (see state B0H).If the SIO hardware detects a repeated START condition on theI2C-bus before generating a repeated START condition itself, it willIf the AA bit is reset during a transfer, SIO will transmit the last byteuse the repeated START as its own and continue with the sending ofof the transfer and enter state C8H. SIO is switched to the notthe slave address.addressed slave mode and will ignore the master receiver if itcontinues the transfer. Thus the master receiver receives all 1s as•DATA TRANSFER AFTER LOSS OF ARBITRATIONserial data. While AA is reset, SIO does not respond to its own slaveArbitration may be lost in the master transmitter and master receiveraddress. However, the I2C-bus is still monitored, and addressmodes. Loss of arbitration is indicated by the following states inrecognition may be resumed at any time by setting AA. This meansI2CSTA; 38H, 68H, and B0H (see Figures 2 and 3).that the AA bit may be used to temporarily isolate SIO from theI2C-bus.NOTE: In order to exit state 38H, a Timeout, Reset, or externalStop are required.Miscellaneous States: There are four I2CSTA codes that do notcorrespond to a defined SIO hardware state (see Table 6). TheseIf the STA flag in I2CCON is set by the routines which service theseare discussed below.states, then, if the bus is free again, a START condition (state 08H)is transmitted without intervention by the CPU, and a retry of theI2CSTA = F8H:total serial transfer can commence.This status code indicates that no relevant information is availablebecause the serial interrupt flag, SI, is not yet set. This occurs on a•FORCED ACCESS TO THE I2C BUSSTOP condition and when SIO is not involved in a serial transfer.In some applications, it may be possible for an uncontrolled sourceto cause a bus hang-up. In such situations, the problem may beI2CSTA = 00H:caused by interference, temporary interruption of the bus or aThis status code indicates that a bus error has occurred during antemporary short-circuit between SDA and SCL.SIO serial transfer. A bus error is caused when a START or STOPcondition occurs at an illegal position in the format frame. ExamplesIf an uncontrolled source generates a superfluous START or masksof such illegal positions are during the serial transfer of an addressa STOP condition, then the I2C-bus stays busy indefinitely. If thebyte, a data byte, or an acknowledge bit. A bus error may also beSTA flag is set and bus access is not obtained within a reasonablecaused when external interference disturbs the internal SIO signals.amount of time, then a forced access to the I2C-bus is possible. IfWhen a bus error occurs, SI is set. To recover from a bus error, thethe I2C-bus stays idle for a time period equal to the time out period,microcontroller must send an external reset signal to reset the SIO.then the ’64 concludes that no other master is using the bus andsends a START condition.I2CSTA = 70H:This status code indicates that the SDA line is stuck LOW when theSIO, in master mode, is trying to send a START condition.SSLAWADATAASBOTH MASTERS CONTINUEWITH SLA TRANSMISSION08H18H28HOTHER MASTER SENDS REPEATEDSTART CONDITION EARLIERSU00975Figure 6. Simultaneous repeated START conditions from 2 masters2006 Sep 01 15Philips SemiconductorsProduct data sheetParallel bus to I2C-bus controllerPCA9564TIME OUTSTA FLAGSDA LINESCL LINESTART CONDITIONSU00976Figure 7. Forced access to a busy I2C-bus•I2C BUS OBSTRUCTED BY A LOW LEVEL ON SCL OR SDAmicrocontroller reads the status register, it needs to send anAn I2C-bus hang-up occurs if SDA or SCL is pulled LOW by anexternal reset signal in order to reset the SIO.uncontrolled source. If the SCL line is obstructed (pulled LOW) by aIf a forced bus access occurs or a repeated START condition isdevice on the bus, no further serial transfer is possible, and the SIOtransmitted while SDA is obstructed (pulled LOW), the SIOhardware cannot resolve this type of problem. When this occurs, thehardware performs the same action as described above. In eachproblem must be resolved by the device that is pulling the SCL buscase, state 08H is entered after a successful START condition isline LOW.transmitted and normal serial transfer continues. Note that the CPUWhen the SCL line stays LOW for a period equal to the time-outis not involved in solving these bus hang-up problems.value, the ’64 concludes that this is a bus error and behaves in a•BUS ERRORmanner described on page 5 under “Time-out Register”.A bus error occurs when a START or STOP condition is present atIf the SDA line is obstructed by another device on the bus (e.g., aan illegal position in the format frame. Examples of illegal positionsslave device out of bit synchronization), the problem can be solvedare during the serial transfer of an address byte, a data or anby transmitting additional clock pulses on the SCL line (seeacknowledge bit.Figure 8). The SIO hardware sends out nine clock pulses followedThe SIO hardware only reacts to a bus error when it is involved in aby the STOP condition. If the SDA line is released by the slaveserial transfer either as a master or an addressed slave. When apulling it LOW, a normal START condition is transmitted by the SIO,bus error is detected, SIO releases the SDA and SCL lines, sets thestate 08H is entered and the serial transfer continues. If the SDAinterrupt flag, and loads the status register with 00H. This statusline is not released by the slave pulling it LOW, then the SIOcode may be used to vector to a service routine which eitherconcludes that there is a bus error, loads 70H in I2CSTA, generatesattempts the aborted serial transfer again or simply recovers froman interrupt signal, and releases the SCL and SDA lines. After thethe error condition as shown in Table 6. The microcontroller mustsend an external reset signal to reset the SIO.STA FLAGSDA LINE123456789SCL LINESTOPSTARTCONDITIONCONDITIONsu01663Figure 8. Recovering from a bus obstruction caused by a LOW level on SDA2006 Sep 01 16Philips SemiconductorsProduct data sheetParallel bus to I2C-bus controllerPCA9564I2C-BUS TIMING DIAGRAMSThe diagrams (Figures 9 to 12) illustrate typical timing diagrams for the PCA9564 in master/slave functions.SCLSDAINT7-bit addressinterruptfirst-byteinterruptnbyteinterruptR/W = 0STARTACKACKACKSTOPconditionconditionfrom slave receiverMaster PCA9564 writes data to slave transmitter.su01490Figure 9. Bus timing diagram; master transmitter modeSCLSDAINT7-bit addressinterruptfirst-byteinterruptnbyteSTARTR/W = 1ACKACKno ACKSTOPconditionconditionfrom slavefrom masterreceiverMaster PCA9564 reads data from slave transmitter.su01491Figure 10. Bus timing diagram; master receiver mode2006 Sep 01 17Philips SemiconductorsProduct data sheetParallel bus to I2C-bus controllerPCA9564SCLSDAINT7-bit addressinterruptfirst-byteinterruptnbyteinterruptSTARTR/W = 1ACKACKno ACKSTOPconditionconditionfrom slave PCA9564from masterreceiverExternal master receiver reads data from PCA9564.su01492Figure 11. Bus timing diagram; slave transmitter modeSCLSDAINT7-bit addressinterruptfirst-byteinterruptnbyteinterruptinterrupt(after STOP)STARTR/W = 0ACKACKACKSTOPconditionconditionfrom slave PCA9564Slave PCA9564 is written to by external master transmitter.su01493Figure 12. Bus timing diagram; slave receiver mode2006 Sep 01 18Philips SemiconductorsProduct data sheetParallel bus to I2C-bus controllerPCA9564VDDADDRESS BUSVDDVDDA0A1DECODERPCA9564SLAVEINTRESETALECE80C51SCL8D[0:7]RDWRSDAVDDINTRESETVDDVSSVSSSD00705Figure 13. Application diagram using the 80C512006 Sep 01 19Philips SemiconductorsProduct data sheetParallel bus to I2C-bus controllerPCA9564SPECIFIC APPLICATIONSPCA8584 MIGRATION PATHThe PCA9564 is a parallel bus to I2C bus controller that is designedThe PCA9564 does the same type of parallel to serial conversion asto allow “smart” devices to interface with I2C or SMBus components,the PCF8584. Although not footprint or code compatible, thewhere the “smart” device does not have an integrated I2C port andPCA9564 provides improvements such as:the designer does not want to “bit-bang” the I2C port. The PCA9564can also be used to add more I2C ports to “smart” devices, provide a1.Operating at 3.3 V and 2.5 V voltage nodes with 5 V tolerant I/Oshigher frequency, lower voltage migration path for the PCF8584 and2.Allows interface with I2C or SMBus components at speeds up toconvert 8 bits of parallel data to a serial bus to avoid running400 kHz.multiple traces across the PC board.3.Built-in oscillator provides a cost effective solution since theexternal clock input is no longer required.ADD I2C-BUS PORT4.Parallel data can be exchanged at speeds up to 50 MHz allowingAs shown in Figure 14, the PCA9564 converts 8-bits of parallel datathe use of faster processors.into a multiple master capable I2C port for microcontrollers,microprocessors, custom ASICs, DSPs, etc., that need to interfacewith I2C or SMBus components.SUPPLY VOLTAGE FREQUENCYPCA9564SDASCL2.3 – 3.6 V< 400 kHzOSCILLATORCONTROL SIGNALSMICROCONTROLLER,SDAMICROPROCESSOR,PCA9564OR ASICSCL4.5 – 5.5 V< 100 kHz8-BITSPCF8584SDASCLSW02108Figure 14. Adding I2C-bus Port ApplicationCLOCK INPUTSW02110Figure 16. PCF8584 Migration PathADD ADDITIONAL I2C-BUS PORTSThe PCA9564 can be used to convert 8-bit parallel data intoadditional multiple master capable I2C port as shown in Figure 15. Itis used if the microcontroller, microprocessor, custom ASIC, DSP,CONVERT 8 BITS OF PARALLEL DATA INTOetc., already have an I2C port but need one or more additional I2CI2C-BUS SERIAL DATA STREAMports to interface with more I2C or SMBus components orFunctioning as a slave transmitter, the PCA9564 can convert 8-bitcomponents that cannot be located on the same bus (e.g., 100 kHzparallel data into a two-wire I2C data stream as is shown inand 400 kHz slaves on different buses so that each bus can operateFigure 17. This would prevent having to run 8 traces across theat its maximum potential).entire width of the PC board.SDACONTROLSCLSIGNALSSDAMICROCONTROLLER,MICROPROCESSOR,PCA9564MASTERMICROCONTROLLER,OR ASICSCLMICROPROCESSOR,8-BITSOR ASICCONTROL SIGNALSSDAPCA9564SCLSW021118-BITSFigure 17. Converting Parallel to Serial Data ApplicationSW02109Figure 15. Adding Additional I2C-bus Ports Application2006 Sep 01 20Philips SemiconductorsProduct data sheetParallel bus to I2C-bus controllerPCA9564ABSOLUTE MAXIMUM RATINGSIn accordance with the Absolute Maximum Rating System (IEC 134)SYMBOLPARAMETERCONDITIONSMINMAXUNITVDDSupply voltage–0.34.6VVIVoltage range (any input)–0.86.01VIIDC input current (any input)–1010mAIODC output current (any output)–1010mAPtotTotal power dissipation—300mWPOPower dissipation per output—50mWTambOperating ambient temperature–40+85°CTstgStorage temperature–65+150°CNOTE:1.5.5 V steady state voltage tolerance on inputs and outputs is valid only when the supply voltage is present. 4.6 V steady state voltagetolerance on inputs and outputs when no supply voltage is present.HANDLINGInputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to takeprecautions appropriate to handling MOS devices. Advice can be found in Data Handbook IC24 under ”Handling MOS devices”.DC CHARACTERISTICSVDD = 2.3 V to 3.6 V; Tamb = –40 to +85 °C; unless otherwise specified.SYMBOLPARAMETERCONDITIONSMINTYPMAXUNITSuppliesVDDSupply voltage2.3—3.6VIstandby—0.13.0µADDSupplySuly currentcurrentoperating – no load——6.0mAVPORPower-on Reset voltage—1.82.2VInputs WR, RD, A0, A1, CE, RESETVILLOW-level input voltage0—0.8VVIHHIGH-level input voltage2.0—5.51VILLeakage currentInput; VI = 0 V or 5.5 V–1—1µACIInput capacitanceVI = VSS or VDD—1.73pFInputs/outputs D0 to D7VILLOW-level input voltage0—0.8VVIHHIGH-level input voltage2.0—5.51VIOHHIGH-level output currentVOH = VDD – 0.4 V–4.0–7.0—mAIOLLOW-level output currentVOL = 0.4 V4.08.0—mAILLeakage currentInput; VI = 0 V or 5.5 V–1—1µACIOInput/output capacitanceVI = VSS or VDD—2.44pFSDA and SCLVILLOW-level input voltage0—0.3 VDDVVIHHIGH-level input voltage0.7 VDD—5.51VILLeakageLeakage currentcurrentInput/output; VI = 0 V or 3.6 V–1—1Input/output; VI = 5.5 V–1—10µAIOLLOW-level output currentVOL = 0.4 V5.08.5—mACIOInput/output capacitanceVI = VSS or VDD—2.54pFOutputs INTIOLLOW-level output currentVOL = 0.4 V3.0——mAILLeakage currentVO = 0 or 3.6 V–1—1µACOOutput capacitanceVI = VSS or VDD—2.14pFNOTE:1.5.5 V steady state voltage tolerance on inputs and outputs is valid only when the supply voltage is present. 4.6 V steady state voltagetolerance on inputs and outputs when no supply voltage is present.2006 Sep 01 21Philips SemiconductorsProduct data sheetParallel bus to I2C-bus controllerPCA9564SDAttLOWFtRtSU;DATtFtHD;STAtSPtRtBUFSCLttSU;STASHD;STAtHD;DATtHIGHStSU;STORPSSU01755Figure 18. Definition of timingI2C-BUS TIMING SPECIFICATIONSAll the timing limits are valid within the operating supply voltage and ambient temperature range; VDD = 2.5 V ± 0.2 V and 3.3 V ± 0.3 V, Tamb = –40 to +85 °C; and refer to VIL and VIH with an input voltage of VSS to VDD.STANDARD-MODEFAST-MODESYMBOLPARAMETERI2C-BUSI2C-BUSUNITSMINMAXMINMAXfSCLOperating frequency01000400kHztBUFBus free time between STOP and START conditions4.7—1.3—µstHD;STAHold time after (repeated) START condition4.0—0.6—µstSU;STARepeated START condition setup time4.7—0.6—µstSU;STOSetup time for STOP condition4.0—0.6—µstHD;DATData in hold time0—0—nstVD;ACKValid time for ACK condition—0.6—0.6µstVD;DAT(L)Data out valid time LOW—0.6—0.6µstVD;DAT(H)Data out valid time HIGH—0.6—0.6µstSU;DATData setup time250—100—nstLOWClock LOW period4.7—1.3—µstHIGHClock HIGH period4.0—0.6—µstFClock/Data fall time—0.3—0.3µstRClock/Data rise time—1—0.3µstSPPulse width of spikes that must be suppressed by the input filters—50—50ns2006 Sep 01 22Philips SemiconductorsProduct data sheetParallel bus to I2C-bus controllerPCA9564STARTSCLACK OR READ CYCLESDA30%tRESRESET50%50%50%tRECtWREStRESDn50%LED OFFSW02107Figure 19. Reset timingA0–A1tAStAHCEtCStCHtRWtRWDRDtDDtDFD0–D7FLOATNOT(READ)VALIDVALIDFLOATtRWDWRtDStDHD0–D7(WRITE)VALIDSD00711Figure 20. Bus timing2006 Sep 01 23Philips SemiconductorsProduct data sheetParallel bus to I2C-bus controllerPCA9564AC CHARACTERISTICS (3.3 VOLT) 1, 2, 3VCC = 3.3 V ± 0.3 V, Tamb = –40 °C to +85 °C, unless otherwise specified. (See page 25 for 2.5 V.)LIMITSSYMBOLPARAMETERMinMaxUNITReset Timing (See Figure 19)tWRESReset pulse width10—nstRES4,5Time to reset250—nstRECReset recovery time0—nsBus Timing (See Figure 20, 21)tASA0–A1 setup time to RD, WR LOW0—nstAHA0–A1 hold time from RD, WR LOW7—nstCSCE setup time to RD, WR LOW0—nstCHCE Hold time from RD, WR LOW0—nstRWWR, RD pulse width (Low time)7—nstData valid after RD and CE LOWnsDD—17tDFData bus floating after RD or CE HIGH—17nstDSData bus setup time before WR or CE HIGH (write cycle)7—nstDHData hold time after WR HIGH0—nstHigh time between read and/or write cycles12—RWDnsNOTES:1.Parameters are valid over specified temperature and voltage range.2.All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0 V and 3.0 V with a transition time of 5 nsmaximum. All time measurements are referenced at input voltages of 1.5 V and output voltages shown in Figures 20–21.3.Test conditions for outputs: CL = 50 pF, RL = 500 Ω, except open drain outputs. Test conditions for open drain outputs: CL = 50 pF, RL = 1 kΩpullup to VResetting the device while actively communicating on the bus may cause glitches or an errant STOP condition.DD.4.5.Upon reset, the full delay will be the sum of tRES and the RC time constant of the SDA and SCL bus.2006 Sep 01 24Philips SemiconductorsProduct data sheetParallel bus to I2C-bus controllerPCA9564AC CHARACTERISTICS (2.5 VOLT) 1, 2, 3VCC = 2.5 V ± 0.2 V, Tamb = –40 to +85 °C, unless otherwise specified. (See page 24 for 3.3 V.)LIMITSSYMBOLPARAMETERMinMaxUNITReset Timing (See Figure 19)tWRESReset pulse width10—nstRES4,5Time to reset250—nstRECReset recovery time0—nsBus Timing (See Figure 20, 21)tASA0–A1 setup time to RD, WR LOW0—nstAHA0–A hold time from RD, WR LOW9—nstCSCE setup time to RD, WR LOW0—nstCHCE Hold time from RD, WR LOW0—nstRWWR, RD pulse width (low time)9—nstData valid after RD and CE LOWnsDD—22tDFData bus floating after RD or CE HIGH—17nstDSData bus setup time before WR or CE HIGH (write cycle)8—nstDHData hold time after WR HIGH0—nstHigh time between read and/or write cycles12—RWDnsNOTES:1.Parameters are valid over specified temperature and voltage range.2.All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0 V and 3.0 V with a transition time of 5 nsmaximum. All time measurements are referenced at input voltages of 1.5 V and output voltages shown in Figures 20–21.3.Test conditions for outputs: CL = 50 pF, RL = 500 Ω, except open drain outputs. Test conditions for open drain outputs: CL = 50 pF, RL = 1 kΩpullup to VResetting the device while actively communicating on the bus may cause glitches or an errant STOP condition.DD.4.5.Upon reset, the full delay will be the sum of tRES and the RC time constant of the SDA and SCL bus.2006 Sep 01 25Philips SemiconductorsProduct data sheetParallel bus to I2C-bus controllerPCA9564RD, CE INPUTVI VMVMGNDtDF(LZ)tDD(ZL)Dn OUTPUTVCCLOW-TO-FLOATFLOAT-TO-LOWVM VOLVXtDF(HZ)tDD(ZH)Dn OUTPUTVOHVYHIGH-TO-FLOATFLOAT-TO-HIGHVM GNDOUTPUTS ENABLEDOUTPUTSFLOATINGOUTPUTS ENABLEDVM = 1.5 VVX = VOL + 0.3 VVY = VOH – 0.3 VVOL AND VOH ARE TYPICAL OUTPUT VOLTAGE DROPS THAT OCCUR WITH THE OUTPUT LOAD.SW02113Figure 21. tDD and tDF timesVCC6.0 VOpenVPULSEIVORL = 500 ΩGENERATORD.U.T.RTCLRL = 500 Ω50 pFTESTS1DEFINITIONStPLZ/tPZL6 VRL =Load resistor.tPLH/tPHLOpenCL =Load capacitance includes jig and probe capacitanceRT =Termination resistance should be equal to the outputimpedance ZO of the pulse generators.SW02114Figure 22. Test circuitry for switching times2006 Sep 01 26Philips SemiconductorsProduct data sheet
Parallel bus to I2C-bus controller
PCA9564
DIP20:plastic dual in-line package; 20 leads (300 mil)SOT146-1
2006 Sep 01 27
Philips SemiconductorsProduct data sheet
Parallel bus to I2C-bus controller
PCA9564
SO20:plastic small outline package; 20 leads; body width 7.5 mmSOT163-1
2006 Sep 01 28
Philips SemiconductorsProduct data sheet
Parallel bus to I2C-bus controller
PCA9564
TSSOP20:plastic thin shrink small outline package; 20 leads; body width 4.4 mmSOT360-1
2006 Sep 01 29
Philips SemiconductorsProduct data sheet
Parallel bus to I2C-bus controller
PCA9564
HVQFN20:plastic thermal enhanced very thin quad flat package; no leads; 20 terminals; body 5 x 5 x 0.85 mm
SOT662-1
2006 Sep 01 30
Philips SemiconductorsProduct data sheetParallel bus to I2C-bus controllerPCA9564REVISION HISTORYRevDateDescription_420060901Product data sheet. Supersedes data of 2004 Jun 25 (9397 750 13272).•Ordering information table on page 2: added whole wafer package option (PCA9564U).•Pin description table on page 3: added table note 1 and its reference at HVQFN pin 7 (VSS).•Section “The Control Register, I2CCON” on page 5: 3rd sentence re-written._320040625Product data sheet (9397 750 13272). Supersedes data of 2003 Apr 02 (9397 750 11353)._220030402Product data (9397 750 11353). ECN 853-2419 29715 Dated 24 March 2003. Supersedes Objective data of 2003 Feb 26 (9397 750 11153)._120030226Objective data (9397 750 11153).2006 Sep 01 31Philips SemiconductorsProduct data sheetParallel bus to I2C-bus controllerPCA9564Legal InformationData sheet statusDocument status[1][2]Product status[3]DefinitionObjective [short] data sheetDevelopmentThis document contains data from the objective specification for product development.Preliminary [short] data sheetQualificationThis document contains data from the preliminary specification.Product [short] data sheetProductionThis document contains the product specification.[1]Please consult the most recently issued document before initiating or completing a design.[2]The term ‘short data sheet’ is explained in section “Definitions”.[3]The product status of device(s) described in this document may have changed since this data sheet was published and may differ in case of multiple devices. The latest product statusinformation is available on the Internet at URL http://www.semiconductors.philips.com.Definitionsinclusion and/or use of Philips Semiconductors products in such equipmentDraft — The document is a draft version only. The content is still underor applications and therefore such inclusion and/or use is at the customer’sinternal review and subject to formal approval, which may result inown risk.modifications or additions. Philips Semiconductors does not give anyApplications — Applications that are described herein for any of theserepresentations or warranties as to the accuracy or completeness ofproducts are for illustrative purposes only. Philips Semiconductors makes noinformation included herein and shall have no liability for the consequencesrepresentation or warranty that such applications will be suitable for theof use of such information.specified use without further testing or modification.Short data sheet — A short data sheet is an extract from a full data sheetLimiting values — Stress above one or more limiting values (as defined inwith the same product type number(s) and title. A short data sheet isthe Absolute Maximum Ratings System of IEC 60134) may causeintended for quick reference only and should not be relied upon to containpermanent damage to the device. Limiting values are stress ratings only anddetailed and full information. For detailed and full information see theoperation of the device at these or any other conditions above those given inrelevant full data sheet, which is available on request via the local Philipsthe Characteristics sections of this document is not implied. Exposure toSemiconductors sales office. In case of any inconsistency or conflict with thelimiting values for extended periods may affect device reliability.short data sheet, the full data sheet shall prevail.Terms and conditions of sale — Philips Semiconductors products areDisclaimerssold subject to the general terms and conditions of commercial sale, asGeneral — Information in this document is believed to be accurate andpublished at http://www.semiconductors.philips.com/profile/terms,reliable. However, Philips Semiconductors does not give any representationsincluding those pertaining to warranty, intellectual property rightsor warranties, expressed or implied, as to the accuracy or completeness ofinfringement and limitation of liability, unless explicitly otherwise agreed to insuch information and shall have no liability for the consequences of use ofwriting by Philips Semiconductors. In case of any inconsistency or conflictsuch information.between information in this document and such terms and conditions, thelatter will prevail.Right to make changes — Philips Semiconductors reserves the right tomake changes to information published in this document, including withoutNo offer to sell or license — Nothing in this document may be interpretedlimitation specifications and product descriptions, at any time and withoutor construed as an offer to sell products that is open for acceptance or thenotice. This document supersedes and replaces all information supplied priorgrant, conveyance or implication of any license under any copyrights,to the publication hereof.patents or other industrial or intellectual property rights.Suitability for use — Philips Semiconductors products are not designed,Trademarksauthorized or warranted to be suitable for use in medical, military, aircraft,space or life support equipment, nor in applications where failure orNotice: All referenced brands, product names, service names andmalfunction of a Philips Semiconductors product can reasonably betrademarks are the property of their respective owners.expected to result in personal injury, death or severe property orI2C-bus — logo is a trademark of Koninklijke Philips Electronics N.V.environmental damage. Philips Semiconductors accepts no liability forContact informationFor additional information please visit: http://www.semiconductors.philips.comFor sales office addresses, send an e-mail to: sales.addresses@www.semiconductors.philips.com.Please be aware that important notices concerning this document and the product(s)described herein, have been included in section ‘Legal information’.© Koninklijke Philips Electronics N.V.2006.All rights reserved.For more information, please visit http://www.semiconductors.philips.com.For sales office addresses, email to: sales.addresses@www.semiconductors.philips.com.Date of release: 20060901Document identifier: PCA9564_4yyyy mmm dd32