XQR17V16VQ44N资料

DS126 (v1.0) December 18, 2003

0Product Specification•••••••••

Simple interface to Xilinx QPro FPGAs

Cascadable for storing longer or multiple bitstreamsProgrammable reset polarity (active High or active Low) for compatibility with different FPGA solutions Low-power CMOS Floating Gate process3.3V supply voltage

Available in compact plastic VQ44 and ceramic CC44 packages

Programming support by leading programmer manufacturers.

Design support using the Xilinx Alliance and Foundation series software packages.Guaranteed 20 year life data retention

Features

••••••

Latch-Up Immune to LET >120 MeV/cm2/mgGuaranteed TID of 50 kRad(Si) per spec 1019.5Fabricated on Epitaxial Substrate16Mbit storage capacity

Guaranteed operation over full military temperature range: –55°C to +125°C

One-time programmable (OTP) read-only memory designed to store configuration bitstreams of Xilinx FPGA devices

Dual configuration modes--Serial configuration (up to 33Mb/s)Parallel (up to 2Mb/s at 33MHz)

•

Description

Xilinx introduces the high-density QPro™ XQR17V16series Radiation Hardened QML configuration PROM whichprovide an easy-to-use, cost-effective method for storinglarge Xilinx FPGA configuration bitstreams. The XQR17V16is a 3.3V device with a storage capacity of 16Mb and canoperate in either a serial or byte wide mode. See Figure1for a simplified block diagram of the XQR17V16 devicearchitecture.

When the FPGA is in Master Serial mode, it generates aconfiguration clock that drives the PROM. A short accesstime after the rising clock edge, data appears on the PROMDATA output pin that is connected to the FPGA DIN pin. TheFPGA generates the appropriate number of clock pulses tocomplete the configuration. Once configured, it disables thePROM. When the FPGA is in Slave Serial mode, the PROMand the FPGA must both be clocked by an incoming signal.

When the FPGA is in Master SelectMAP mode, it generatesa configuration clock that drives the PROM and the FPGA.After the rising CCLK edge, data are available on thePROMs DATA (D0-D7) pins. The data will be clocked intothe FPGA on the following rising edge of the CCLK. Whenthe FPGA is in Slave SelectMAP mode, the PROM and theFPGA must both be clocked by an incoming signal. Afree-running oscillator may be used to drive CCLK. SeeFigure2.

Multiple devices can be concatenated by using the CEOoutput to drive the CE input of the following device. Theclock inputs and the DATA outputs of all PROMs in thischain are interconnected. All devices are compatible andcan be cascaded with other members of the family.For device programming, either the Xilinx Alliance or Foun-dation series development system compiles the FPGAdesign file into a standard Hex format, which is then trans-ferred to most commercial PROM programmers.

© 2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

QPro XQR17V16 Radiation Hardened 16Mbit QML Configuration PROMVCCVPPGNDRESET/OEorOE/RESETCECEOCLKBUSYAddress CounterTCEPROMCellMatrixOutput87OED0 Data(Serial or Parallel Mode)7D[1:7] (SelectMAP Interface)DS073_02_072600Figure 1: Simplified Block Diagram for XQR17V16 (does not show programming circuit)

Pin Description

DATA[0:7]

Data output is in a high-impedance state when either CE orOE are inactive. During programming, the D0 pin is I/O.Note that OE can be programmed to be either active High oractive Low.

option is active Low RESET, because it can connected tothe FPGAs INIT pin and a pullup resistor.

The polarity of this pin is controlled in the programmer inter-face. This input pin is easily inverted using the XilinxHW-130 Programmer. Third-party programmers have differ-ent methods to invert this pin.

CE

When High, this pin disables the internal address counter,puts the DATA output in a high-impedance state, and forcesthe device into low-ICC standby mode.

CLK

Each rising edge on the CLK input increments the internaladdress counter, if both CE and OE are active.

RESET/OE

When High, this input holds the address counter reset andputs the DATA output in a high-impedance state. The polar-ity of this input pin is programmable as either RESET/OE orOE/RESET. To avoid confusion, this document describesthe pin as RESET/OE, although the opposite polarity is pos-sible on all devices. When RESET is active, the addresscounter is held at “0”, and puts the DATA output in ahigh-impedance state. The polarity of this input is program-mable. The default is active High RESET, but the preferred

CEO

Chip Enable output, to be connected to the CE input of thenext PROM in the daisy chain. This output is Low when theCE and OE inputs are both active AND the internal addresscounter has been incremented beyond its Terminal Count(TC) value. In other words: when the PROM has been read,CEO will follow CE as long as OE is active. When OE goesinactive, CEO stays High until the PROM is reset. Note thatOE can be programmed to be either active High or activeLow.

QPro XQR17V16 Radiation Hardened 16Mbit QML Configuration PROMBUSY (XQR17V16 only)

If BUSY pin is floating, the user must program the BUSY bit which will cause BUSY pin to be internally tied to a

pull-down resistor. When asserted High, output data are held and when BUSY pin goes Low, data output will resume.

VPP

Programming voltage. No overshoot above the specifiedmax voltage is permitted on this pin. For normal read oper-ation, this pin must be connected to VCC. Failure to do somay lead to unpredictable, temperature-dependent opera-tion and severe problems in circuit debugging. Do not leaveVPP floating!

VCC and GND

Positive supply and ground pins.

PROM Pinouts for XQR17V16

(Pins not listed are “no connect”)

Pin Name44-pin VQFP

44-pin CLCC

BUSY2430D0402D12935D2424D32733D4915D52531D61420D71925CLK435RESET/OE1319(OE/RESET)CE15

21

GND6, 18, 28, 37, 41

3, 12, 24, 34, 43

CEO2127VPP35

41VCC

8, 16, 17, 26, 36,

14, 22, 23, 32,

38

42, 44

Capacity

DeviceConfiguration Bits

XQR17V16

16,777,216

Xilinx FPGAs and Compatible PROMs

DeviceConfiguration Bits

XQR17V16(s)

XQR2V10004,082,6561XQR2V300010,494,4321XQR2V600021,849, 5682XQVR3001,751,8081XQVR6003,607,9681XQVR1000

6,127,744

1

Controlling PROMs

Connecting the FPGA device with the PROM. •The DATA output(s) of the PROM(s) drives the DIN input of the lead FPGA device.

•The Master FPGA CCLK output drives the CLK input(s) of the PROM(s).

•The CEO output of a PROM drives the CE input of the next PROM in a daisy chain (if any).

•

The RESET/OE input of all PROMs is best driven by the INIT output of the lead FPGA device. This

connection assures that the PROM address counter is reset before the start of any (re)configuration, even when a reconfiguration is initiated by a VCC glitch. •

The PROM CE input is best connected to the FPGA DONE pin(s) and a pullup resistor. CE can also be permanently tied Low, but this keeps the DATA output active and causes an unnecessary supply current of 15mA maximum.

•

SelectMAP mode is similar to Slave Serial mode. The DATA is clocked out of the PROM one byte per CCLK instead of one bit per CCLK cycle. See FPGA data sheets for special configuration requirements.

FPGA Master Serial Mode Summary

The I/O and logic functions of the Configurable Logic Block(CLB) and their associated interconnections are estab-lished by a configuration program. The program is loadedeither automatically upon power up, or on command,depending on the state of the three FPGA mode pins. InMaster Serial mode, the FPGA automatically loads the con-figuration program from an external memory. The XilinxPROMs have been designed for compatibility with the Mas-ter Serial mode.

Upon power-up or reconfiguration, an FPGA enters theMaster Serial mode whenever all three of the FPGA

QPro XQR17V16 Radiation Hardened 16Mbit QML Configuration PROMmode-select pins are Low (M0=0, M1=0, M2=0). Data isread from the PROM sequentially on a single data line. Syn-chronization is provided by the rising edge of the temporarysignal CCLK, which is generated during configuration.Master Serial Mode provides a simple configuration inter-face. Only a serial data line, two control lines, and a clockline are required to configure an FPGA. Data from thePROM is read sequentially, accessed via the internaladdress and bit counters which are incremented on everyvalid rising edge of CCLK.

If the user-programmable, dual-function DIN pin on theFPGA is used only for configuration, it must still be held at adefined level during normal operation. The Xilinx FPGAfamilies take care of this automatically with an on-chipdefault pull-up/down resistor or keeper circuit.

Cascading Configuration PROMs

For multiple FPGAs configured as a daisy-chain, or forfuture FPGAs requiring larger configuration memories, cas-caded PROMs provide additional memory. After the last bitfrom the first PROM is read, the next clock signal to thePROM asserts its CEO output Low and disables its DATAline. The second PROM recognizes the Low level on its CEinput and enables its DATA output. See Figure2.

After configuration is complete, the address counters of allcascaded PROMs are reset if the FPGA PROGRAM pingoes Low, assuming the PROM reset polarity option hasbeen inverted.

QPro XQR17V16 Radiation Hardened 16Mbit QML Configuration PROMDOUTVCCFPGAModes(1)4.7KVCC4.7KVCC(2)OPTIONALDaisy-chainedFPGAs withdifferentconfigurationsOPTIONALSlave FPGAswith identicalconfigurationsVCCVCCDINCCLKDONEINITPROGRAM(Low Resets the Address Pointer)VCCDATACLKCEVppBUSYCEOVCCBUSYDATACLKCEVppFirstPROMOE/RESETCascadedPROMOE/RESET(1) For Mode pin connections, refer to the appropriate FPGA data sheet.(2) Virtex, Virtex-E is 300 ohms, all others are 4.7K.Master Serial ModeModes(3)CSWRITE1KI/O(1)I/O(1)1KVCC(2)ExternalOsc(4)VCCVCCVIRTEXSelectMAPBUSYCCLKPROGRAMD[0:7]DONEINIT3.3V4.7KVCCVppBUSYVCCVppFirstCLKPROM8D[0:7]CEOE/RESETCEOBUSYSecondCLKPROMCEOD[0:7]CEOE/RESET(1) CS and WRITE must be pulled down to be used as I/O. One option is shown.(2) Virtex, Virtex-E is 300 ohms, all others are 4.7K.(3) For Mode pin connections, refer to the appropriate FPGA data sheet.(4) External oscillator required for Virtex/E SelectMAP or Virtex-II slave SelectMAP modes.Virtex SelectMAP Mode, XQ17V16 only.DS073_03_062602Figure 2: (a) Master Serial Mode (b) Virtex SelectMAP Mode

(dotted lines indicates optional connection)

QPro XQR17V16 Radiation Hardened 16Mbit QML Configuration PROMStandby Mode

The PROM enters a low-power standby mode wheneverCE is asserted High. The output remains in a high imped-ance state regardless of the state of the OE input.

Programming

The devices can be programmed on programmers suppliedby Xilinx or qualified third-party vendors. The user mustensure that the appropriate programming algorithm and thelatest version of the programmer software are used. Thewrong choice can permanently damage the device.

Table 1: Truth Table for XQ17V00 Control Inputs

Control InputsRESETInactiveActiveInactiveActive

CELowLowHighHigh

Internal Address

If address < TC(1): increment If address > TC(1): don’t change

Held resetNot changingHeld reset

DATAActiveHigh-ZHigh-ZHigh-ZHigh-Z

OutputsCEOHighLowHighHighHigh

ICCActiveReducedActiveStandbyStandby

Notes:

1.The XQ17V00 RESET input has programmable polarity

1.TC = Terminal Count = highest address value. TC + 1 = address 0.

Radiation Tolerances

Table 2: Guaranteed Radiation Tolerance Specifications(1)

SymbolTIDSELSEU

Description

Total Ionizing Dose for data retention and data output port read (configuration) operationsSingle Event Latch-Up

(No Latch-Up observed for LET > 120 MeV-mg/cm2)Static Memory Cell Saturation Bit Cross-Section(No Upset observed for LET > 120 MeV-mg/cm2)

Notes:

1.For more information on dynamic SEU error rates please see the SEU test reports at http://www.xilinx.com/milaero

Min---

Max5000

Unitskrad(Si)cm2cm2

QPro XQR17V16 Radiation Hardened 16Mbit QML Configuration PROMAbsolute Maximum Ratings

SymbolVCCVPPVINVTSTSTGTSOLTJ

Description

Supply voltage relative to GNDSupply voltage relative to GNDInput voltage relative to GNDVoltage applied to High-Z outputStorage temperature (ambient)

Maximum soldering temperature (10s @ 1/16 in.)Junction temperature

CeramicPlastic

Conditions–0.5 to +7.0–0.5 to +12.5–0.5 to VCC +0.5–0.5 to VCC +0.5–65 to +150

+260+150+125

UnitsVVVV°C°C°C°C

Notes:

1.Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress

ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.

Operating Conditions (3.3V Supply)

SymbolVCC(1)TVCC

Description

Supply voltage relative to GND (TC = –55°C to +125°C)Supply voltage relative to GND (TJ = –55°C to +125°C)VCC rise time from 0V to nominal voltage

CeramicPlastic

Min3.03.01.0

Max3.63.650

UnitsVVms

Notes:

1.During normal read operation VPP must be connected to VCC.

2.At power up, the device requires the VCC power supply to monotonically rise from 0V to nominal voltage within the specified VCC rise

time. If the power supply cannot meet this requirement, then the device may not power-on-reset properly.

DC Characteristics Over Operating Condition

SymbolVIHVILVOHVOLICCAICCSILCINCOUT

High-level input voltageLow-level input voltage

High-level output voltage (IOH = –3 mA)Low-level output voltage (IOL = +3 mA)

Supply current, active mode (at maximum frequency) Supply current, standby modeInput or output leakage current

Input capacitance (VIN = GND, f = 1.0 MHz)Output capacitance (VIN = GND, f = 1.0 MHz)

Description

Min202.4---–10--MaxVCC0.8-0.41001101515

UnitsVVVVmAmAµApFpF

QPro XQR17V16 Radiation Hardened 16Mbit QML Configuration PROMAC Characteristics Over Operating Condition for XQR17V16

CETSCETSCETHCERESET/OETLCTHCTHOETCYCCLKTOETCETSBUSYTCACTOHTDFDATATHBUSYTOHBUSYDS073_05_072600SymbolTOETCETCACTDFTOHTCYCTLCTHCTSCETHCETHOETSBUSYTHBUSY

OE to data delayCE to data delayCLK to data delay(2)

DescriptionMin----05025252502555

Max15202035---------

Unitsnsnsnsnsnsnsnsnsnsnsnsnsns

CE or OE to data float delay(3,4)Data hold from CE, OE, or CLK(4)Clock periodsCLK Low time(4)CLK High time(4)

CE setup time to CLK (to guarantee proper counting)CE hold time to CLK (to guarantee proper counting)OE hold time (guarantees counters are reset)BUSY setup timeBUSY hold time

Notes:

1.AC test load = 50 pF.2.When BUSY = 0.

3.Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels.4.Guaranteed by design, not tested.

5.All AC parameters are measured with VIL = 0.0V and VIH = 3.0V.

QPro XQR17V16 Radiation Hardened 16Mbit QML Configuration PROMAC Characteristics Over Operating Condition When Cascading

OE/RESETCECLKTCDFTOCEFirst BitTOOEDATA Last BitTOCKCEODS026_07_020300SymbolTCDFTOCKTOCETOOE

Description

CLK to data float delay(2,3)CLK to CEO delay(3)CE to CEO delay(3)

RESET/OE to CEO delay(3)

Min----

Max50303530

Unitsnsnsnsns

Notes:

1.AC test load = 50 pF

2.Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady

state active levels.

3.Guaranteed by design, not tested.

4.All AC parameters are measured with VIL = 0.0V and VIH = 3.0V.

QPro XQR17V16 Radiation Hardened 16Mbit QML Configuration PROMOrdering Information

XQR17V16 CC44 VDevice Number

Package Type

Manufacturing Grade

Device Ordering Options

Device TypeXQR17V16

CC44VQ44

Package

44-pin Ceramic Chip Carrier Package44-pin Plastic Thin Quad Flat Package

Grade

Flow

M-GradeQPRO-PLUSClass N

QPRO+PLUS PEM

Temp

Military CeramicTC = –55°C to +125°C

Military PlasticTJ = –55°C to +125°C

MVNR

Valid Ordering Combinations

M GradeXQR17V16CC44M

V GradeXQR17V16CC44V

N GradeXQR17V16VQ44N

R GradeXQR17V16VQ44R

Revision History

The following table shows the revision history for this document.

Date12/15/03

Version1.0

Initial Xilinx release.

Revision