FPGA可编程逻辑器件芯片ADG409BRZ中文规格书

APPARENT POWER CALCULATION

Apparent power is defined as the amplitude of the vector sum of the active and reactive powers. Figure 75 shows what is typically referred to as the power triangle.

APPARENTPOWERFor a pure sinusoidal system, the two approaches should yield the same result. The apparent energy calculation in the ADE7758 uses the arithmetical approach. However, the line cycle energy accumulation mode in the ADE7758 enables energy accumula-tion between active and reactive energies over a synchronous period, thus the vectorial method can be easily implemented in the external MCU (see the Line Cycle Active Energy Accumulation Mode section).

Note that apparent power is always positive regardless of the direction of the active or reactive energy flows. The rms value of the current and voltage in each phase is multiplied to produce the apparent power of the corresponding phase.

The output from the multiplier is then low-pass filtered to obtain the average apparent power. The frequency response of the LPF in the apparent power signal path is identical to that of the LPF2 used in the average active power calculation (see Figure 66).

REACTIVE POWERApparent Power Gain Calibration

θACTIVE POWER04443-074Figure 75. Power Triangle

There are two ways to calculate apparent power: the arithmetical approach or the vectorial method. The arithmetical approach uses the product of the voltage rms value and current rms value to calculate apparent power. Equation 38 describes the arithmetical approach mathematically.

S = VRMS × IRMS

(38)

where S is the apparent power, and VRMS and IRMS are the rms voltage and current, respectively.

The vectorial method uses the square root of the sum of the active and reactive power, after the two are individually squared. Equation 39 shows the calculation used in the vectorial approach.

S=P2+Q2

Note that the average active power result from the LPF output in each phase can be scaled by ±50% by writing to the phase’s VAGAIN register (AVAG, BVAG, or CVAG). The VAGAIN registers are twos complement, signed registers and have a resolution of 0.024%/LSB. The function of the VAGAIN registers is expressed mathematically as

AverageApparentPower=

VAGAINRegister⎞⎛

LPF2Output×⎜1+⎟12

2⎝⎠

(40)

The output is scaled by –50% by writing 0x800 to the VAR gain

registers and increased by +50% by writing 0x7FF to them. These registers can be used to calibrate the apparent power (or energy) calculation in the ADE7758 for each phase.

Apparent Power Offset Calibration

where:

S is the apparent power. P is the active power. Q is the reactive power.

Each rms measurement includes an offset compensation register

(39) to calibrate and eliminate the dc component in the rms value

(see the Current RMS Calculation section and the Voltage Channel RMS Calculation section). The voltage and current rms values are then multiplied together in the apparent power signal processing. As no additional offsets are created in the multiplication of the rms values, there is no specific offset

compensation in the apparent power signal processing. The offset compensation of the apparent power measurement in each phase should be done by calibrating each individual rms measurement (see the Calibration section).

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ADE7758

Apparent Energy Calculation

Apparent energy is defined as the integral of apparent power.

Apparent Energy = ∫ S(t)dt

(41)

Similar to active and reactive energy, the ADE7758 achieves the integration of the apparent power signal by continuously

accumulating the apparent power signal in the internal 41-bit, unsigned accumulation registers. The VA-hr registers (AVAHR, BVAHR, and CVAHR) represent the upper 16 bits of these internal registers. This discrete time accumulation or

summation is equivalent to integration in continuous time. Equation 42 expresses the relationship

⎧∞⎫

ApparentEnergy=∫S(t)dt=Lim⎨∑S(nT)×T⎬

T→0

⎩n=0⎭where:

n is the discrete time sample number.

T is the sample period.

Figure 76 shows the signal path of the apparent energy accumu-lation. The apparent power signal is continuously added to the internal apparent energy register. The average apparent power is divided by the content of the VA divider register before it is added to the corresponding VA-hr accumulation register. When the value in the VADIV[7:0] register is 0 or 1, apparent power is accumulated without any division. VADIV is an 8-bit unsigned register that is useful to lengthen the time it takes before the VA-hr accumulation registers overflow.

(42)

Data Sheet

Similar to active or reactive power accumulation, the fastest integration time occurs when the VAGAIN registers are set to maximum full scale, that is, 0x7FF. When overflow occurs, the content of the VA-hr accumulation registers can roll over to 0 and continue increasing in value.

By setting the VAEHF bit (Bit 2) of the mask register, the ADE7758 can be configured to issue an interrupt (IRQ) when the MSB of any one of the three VA-hr accumulation registers has changed, indicating that the accumulation register is half full.

Setting the RSTREAD bit (Bit 6) of the LCYMODE register enables a read-with-reset for the VA-hr accumulation registers; that is, the registers are reset to 0 after a read operation.

Integration Time Under Steady Load

The discrete time sample period (T) for the accumulation register is 0.4 μs (4/CLKIN). With full-scale, 60 Hz sinusoidal signals onthe analog inputs and the VAGAIN registers set to 0x000, theaverage word value from each LPF2 is 0xB99. The maximumvalue that can be stored in the apparent energy register before itoverflows is 216 − 1 or 0xFFFF. As the average word value is firstadded to the internal register, which can store 241 − 1 or 0x1FF,FFFF, FFFF before it overflows, the integration time under theseconditions with VADIV = 0 is calculated as

Time=

0x1FF,FFFF,FFFF

0xB99

×0.4μs=1.157sec (43)

When VADIV is set to a value different from 0, the time before overflow is scaled accordingly, as shown in Equation 44.

Time = Time(VADIV = 0) × VADIV

(44)

15IRMSCURRENT RMS SIGNAL0x1C82BVAG[11:0]LPF2++VADIV[7:0]0x00VRMSVOLTAGE RMS SIGNAL0x17F26350Hz0x00x174BAC40VARHR[15:0]0MULTIPLIER0%APPARENT POWER ISACCUMULATED (INTEGRATED) INTHE VA-HR ACCUMULATION REGISTERS0x0Figure 76. ADE7758 Apparent Energy Accumulation

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04443-07560HzData Sheet

Table 14. Inputs to VA-Hr Accumulation Registers

CONSEL[1, 0] 00 01 10 11

1

ADE7758

AVAHR1

AVRMS × AIRMS AVRMS × AIRMS AVRMS × AIRMS Reserved

BVAHR

BVRMS × BIRMS

AVRMS + CVRMS/2 × BIRMS BVRMS × BIRMS Reserved

CVAHR

CVRMS × CIRMS CVRMS × CIRMS CVRMS × CIRMS Reserved

AVRMS/BVRMS/CVRMS are the rms voltage waveform, and AIRMS/BIRMS/CIRMS are the rms values of the current waveform.

Energy Accumulation Mode

The apparent power accumulated in each VA-hr accumulation register (AVAHR, BVAHR, or CVAHR) depends on the con-figuration of the CONSEL bits in the COMPMODE register (Bit 0 and Bit 1). The different configurations are described in Table 14.

The contents of the VA-hr accumulation registers are affected by both the registers for rms voltage gain (VRMSGAIN), as well as the VAGAIN register of the corresponding phase.

root of their sum to determine the apparent energy over the same period.

ENERGY REGISTERS SCALING

The ADE7758 provides measurements of active, reactive, and apparent energies that use separate signal paths and filtering for calculation. The differences in the datapaths can result in small differences in LSB weight between the active, reactive, and apparent energy registers. These measurements are internally compensated so that the scaling is nearly one to one. The relationship between the registers is shown in Table 15. Table 15. Energy Registers Scaling

60 Hz

Integrator Off VAR VA

Integrator On VAR VA

Frequency

50 Hz

1.00 × WATT 1.0085 × WATT 1.00 × WATT 1.00845 × WATT

Apparent Power Frequency Output

Pin 17 (VARCF) of the ADE7758 provides frequency output for the total apparent power. By setting the VACF bit (Bit 7) of the WAVMODE register, this pin provides an output frequency that is directly proportional to the total apparent power.

A digital-to-frequency converter (DFC) is used to generate the pulse output from the total apparent power. The TERMSEL bits (Bit 2 to Bit 4) of the COMPMODE register can be used to select which phases to include in the total power calculation. Setting Bit 2, Bit 3, and Bit 4 includes the input to the AVAHR, BVAHR, and CVAHR registers in the total apparent power calculation. A pair of frequency divider registers, namely

VARCFDEN and VARCFNUM, can be used to scale the output frequency of this pin. Note that either VAR or apparent power can be selected at one time for this frequency output (see the Reactive Power Frequency Output section).

1.004 × WATT 1.00058 × WATT 1.0059 × WATT 1.00058 × WATT

WAVEFORM SAMPLING MODE

The waveform samples of the current and voltage waveform, as well as the active, reactive, and apparent power multiplier out-puts, can all be routed to the WAVEFORM register by setting the WAVSEL[2:0] bits (Bit 2 to Bit 4) in the WAVMODE register. The phase in which the samples are routed is set by setting the PHSEL[1:0] bits (Bit 0 and Bit 1) in the WAVMODE register. All energy calculation remains uninterrupted during waveform sampling. Four output sample rates can be chosen by using Bit 5 and Bit 6 of the WAVMODE register (DTRT[1:0]). The output sample rate can be 26.04 kSPS, 13.02 kSPS, 6.51 kSPS, or 3.25 kSPS (see Table 20).

By setting the WFSM bit in the interrupt mask register to

Logic 1, the interrupt request output IRQ goes active low when a sample is available. The 24-bit waveform samples are

transferred from the ADE7758 one byte (8 bits) at a time, with the most significant byte shifted out first.

The interrupt request output IRQ stays low until the interrupt routine reads the reset status register (see the Interrupts section).

Line Cycle Apparent Energy Accumulation Mode

The line cycle apparent energy accumulation mode is activated by setting the LVA bit (Bit 2) in the LCYCMODE register. The total apparent energy accumulated over an integer number of zero crossings is written to the VA-hr accumulation registers after the LINECYC number of zero crossings is detected. The operation of this mode is similar to watt-hr accumulation (see the Line Cycle Active Energy Accumulation Mode section). When using the line cycle accumulation mode, the RSTREAD bit (Bit 6) of the LCYCMODE register should be set to Logic 0. Note that this mode is especially useful when the user chooses to perform the apparent energy calculation using the vectorial method.

By setting LWATT and LVAR bits (Bit 0 and Bit 1) of the LCYCMODE register, the active and reactive energies are accumulated over the same period. Therefore, the MCU can perform the squaring of the two terms and then take the square

Rev. E | Page 41 of 72

ADE7758 Data Sheet

Rev. E | Page 42 of 72

Data Sheet

STARTCALIBRATE IRMSOFFSETADE7758

MUST BE DONEBEFORE VA GAINCALIBRATIONCALIBRATE VRMSOFFSETYESALLPHASESVA AND WATTGAIN CAL?NOSET UP PULSEOUTPUT FORA, B, OR CYESALLPHASESGAIN CALVAR?NOCALIBRATEWATT AND VAGAIN @ ITEST,PF = 1WATT AND VACAN BE CALIBRATEDSIMULTANEOUSLY @PF = 1 BECAUSE THEYHAVE SEPARATE PULSE OUTPUTSSET UP FORPHASEA, B, OR CYESALLPHASESPHASE ERROR CAL?NOCALIBRATEVAR GAIN@ ITEST, PF = 0,INDUCTIVESET UP PULSEOUTPUT FORA, B, OR CYESALL PHASESVAR OFFSETCAL?NOCALIBRATEPHASE @ ITEST,PF = 0.5,INDUCTIVESET UP PULSEOUTPUT FORA, B, OR CYESALL PHASESWATT OFFSETCAL?NOSET UP PULSEOUTPUT FORA, B, OR CENDCALIBRATEVAR OFFSET@ IMIN, PF = 0,INDUCTIVEFigure 77. Calibration Using Pulse Output

Gain Calibration Using Pulse Output

Gain calibration is used for meter-to-meter gain adjustment, APCF or VARCF output rate calibration, and determining the Wh/LSB, VARh/LSB, and VAh/LSB constant. The registers used for watt gain calibration are APCFNUM (0x45), APCFDEN (0x46), and xWG (0x2A to 0x2C). Equation 50 through Equation 52 show how these registers affect the Wh/LSB constant and the APCF pulses.

For calibrating VAR gain, the registers in Equation 50 through Equation 52 should be replaced by VARCFNUM (0x47),

VARCFDEN (0x48), and xVARG (0x2D to 0x2F). For VAGAIN, they should be replaced by VARCFNUM (0x47), VARCFDEN (0x48), and xVAG (0x30 to 0x32).

Figure 78 shows the steps for gain calibration of watts, VA, or VAR using the pulse outputs.

Rev. E | Page 43 of 72

04443-076CALIBRATEWATT OFFSET@ IMIN, PF = 1