FEATURESAC PERFORMANCEGain Bandwidth Product: 80 MHz (Gain = 2)Fast Settling: 100 ns to 0.01% for a 10 V StepSlew Rate: 375 V/sStable at Gains of 2 or GreaterFull Power Bandwidth: 6.0 MHz for 20 V p-pDC PERFORMANCEInput Offset Voltage: 1 mV maxInput Offset Drift: 14 V/؇CInput Voltage Noise: 9 nV/√Hz typOpen-Loop Gain: 90 V/mV into a 500 ⍀ LoadOutput Current: 100 mA minQuiescent Supply Current: 14 mA maxAPPLICATIONSLine DriversDAC and ADC BuffersVideo and Pulse AmplifiersAvailable in Plastic DIP, Hermetic Metal Can,Hermetic Cerdip, SOIC and LCC Packages and inChip FormMIL-STD-883B Parts AvailableAvailable in Tape and Reel in Accordance withEIA-481A StandardPRODUCT DESCRIPTIONThe AD842 is a member of the Analog Devices family of widebandwidth operational amplifiers. This device is fabricated usingAnalog Devices’ junction isolated complementary bipolar (CB)process. This process permits a combination of dc precision andwideband ac performance previously unobtainable in a mono-lithic op amp. In addition to its 80 MHz gain bandwidth, theAD842 offers extremely fast settling characteristics, typicallysettling to within 0.01% of final value in less than 100 ns for a10 volt step.The AD842 also offers a low quiescent current of 13 mA, a highoutput current drive capability (100 mA minimum), a low inputvoltage noise of 9 nV√Hz and a low input offset voltage (1 mVmaximum).The 375 V/µs slew rate of the AD842, along with its 80 MHzgain bandwidth, ensures excellent performance in video andpulse amplifier applications. This amplifier is ideally suited foruse in high frequency signal conditioning circuits and widebandwidth active filters. The extremely rapid settling time ofthe AD842 makes this amplifier the preferred choice for dataacquisition applications which require 12-bit accuracy. The*Covered by U.S. Patent Nos. 4,969,823 and 5,141,898.REV.E
Information furnished by Analog Devices is believed to be accurate andreliable. However, no responsibility is assumed by Analog Devices for itsuse, nor for any infringements of patents or other rights of third partieswhich may result from its use. No license is granted by implication orotherwise under any patent or patent rights of Analog Devices.
Wideband, High Output Current,Fast Settling Op AmpAD842*CONNECTION DIAGRAMSPlastic DIP (N) PackageLCC (E) PackageandCerdip (Q) PackageEECCNNAALLCACACNC1AD84214NCNBNBN0932121NC213BALANCEBALANCE312NCNC418NC–INPUT411V+–IN517+VSNC616NC+INPUT5+10OUTPUT+IN7+15OUTPUTV–69NCNC8AD84214NCNC7TOP VIEW8NC901311211NC = NO CONNECTCSCNVCC–NNNNC = NO CONNECTTO-8 (H) PackageSOIC (R-16) PackageBALANCENCNCNC116NCBALANCEV+BALANCE2AD84215BALANCEAD842–INPUT314+VS–INPUTOUTPUTNC413NC++INPUT512+INPUT+OUTPUTV–NC611NC–VS710NCNCNCNCNC8TOP VIEW9NCTOP VIEWNOTE: CAN BE TIED TO V+NC = NO CONNECTNC = NO CONNECTAD842 is also appropriate for other applications such as highspeed DAC and ADC buffer amplifiers and other wide band-width circuitry.APPLICATION HIGHLIGHTS1.The high slew rate and fast settling time of the AD842 makeit ideal for DAC and ADC buffers amplifiers, lines driversand all types of video instrumentation circuitry.2.The AD842 is a precision amplifier. It offers accuracy to0.01% or better and wide bandwidth; performance previouslyavailable only in hybrids.3.Laser-wafer trimming reduces the input offset voltage of1 mV max, thus eliminating the need for external offsetnulling in many applications.4.Full differential inputs provide outstanding performance inall standard high frequency op amp applications where thecircuit gain will be 2 or greater.5.The AD842 is an enhanced replacement for the HA2542.One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781/329-4700World Wide Web Site: http://www.analog.comFax: 781/326-8703© Analog Devices, Inc., 2000
AD842–SPECIFICATIONS(@ +25؇C and ؎15 V dc, unless otherwise noted)
ModelConditionsINPUT OFFSET VOLTAGE3TMIN–TMAXOffset DriftINPUT BIAS CURRENTTMIN–TMAXInput Offset CurrentTMIN–TMAXINPUT CHARACTERISTICSInput ResistanceInput CapacitanceINPUT VOLTAGE RANGECommon ModeCommon-Mode RejectionINPUT VOLTAGE NOISEWideband NoiseOPEN-LOOP GAINDifferential Mode1002.0؎108680؎1090861002.0؎1086801002.0kΩpFVdBdBnV/√HzµV rmsV/mVV/mVVmAΩMHzMHzns%V/µsnsns%DegreeVVmAmAdBdB°C0.1144.28100.40.5MinAD842J/JR1TypMax0.51.52.5/3AD842K Min TypMax0.3143.50.05560.20.31.01.5 MinAD842S2 Typ0.5144.20.18120.40.6Max1.53.5UnitsmVmVµV/°CµAµAµAµAVCM = ±10 VTMIN–TMAXf = 1 kHz10 Hz to 10 MHzVO = ±10 VRLOAD ≥ 500 ΩTMIN–TMAXRLOAD ≥ 500 ΩVOUT = ±10 VOpen LoopVOUT = 90 mVVO = 20 V p-pRLOAD ≥ 500 ΩAVCL = –2AVCL = –2AVCL = –210 V Stepto 0.1%to 0.01%f = 4.4 MHzf = 4.4 MHz11592811592811592840/3020/15؎10100905025؎10100904020؎1010090OUTPUT CHARACTERISTICSVoltageCurrentFREQUENCY RESPONSEGain Bandwidth ProductFull Power Bandwidth4Rise TimeOvershoot5Slew Rate5Settling Time555804.761020375801000.0150.035±15؎513/14؎18؎514/1616/19.59086+7504.758061020375801000.0150.035±1513105؎181416؎54.758061020375801000.0150.035±15138680+75–55100؎181419300300300Differential GainDifferential PhasePOWER SUPPLYRated PerformanceOperating RangeQuiescent CurrentPower Supply Rejection RatioTEMPERATURE RANGERated Performance6PACKAGE OPTIONSPlastic (N-14)Cerdip (Q-14)SOIC (R-16)Tape and ReelTO-8 (H-12A)LCC (E-20A)ChipsTMIN–TMAXVS = ±5 V to ±18 VTMIN–TMAX86800100+125AD842JNAD842JQAD842JR-16AD842JR-16-REELAD842JR-16-REEL7AD842JHAD842JCHIPSAD842KNAD842KQAD842SQ, AD842SQ/883BAD842KHAD842SH AD842SE/883BAD842SCHIPSNOTES1AD842JR specifications differ from those of the AD842JN, JQ and JH due to the thermal characteristics of the SOIC package.2Standard Military Drawing available 5962-8964201xx2A – (SE/883B); XA – (SH/883B); CA – (SQ/883B).3Input offset voltage specifications are guaranteed after 5 minutes at TA = +25°C.4Full power bandwidth = slew rate/2 π VPEAK.5Refer to Figures 22 and 23.6“S” grade TMIN–TMAX specifications are tested with automatic test equipment at TA = –55°C and TA = +125°C.All min and max specifications are guaranteed. Specifications shown in boldface are tested on all production units.Specifications subject to change without notice.–2–
REV. E
AD842
ABSOLUTE MAXIMUM RATINGS1Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 VInternal Power Dissipation2Plastic (N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 WCerdip (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 WTO-8 (H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 WSOIC (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 WLCC (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 WInput Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VSDifferential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . ±6 VStorage Temperature RangeQ, H, E . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°CN, R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +125°CJunction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +175°CLead Temperature Range (Soldering 60 sec) . . . . . . . . +300°CNOTES1Stresses above those listed under Absolute Maximum Ratings may cause perma-nent damage to the device. This is a stress rating only; functional operation of thedevice at these or any other conditions above those indicated in the operationalsection of this specification is not implied. Exposure to absolute maximum ratingconditions for extended periods may affect device reliability.2Maximum internal power dissipation is specified so that TJ does not exceed+150°C at an ambient temperature of +25°C.Thermal Characteristics:θJCθJAθSAPlastic Package30°C/W100°C/WCerdip Package30°C/W110°C/W38°C/WTO-8 Package30°C/W100°C/W27°C/W16-Lead SOIC Package30°C/W100°C/W20-Lead LCC Package35°C/W150°C/WRecommended Heat Sink: Aavid Engineering© #602BMETALIZATION PHOTOGRAPHContact factory for latest dimensions.Dimensions shown in inches and (mm).REV. E–3–
AD842–Typical Characteristics(at +25؇C and V = ؎15 V, unless otherwise noted)
S
20stlo V –15NGEARVIN DEMO10-NMOMCO5 TUNPI005101520SUPPLY VOLTAGE – ؎VoltsFigure 1.Input Common-ModeRange vs. Supply Voltage18Am –16 TNRERUC14 TNCESIEU12Q1005101520SUPPLY VOLTAGE – ؎ VoltsFigure 4.Quiescent Current vs.Supply Voltage1817Am –16 TNER15RUC14 TNEC13S EIU12Q1110–60–40–20020406080100120140TEMPERATURE – ؇CFigure 7.Quiescent Current vs.Temperature20stlo V–15 NG؎ VOUTIW S10AGETL VOTU5TPUO005101520SUPPLY VOLTAGE –؎ VoltsFigure 2.Output Voltage Swingvs. Supply Voltage–5A– TNE–4RRUC SAIB TU–3 PNI–2–60–40–20020406080100120140TEMPERATURE – ؇CFigure 5.Input Bias Current vs.Temperature300Am –275 TIMI250L T+ OUTPUT CURRENTNE225RRUC200 TIUC175R–OUTPUT CURRENTIC T150ROH125S100–60–40–20020406080100120140AMBIENT TEMPERATURE – ؇CFigure 8.Short-Circuit CurrentLimit vs. Temperature–4–
30p-p s25tloV؎ 15V SUPPLIES – G20NIWS E15GATLO10V TUP5TUO0101001k10kLOAD RESISTANCE – ⍀Figure 3.Output Voltage Swingvs. Load Resistance100⍀ –10 ECNADEP1MI TUPTUO0.10.0110k100k1M10M100MFREQUENCY – HzFigure 6.Output Impedance vs.Frequency85zHM80 – HTDIWD75NAB NIAG7065–60–40–20020406080100120140TEMPERATURE – ؇CFigure 9.Gain Bandwidth Productvs. TemperatureREV. E
12010010080Bdrees –8060g NIDeA – GN6040IOPRGLOA-MN4020 E OP500⍀ LOADASEHP20001001k10k100k1M10M100MFREQUENCY – HzFigure 10.Open-Loop Gain andPhase Margin vs. Frequency120VS = ؎ 15VVCM = 1V p-p100+ 25؇CBd80 – RMC60 40201k10k100k1M10M100MFREQUENCY – HzFigure 13.Common-ModeRejection vs. Frequency–803V RMSRL = 1k⍀B–90d – NIO–100TRTO–1102ND HARMONICISD CIN–120MORAH–1303RD HARMONIC–1401001k10k100kFREQUENCY – HzFigure 16.Harmonic Distortion vs.FrequencyREV. E110Bd105 –NIA GOP100LO-N500⍀ LOAD OPE959005101520SUPPLY VOLTAGE – ؎VFigure 11.Open-Loop Gain vs.Supply Voltage30RL = 1kV+25؇Cp-p25VS = ؎15V tsloV 20– EGAT15LOV TU10 PTUO501M10M100MFREQUENCY – HzFigure 14.Large Signal FrequencyResponse50z40H nV – 30AGETL20 VOTU NPI100101001k10k100k1M10MFREQUENCY – HzFigure 17.Input Voltage vs.Frequency–5–
AD842
120Bd–100 N+ SUPPLYIOTC80REJE 60LYP– SUPPLYUP40 S RWE20PO01001k10k100k1M10M100MFREQUENCY – HzFigure 12.Power Supply Rejectionvs. Frequency108؎V 6TO 04MRO2F0.1%0.01% 0NGIW0.1%0.01%–2 ST U–4TPUO–6–8–1030405060708090100110SETTLING TIME – nsFigure 15.Output Swing andError vs. Settling Time550500sV450 – ETA400R WEL350S300250–60–40–20020406080100120140TEMPERATURE – ؇CFigure 18.Slew Rate vs.TemperatureAD842
RF = 1k⍀0.1F+VSHP3314ARIN =2.2FFUNCTION499⍀GENERATOR–ORVEQUIVALENT49.9⍀AD842OUT+0.1F499⍀332⍀2.2F–VSFigure 19a.Inverting AmplifierConfiguration (DIP Pinout)R1 = 205⍀RF = 205⍀0.1F+VS2.2F–VHP3314AFUNCTIONVIN100⍀AD842OUTGENERATOR+0.1F499⍀OREQUIVALENT49.9⍀2.2F–VSFigure 20a.Noninverting AmplifierConfiguration (DIP Pinout)Figure 19b.Inverter Large SignalPulse ResponseFigure 20b.Noninverting LargeSignal Pulse Response–6–
Figure 19c.Inverter Small SignalPulse ResponseFigure 20c.Noninverting SmallSignal Pulse ResponseREV. E
AD842
OFFSET NULLINGThe input offset voltage of the AD842 is very low for a highspeed op amp, but if additional nulling is required, the circuitshown in Figure 21 can be used.AD842 SETTLING TIMEERRORAMP(؋15)TEK7A13TEK7603OSCILLOSCOPETEK7A16Figures 22 and 24 show the settling performance of the AD842in the test circuit shown in Figure 23.Settling time is defined as:The interval of time from the application of an ideal stepfunction input until the closed-loop amplifier output hasentered and remains within a specified error band.This definition encompasses the major components which com-prise settling time. They include (1) propagation delay throughthe amplifier; (2) slewing time to approach the final output value;(3) the time of recovery from the overload associated with slew-ing and (4) linear settling to within the specified error band.Expressed in these terms, the measurement of settling time isobviously a challenge and needs to be done accurately to assurethe user that the amplifier is worth consideration for theapplication.+VS10k⍀0.1F2.2FINPUTDDD5109FLAT-TOPPULSEGENERATOR499⍀1k⍀499⍀50⍀1k⍀HP62630.1F+15V2.2FFET PROBETEK P62010.1F499⍀2.2F–15V499⍀AD842 Figure 23.Settling Time Test Circuit–AD842+OUTPUT0.1F2.2FRL–VSFigure 23 shows how measurement of the AD842’s 0.01% set-tling in 100 ns was accomplished by amplifying the error signalfrom a false summing junction with a very high-speed propri-etary hybrid error amplifier specially designed to enable testingof small settling errors. The device under test was driving a300 Ω load. The input to the error amp is clamped in order toavoid possible problems associated with the overdrive recoveryof the oscilloscope input amplifier. The error amp gains theerror from the false summing junction by 15, and it contains again vernier to fine trim the gain.Figure 24 shows the “long term” stability of the settling charac-teristics of the AD842 output after a 10 V step. There is noevidence of settling tails after the initial transient recovery time.The use of a junction isolated process, together with carefullayout, avoids these problems by minimizing the effects of tran-sistor isolation capacitance discharge and thermally inducedshifts in circuit operating points. These problems do not occureven under high output current conditions.Figure 21.Offset Nulling (DIP Pinout)Figure 22.0.01% Settling TimeREV. E–7–
AD842
GROUNDING AND BYPASSINGUSING A HEAT SINKIn designing practical circuits with the AD842, the user mustremember that whenever high frequencies are involved, someThe AD842 draws less quiescent power than most precisionhigh speed amplifiers and is specified for operation without aheat sink. However, when driving low impedance loads, the cur-rent to the load can be 10 times the quiescent current. This willcreate a noticeable temperature rise. Improved performance canbe achieved by using a small heat sink such as the Aavid Engi-neering #602B.TERMINATED LINE DRIVERThe AD842 is optimized for high speed line driver applications.Figure 25 shows the AD842 driving a doubly terminated cablein a gain-of-2 follower configuration. The AD842 maintains atypical slew rate of 375 V/µs, which means it can drive a ±10 V,6.0 MHz signal or a ±3 V, 19.9 MHz signal.Figure 24.AD842 Settling Demonstrating No SettlingTailsspecial precautions are in order. Circuits must be built withshort interconnect leads. Large ground planes should be usedwhenever possible to provide a low resistance, low inductancecircuit path, as well as minimizing the effects of high frequencycoupling. Sockets should be avoided because the increasedinterlead capacitance can degrade bandwidth.Feedback resistors should be of low enough value to assure thatthe time constant formed with the circuit capacitances will notlimit the amplifier performance. Resistor values of less than5 kΩ are recommended. If a larger resistor must be used, a small(<10 pF) feedback capacitor connected in parallel with the feed-back resistor, RF, may be used to compensate for these straycapacitances and optimize the dynamic performance of theamplifier in the particular application.Power supply leads should be bypassed to ground as close aspossible to the amplifier pins. A 2.2 µF capacitor in parallel witha 0.1 µF ceramic disk capacitor is recommended.CAPACITIVE LOAD DRIVING ABILITYThe termination resistor, RT, (when equal to the characteristicimpedance of the cable) minimizes reflections from the far endof the cable. A back-termination resistor (RBT, also equal to thecharacteristic impedance of the cable) may be placed betweenthe AD842 output and the cable in order to damp any straysignals caused by a mismatch between RT and the cable’s char-acteristic impedance. This will result in a “cleaner” signal. Withthis circuit, the voltage on the line equals VIN because one halfof VOUT is dropped across RBT.The AD842 has ±100 mA minimum output current and, there-fore, can drive ±5 V into a 50 Ω cable.The feedback resistors, R1 and R2, must be chosen carefully.Large value resistors are desirable in order to limit the amountof current drawn from the amplifier output. But large resistorscan cause amplifier instability because the parallel resistanceR1ʈR2 combines with the input capacitance (typically 2–5 pF) tocreate an additional pole. Also, the voltage noise of the AD842is equivalent to a 5 kΩ resistor, so large resistors can signifi-cantly increase the system noise. Resistor values of 1 kΩ or 2 kΩare recommended.If termination is not used, cables appear as capacitive loads andcan be decoupled from the AD842 by a resistor in series withthe output.Like all wideband amplifiers, the AD842 is sensitive to capaci-tive loading. The AD842 is designed to drive capacitive loads ofup to 20 pF without degradation of its rated performance. Ca-pacitive loads of greater than 20 pF will decrease the dynamicperformance of the part although instability should not occurunless the load exceeds 100 pF.2.2F+VS0.1FVINTERMINATIONRESISTOR FORINPUT SIGNAL+AD842–0.1FRST50⍀ OR 75⍀CABLERTR1–VS2.2FRT = RST = CABLE CHARACTERISTICIMPEDANCER2Figure 25.Line Driver Configuration–8–
REV. E
AD842
OVERDRIVE RECOVERY2.2F+VS0.1FHP3314APULSE GENERATOROR EQUIVALENT1s, ؎1V SQUAREWAVE INPUT50⍀–VS2.2F–Figure 26 shows the overdrive recovery capability of the AD842.Typical recovery time is 80 ns from negative overdrive and400 ns from positive overdrive.AD842+0.1FOUTPUT1k⍀Figure 27.Overdrive Recovery Test CircuitFigure 26.Overdrive RecoveryREV. E–9–
AD842
OUTLINE DIMENSIONSDimensions shown in inches and (mm).14-Lead Plastic Package14-Lead Cerdip Package (N-14) (Q-14)0.795 (20.19)0.005 (0.13) MIN0.098 (2.49) MAX0.725 (18.42)1481480.280 (7.11)0.310 (7.87)170.240 (6.10)10.220 (5.59)PIN 10.325 (8.25)70.100 (2.54)0.060 (1.52)0.300 (7.62)PIN 10.320 (8.13)BSC0.290 (7.37)0.210 (5.33)0.015 (0.38) 0.785 (19.94) MAX0.060 (1.52)0.195 (4.95)MAX0.1300.115 (2.93)0.200 (5.08)0.015 (0.38)MAX0.160 (4.06)(3.30)0.1500.115 (2.93)MIN0.200 (5.08)(3.81)0.015 (0.381)0.022 (0.558)0.070 (1.77)SEATING0.125 (3.18)MIN0.008 (0.204)0.015 (0.38)0.014 (0.356)0.045 (1.15)PLANE0.023 (0.58)0.1000.070 (1.78)SEATING15°0.014 (0.36)(2.54)0.008 (0.20)BSC0.030 (0.76)PLANE0°16-Lead SOIC Package20-Terminal Leadless Ceramic Chip Carrier Package (R-16)(E-20A)0.4133 (10.50)0.200 (5.08)0.3977 (10.00)0.100 (2.54)0.075BSC0.064 (1.63)(1.91)REF0.100 (2.54) BSC1690.095 (2.41)0.015 (0.38)0.2992 (7.60)193MIN0.075 (1.90)182040.2914 (7.40)0.358 (9.09)0.3580.028 (0.71)0.011 (0.28)10.4193 (10.65)0.342 (8.69)(9.09)0.007 (0.18)BOTTOM0.022 (0.56)180.3937 (10.00)SQMAXSQR TYPVIEW0.050 (1.27)0.075 (1.91)148BSCREF139PIN 145° TYP0.050 (1.27)0.1043 (2.65)BSC0.0926 (2.35)0.0291 (0.74)؋ 450.088 (2.24)0.055 (1.40)0.150 (3.81)0.0098 (0.25)؇0.054 (1.37)0.045 (1.14)BSC0.0118 (0.30)0.0192 (0.49)8؇SEATING0.0040 (0.10)0.0138 (0.35)PLANE0.0125 (0.32)0؇0.0500 (1.27)0.0091 (0.23)0.0157 (0.40)12-Lead Metal Can Package(TO-8 Style)REFERENCE PLANE0.181 (4.60)0.375 (9.53)0.200 (5.08)0.148 (3.76)MIN0.050 (1.27) MAXBSC0.100 (2.54)BSC))))246004789..18..105511430.200((110.4006(( 52(10.16)511(5.08)19556554BSC.55..000412BSC.0 3210.019 (0.48)0.036 (0.91)0.040 (1.02) MAX0.016 (0.41)0.045 (1.14)0.021 (0.53)0.037 (0.94)0.026 (0.66)0.000 (0.00)0.016 (0.41)0.026 (0.66)BASE & SEATING PLANE–10–
REV. E
)E .ver( 00/3–0–c5911C.A.S.U NI DETNIRP
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