IC(bathtub curve)
ICFITIC
ICIC
(Reliability)(bathtub curve)(Failure unIT, FIT)
(Accelerated Testing)(Acceleration Factor)
ICICIC9020000.1850ICICSIA(Semiconductor Industry Association)IC[1]IC(Long term failurerate)90FIT(Failure unIT)FIT8
57
ICIC(failurerate)ICICICICA(infancy period)B(useful life period)ICC(wear outperiod)IC(Bathtub Curve)ICPPM(Parts Per Million)(WeibullDistribution)FIT109(device-hour)(ESD)(EOS)58
8
Historical IC Failure Rates
1000IntelAT & T/Lucent)TIF( e100taR 0.25erul0.13iFa m0.10r10 TegnoL1'70'75'80'85'90'9520002005Year
1 FIT = 1 fail in 109 device-hours
SIAIC
(λ)ABC
(Exponential Distribution)0.1%(Cumulative Distribution Function)(Lognormal Distribution)ICICICICIC(Burn-In)ICFITICFIT(λ)[2],[3]λ(in FIT)= M×109/N×Ts×AfMχ222(r+1)/2χ2(r+1)(Confidence Level)2(r+1)(Degrees of freedom)(Chi squared distribution value)rNTsAfFITICFITIC10011%90%(Confidence Level)3.89%1000101%90%1.5%1%[3]ICFITICICIC(Acceleration Factor)Arrhenius model[3]TAF=Lnormal/Lstress=exp[(Ea/k)×(1/Tnormal-1/Tstress)],LnormalLstressEa(eV)kBoltzmann’s constant(8.62×10-5eV/K)Tnormaland TstressEyring model[3]Vβ(Vstress-Vnormal)AF=10,VnormalVstress8
59
β(exp)10βHallbergPeck[3]HAF=(RHstress/RHnormal)nwith n=2~3,RHnormalRHstressn2~3Coffin-Mason equation [3]TEAF=(∆Tstress/∆Tnormal)nwith n4~8,∆Tnormal∆Tstressn4~8IC(Device-level)TDDB(Time-Dependent Dielectric Breakdown)HCI(Hot Carrier Injection)EM(Electro Migration)ICICICEFTHTOLTHBHTSLTCTTSTPCTESDLatchUpSER608 Endurance cycling testData retentiontest1. EFT(Early Fail Test)ICIC2. HTOL(High Temperature OperatingLife Test)ICIC3. THB(Temperature Humidity BiasTest)IC85°C85%85/85IC4. HTSL(High Temperature StorageLife Test)ICIC5. TCT(Temperature Cycling Test)ICICair to air6. TST(Thermal Shock Test)ICTCTliquid to liquid7. PCT(Pressure Cooker Test)ICTHB(121°C)(100%R.H.)8. ESD(Electro Static Discharge Test)ICHBM(Human Body Model)MM(Machine Model)CDM(Charge DeviceModel)HBMMMICCDM9. Latch UpICLatch UpCMOS10. SER(Soft Error Rate Test)ICα(Soft Error)DRAMSRAM11. Endurance Cycling TestICIC12. Data Retention TestICIC[5~30]ICICICIC1.BIR(Built-In Reliability)2.WLR(Wafer Level Reliability)3.QML (Qualified Manufacturing Line)4.POF(Physics of Failure)[31]Hu [32]BIRBIRSPC(Statistical Process Control)B/I(Burn-In)In-Line TestingWLRWafer level[33]QML[34]Test CircuitPOF[35]8 61ICICIC1.SIA (Semiconductor Industry Association)reliability road map.2.Accelerated Testing Handbook, D.S. Peck andO.D. Trapp.3.Applied Reliability second edition, Tobiasand Trindade.4.Paul Syndergaard,Having Fits OverFITS, 2000 Cahners Business Information.5.MIL-STD-883D, METHOD 1015.9.6.EIAJ ED-4701, METHOD D-101.7.JESD22-A108-A.8.MIL-STD-883D, METHOD 1005.8.9.EIAJ ED-4701, METHOD B-122.10.EIAJ ED-4701, METHOD B-123.11.EIAJ ED-4701, METHOD B-131.12.JESD22-A104-A.13.MIL-STD-883D, METHOD 1010.7.14.EIAJ ED-4701, METHOD B-141.15.MIL-STD-883D, METHOD 1011.9.16.JESD22-A102-B.628
17.EIAJ ED-4701, METHOD B-111.18.MIL-STD-883D, METHOD 1008.2.19.EIAJ ED-4701-1 C-113.20.JESD17.21.JESD78.22.EIAJ ED-4701, METHOD C-111.23.EIAJ ED-4701-1, METHOD C-111A.24.ANSI/ESD-S5.2-1994.25.ANSI/EOS/ESD-S5.1-1993.26.ESD DS5.3.1.27.JESD22-C101.28.JESD22-A114-A.29.JESDS22-A115-A.30.MIL-S-19500.31.Way Kuo, Taeho Kim, An overview ofmanufacturing yield and reliability modelingfor semiconductor products., Proc. of theIEEE Vol.87, no.8.1999.32.C. Hu, Future CMOS scaling andreliability, Proc. IEEE, vol.81,pp.682-689,May 1993.33.J.A. Schideler, T. Turner, J. Reedholm, and C.Messck, A systematic approach to waferlevel reliability, Solid state Technol.,vol.38, no.3, p.47 Mar.1995.34.J.M. Soden and R.E. Anderson, IC failureanalysis: Techniques and tools for quality andreliabilty improvement, Proc. IEEE, vol.81,pp.703-715, May 1993.35.B. Schlund, C. Messick, J. Suehle, and P.Chaparala, A new physics-based model fortime-dependent-dielectric-breakdown, inIntegrated Reliability Workshop, Final Rep.Int., 1995,pp.72-80.
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