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UCC27423, UCC27424, UCC27425SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004DUAL 4ĆA HIGH SPEED LOW-SIDE MOSFET DRIVERS WITH ENABLEFEATURESDIndustry-Standard Pin-OutDEnable Functions for Each DriverDHigh Current Drive Capability of ±4 ADUnique BiPolar and CMOS True Drive OutputDDDDDDDDESCRIPTIONThe UCC27423/4/5 family of high-speed dual MOSFETdrivers can deliver large peak currents into capacitiveloads.Three standard logic options are offered –dual-inverting, dual-noninverting and one-inverting andone-noninverting driver. The thermally enhanced 8-pinPowerPADTM MSOP package (DGN) drastically lowersthe thermal resistance to improve long-term reliability.It is also offered in the standard SOIC-8 (D) or PDIP-8(P) packages.Using a design that inherently minimizes shoot-throughcurrent, these drivers deliver 4-A of current where it isneeded most at the Miller plateau region during theMOSFET switching transition. A unique BiPolar andMOSFET hybrid output stage in parallel also allowsefficient current sourcing and sinking at low supplyvoltages.The UCC27423/4/5 provides enable (ENBL) functionsto have better control of the operation of the driverapplications. ENBA and ENBB are implemented on pins1 and 8 which were previously left unused in the industrystandard pin-out. They are internally pulled up to Vdd foractive high logic and can be left open for standardoperation.Stage Provides High Current at MOSFETMiller ThresholdsTTL/CMOS Compatible Inputs Independent ofSupply Voltage20-ns Typical Rise and 15-ns Typical FallTimes with 1.8-nF LoadTypical Propagation Delay Times of 25 ns withInput Falling and 35 ns with Input Rising4-V to 15-V Supply VoltageDual Outputs Can Be Paralleled for HigherDrive CurrentAvailable in Thermally Enhanced MSOPPowerPADTM Package with 4.7°C/W θjcRated From –40°C to 105°CAPPLICATIONSDSwitch Mode Power SuppliesDDC/DC ConvertersDMotor ControllersDLine DriversDClass D Switching Amplifiers BLOCK DIAGRAM8ENBA1INVERTINGENBB 7INA2VDDNON−INVERTINGINVERTINGGND35INB4NON−INVERTING6OUTAVDDOUTBUDG−01063PowerPADt is a trademark of Texas Instruments Incorporated.Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstrumentssemiconductor products and disclaimers thereto appears at the end of this data sheet.PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.Copyright  2003, Texas Instruments Incorporatedwww.ti.com1UCC27423, UCC27424, UCC27425SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004ORDERING INFORMATIONOUTPUT CONFIGURATIONDual invertingDual nonInvertingOne inverting,one noninvertingTEMPERATURE RANGETA = TJ−40°C to +105°C−40°C to +105°C−40°C to +105°CPACKAGED DEVICESSOIC-8 (D)UCC27423DUCC27424DUCC27425DMSOP-8 PowerPAD(DGN)}UCC27423DGNUCC27424DGNUCC27425DGNPDIP-8 (P)UCC27423PUCC27424PUCC27425P†D (SOIC−8) and DGN (PowerPAD−MSOP) packages are available taped and reeled. Add R suffix to device type (e.g. UCC27423DR,UCC27424DGNR) to order quantities of 2,500 devices per reel for D or 1,000 devices per reel for DGN package.‡The PowerPAD is not directly connected to any leads of the package. However, it is electrically and thermally connected to the substrate whichis the ground of the device.D, DGN, OR P PACKAGE(TOP VIEW)UCC27423ENBA1INA2GND3INB48ENBB7OUTA6VDD5OUTBENBA1INA2GND3INB4D, DGN, OR P PACKAGE(TOP VIEW)UCC274248ENBB7OUTA6VDD5OUTBENBA1INA2GND3INB4D, DGN, OR P PACKAGE(TOP VIEW)UCC274258ENBB7OUTA6VDD5OUTB(DUAL INVERTING)(DUAL NON−INVERTING)(ONE INVERTING ANDONE NON−INVERTING)power dissipation rating tablePACKAGESOIC-8PDIP-8MSOP PowerPAD-8See Note 3SUFFIXDPDGNΘjc (°C/W)42494.7Θja (°C/W)84 – 160}11050 − 59}Power Rating (mW) TA = 70°C See Note 1344−655 See Note 25001370Derating Factor Above70°C (mW/5C) SeeNote 16.25 − 11.9 See Note 2917.1Notes: 1.125°C operating junction temperature is used for power rating calculations2.The range of values indicates the effect of pc−board. These values are intended to give the system designer an indication of thebest and worst case conditions. In general, the system designer should attempt to use larger traces on the pc−board where possiblein order to spread the heat away form the device more effectively. For information on the PowerPADt package, refer to TechnicalBrief, PowerPad Thermally Enhanced Package, Texas Instrument s Literature No. SLMA002 and Application Brief, PowerPad MadeEasy, Texas Instruments Literature No. SLMA004.3.The PowerPAD is not directly connected to any leads of the package. However, it is electrically and thermally connected to thesubstrate which is the ground of the device.Table 1. Input/Output TableINPUTS (VIN_L, VIN_H)ENBAHHHHLENBBHHHHLINALLHHXINBLHLHXUCC27423OUTAHHLLLOUTBHLHLLUCC27424OUTALLHHLOUTBLHLHLUCC27425OUTAHHLLLOUTBLHLHL2www.ti.comUCC27423, UCC27424, UCC27425SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004absolute maximum ratings over operating free-air temperature (unless otherwise noted)†}Supply voltage, VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 16 VOutput current (OUTA, OUTB) DC, IOUT_DC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 A Pulsed, (0.5 µs), IOUT_PULSED. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 AInput voltage (INA, INB), VIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −5 V to 6 V or VDD+0.3 (whichever is larger)Enable voltage (ENBA, ENBB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V or VDD+0.3 (whichever is larger)Power dissipation at TA = 25°C (DGN package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 W (D package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650 mW (P package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 mWJunction operating temperature, TJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°CStorage temperature, Tstg. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°CLead temperature (soldering, 10 sec.),. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.‡All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal.ELECTRICAL CHARACTERISTICSVDD = 4.5 V to 15 V, TA = −40°C to 105°C,TA = TJ, (unless otherwise noted)PARAMETERInput (INA, INB)VIN_H, logic 1 input thresholdVIN_L, logic 0 input thresholdInput currentOutput (OUTA, OUTB)Output currentVOH, high-level output voltageVOL, low-level output levelOutput resistance highVDD = 14 V,See Note 1,VOH = VDD – VOUT,IOUT = 10 mATA = 25°C, IOUT = −10 mA,See Note 3TA = full range,See Note 3Output resistance lowTA = 25°C,See Note 3TA = full rangeSee Note 3Latch-up protectionSee Note 1IOUT = −10 mA,IOUT = 10 mA,IOUT = 10 mA,VDD = 14 V,VDD = 14 V,VDD = 14 V,VDD = 14 V,25181.91.25002.2See Note 2IOUT = −10 mA433022304504035452.54.0AmVmVΩΩΩΩmA0 V <= VIN <= VDD−1002110VVµATEST CONDITIONMINTYPMAXUNITSNOTES:1.Ensured by design. Not tested in production.2.The pullup / pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The pulsed output current rating is thecombined current from the bipolar and MOSFET transistors.3.The pullup / pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The output resistance is the RDS(ON) ofthe MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor.www.ti.com3UCC27423, UCC27424, UCC27425SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004ELECTRICAL CHARACTERISTICSVDD = 4.5 V to 15 V, TA = −40°C to 105°C,TA = TJ, (unless otherwise noted)PARAMETERSwitching TimetR, rise time (OUTA, OUTB)tF, fall time (OUTA, OUTB)tD1, delay, IN rising (IN to OUT)tD2, delay, IN falling (IN to OUT)Enable (ENBA, ENBB)VIN_H, high-level input voltageVIN_L, low-level input voltageHysteresisRENBL, enable impedancetD3, propagation delay time(4)tD4, propagation delay time(4)OverallINA = 0 V, UCC27423INA = 0 V, INA = HIGH, INA = HIGH, INA = 0 V, IDD, static operating current,VDD = 15 V, ENBA = ENBB = 15 VUCC27424INA = 0 V, INA = HIGH, INA = HIGH, INA = 0 V, UCC27425INA = 0 V, INA = HIGH, INA = HIGH, INA = 0 V, IDD, disabled, VDD = 15 V,ENBA = ENBB = 0 VAllINA = 0 V, INA = HIGH, INA = HIGH, INB = 0 VINB = HIGHINB = 0 VINB = HIGHINB = 0 VINB = HIGHINB = 0 VINB = HIGHINB = 0 VINB = HIGHINB = 0 VINB = HIGHINB = 0 VINB = HIGHINB = 0 VINB = HIGH9007507506003007507501200600105045090030045045060013501100110090045011001100180090016007001350450700700900µAVDD = 14 V, CLOAD = 1.8 nF(1)CLOAD = 1.8 nF(1)ENBL = GNDLO to HI transitionHI to LO transition1.71.10.15752.41.80.55100301002.92.20.9014060150VVkΩnsCLOAD = 1.8 nF,(1)CLOAD = 1.8 nF,(1)CLOAD = 1.8 nF,(1)CLOAD = 1.8 nF,(1)2015253540404050nsTEST CONDITIONMINTYPMAXUNITSNOTES:1.Ensured by design. Not production.2.The pullup / pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The peak output current rating is thecombined current from the bipolar and MOSFET transistors.3.The pullup / pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The output resistance is the RDS(ON) ofthe MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor.4.See Figure 2.4www.ti.comUCC27423, UCC27424, UCC27425SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004(a)+5V90%(b)90%INPUTINPUT0V10%tf90%OUTPUT10%tD116V90%OUTPUTtFtD2tFtD190%tD2tF0V10%10%Figure 1. Switching Waveforms for (a) Inverting Driver and (b) Noninverting Driver5VENBx0VtD3VDD90%OUTxtR10%0V90%tFtD4VIN_HVIN_LFigure 2. Switching Waveform for Enable to OutputNOTE:The 10% and 90% thresholds depict the dynamics of the BiPolar output devices that dominate thepower MOSFET transition through the Miller regions of operation.www.ti.com5UCC27423, UCC27424, UCC27425SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004Terminal FunctionsTERMINALNO.1NAMEENBAI/OIFUNCTIONEnable input for the driver A with logic compatible threshold and hysteresis. The driveroutput can be enabled and disabled with this pin. It is internally pulled up to VDD with100-kΩ resistor for active high operation. The output state when the device is disabledwill be low regardless of the input state.Input A. Input signal of the A driver which has logic compatible threshold and hysteresis.If not used, this input should be tied to either VDD or GND. It should not be left floating.Common ground. This ground should be connected very closely to the source of thepower MOSFET which the driver is driving.Input B. Input signal of the A driver which has logic compatible threshold and hysteresis.If not used, this input should be tied to either VDD or GND. It should not be left floating.Driver output B. The output stage is capable of providing 4-A drive current to the gate ofa power MOSFET.Supply. Supply voltage and the power input connection for this device.Driver output A. The output stage is capable of providing 4-A drive current to the gate ofa power MOSFET.Enable input for the driver B with logic compatible threshold and hysteresis. The driveroutput can be enabled and disabled with this pin. It is internally pulled up to VDD with100-kΩ resistor for active high operation. The output state when the device is disabledwill be low regardless of the input state.2345678INAGNDINBOUTBVDDOUTAENBBI−IOIOIAPPLICATION INFORMATIONGeneral InformationHigh frequency power supplies often require high-speed, high-current drivers such as the UCC27423/4/5 family.A leading application is the need to provide a high power buffer stage between the PWM output of the controlIC and the gates of the primary power MOSFET or IGBT switching devices. In other cases, the driver IC isutilized to drive the power device gates through a drive transformer. Synchronous rectification supplies alsohave the need to simultaneously drive multiple devices which can present an extremely large load to the controlcircuitry.Driver ICs are utilized when it is not feasible to have the primary PWM regulator IC directly drive the switchingdevices for one or more reasons. The PWM IC may not have the brute drive capability required for the intendedswitching MOSFET, limiting the switching performance in the application. In other cases there may be a desireto minimize the effect of high frequency switching noise by placing the high current driver physically close tothe load. Also, newer ICs that target the highest operating frequencies may not incorporate onboard gate driversat all. Their PWM outputs are only intended to drive the high impedance input to a driver such as theUCC27423/4/5. Finally, the control IC may be under thermal stress due to power dissipation, and an externaldriver can help by moving the heat from the controller to an external package.6www.ti.comUCC27423, UCC27424, UCC27425SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004APPLICATION INFORMATIONInput StageThe input thresholds have a 3.3-V logic sensitivity over the full range of VDD voltages; yet it is equally compatiblewith 0 to VDD signals. The inputs of UCC27423/4/5 family of drivers are designed to withstand 500-mA reversecurrent without either damage to the IC for logic upset. The input stage of each driver should be driven by a signalwith a short rise or fall time. This condition is satisfied in typical power supply applications, where the inputsignals are provided by a PWM controller or logic gates with fast transition times (<200 ns). The input stagesto the drivers function as a digital gate, and they are not intended for applications where a slow changing inputvoltage is used to generate a switching output when the logic threshold of the input section is reached. Whilethis may not be harmful to the driver, the output of the driver may switch repeatedly at a high frequency.Users should not attempt to shape the input signals to the driver in an attempt to slow down (or delay) the signalat the output. If limiting the rise or fall times to the power device is desired, limit the rise or fall times to the powerdevice, then an external resistance can be added between the output of the driver and the load device, whichis generally a power MOSFET gate. The external resistor may also help remove power dissipation from thedevoce package, as discussed in the section on Thermal Considerations.Output StageInverting outputs of the UCC27423 and OUTA of the UCC27425 are intended to drive external P-channelMOSFETs. Noninverting outputs of the UCC27424 and OUTB of the UCC27425 are intended to drive externalN-channel MOSFETs.Each output stage is capable of supplying ±4-A peak current pulses and swings to both VDD and GND. Thepullup/ pulldown circuits of the driver are constructed of bipolar and MOSFET transistors in parallel. The peakoutput current rating is the combined current from the bipolar and MOSFET transistors. The output resistanceis the RDS(on) of the MOSFET transistor when the voltage on the driver output is less than the saturation voltageof the bipolar transistor. Each output stage also provides a very low impedance to overshoot and undershootdue to the body diode of the external MOSFET. This means that in many cases, external-schottky-clamp diodesare not required.The UCC27423 family delivers 4-A of gate drive where it is most needed during the MOSFET switchingtransition – at the Miller plateau region – providing improved efficiency gains. A unique BiPolar and MOSFEThybrid output stage in parallel also allows efficient current sourcing at low supply voltages.www.ti.com7UCC27423, UCC27424, UCC27425SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004APPLICATION INFORMATIONSource/Sink Capabilities During Miller PlateauLarge power MOSFETs present a large load to the control circuitry. Proper drive is required for efficient, reliableoperation. The UCC27423/4/5 drivers have been optimized to provide maximum drive to a power MOSFETduring the Miller plateau region of the switching transition. This interval occurs while the drain voltage is swingingbetween the voltage levels dictated by the power topology, requiring the charging/discharging of the drain-gatecapacitance with current supplied or removed by the driver device. [1]Two circuits are used to test the current capabilities of the UCC27423 driver. In each case external circuitry isadded to clamp the output near 5 V while the IC is sinking or sourcing current. An input pulse of 250 ns is appliedat a frequency of 1 kHz in the proper polarity for the respective test. In each test there is a transient period wherethe current peaked up and then settled down to a steady-state value. The noted current measurements aremade at a time of 200 ns after the input pulse is applied, after the initial transient.The first circuit in Figure 2 is used to verify the current sink capability when the output of the driver is clampedaround 5 V, a typical value of gate-source voltage during the Miller plateau region. The UCC27423 is found tosink 4.5 A at VDD = 15 V and 4.28 A at VDD = 12 V.VDDUCC27423INPUT1ENBAENBBOUTA8DSCHOTTKY7C21µFC3100µF+VSUPPLY5.5 V10Ω2INA3GNDINBVDDOUTB6451µFCER100µFAL ELRSNS0.1ΩVSNSUDG−01065Figure 3. 8www.ti.comUCC27423, UCC27424, UCC27425SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004APPLICATION INFORMATIONThe circuit shown in Figure 3 is used to test the current source capability with the output clamped to around 5 Vwith a string of Zener diodes. The UCC27423 is found to source 4.8 A at VDD = 15 V and 3.7 A at VDD = 12 V.VDDUCC27423ENBA1ENBB2INAOUTAINPUT8DSCHOTTKY7C21µFC3100µF+DADJ5.5 V10Ω3GND4INBVDD6OUTB51µFCER100µFAL ELVSNSRSNS0.1ΩUDG−01066Figure 4. It should be noted that the current sink capability is slightly stronger than the current source capability at lowerVDD. This is due to the differences in the structure of the bipolar-MOSFET power output section, where thecurrent source is a P-channel MOSFET and the current sink has an N-channel MOSFET.In a large majority of applications it is advantageous that the turn-off capability of a driver is stronger than theturn-on capability. This helps to ensure that the MOSFET is held OFF during common power supply transientswhich may turn the device back ON.Parallel OutputsThe A and B drivers may be combined into a single driver by connecting the INA/INB inputs together and theOUTA/OUTB outputs together. Then, a single signal can control the paralleled combination as shown inFigure 4.VDDUCC27423ENBA1ENBB2INAOUTAINPUT873GND4INBVDD6OUTB51µFCER2.2µFCLOADUDG−01067Figure 5. www.ti.com9UCC27423, UCC27424, UCC27425SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004APPLICATION INFORMATIONOperational Waveforms and Circuit LayoutFigure 5 shows the circuit performance achievable with a single driver (1/2 of the 8-pin IC) driving a 10-nF load.The input pulsewidth (not shown) is set to 300 ns to show both transitions in the output waveform. Note the linearrise and fall edges of the switching waveforms. This is due to the constant output current characteristic of thedriver as opposed to the resistive output impedance of traditional MOSFET-based gate drivers.Figure 6. In a power driver operating at high frequency, it is a significant challenge to get clean waveforms without muchovershoot/undershoot and ringing. The low output impedance of these drivers produces waveforms with highdi/dt. This tends to induce ringing in the parasitic inductances. Utmost care must be used in the circuit layout.It is advantageous to connect the driver IC as close as possible to the leads. The driver IC layout has groundon the opposite side of the output, so the ground should be connected to the bypass capacitors and the loadwith copper trace as wide as possible. These connections should also be made with a small enclosed loop areato minimize the inductance.VDDAlthough quiescent VDD current is very low, total supply current will be higher, depending on OUTA and OUTBcurrent and the programmed oscillator frequency. Total VDD current is the sum of quiescent VDD current andthe average OUT current. Knowing the operating frequency and the MOSFET gate charge (Qg), average OUTcurrent can be calculated from:IOUT = Qg x f, where f is frequencyFor the best high-speed circuit performance, two VDD bypass capacitors are recommended tp prevent noiseproblems. The use of surface mount components is highly recommended. A 0.1-µF ceramic capacitor shouldbe located closest to the VDD to ground connection. In addition, a larger capacitor (such as 1-µF) with relativelylow ESR should be connected in parallel, to help deliver the high current peaks to the load. The parallelcombination of capacitors should present a low impedance characteristic for the expected current levels in thedriver application.10www.ti.comUCC27423, UCC27424, UCC27425SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004APPLICATION INFORMATIONDrive Current and Power RequirementsThe UCC27423/4/5 family of drivers are capable of delivering 4-A of current to a MOSFET gate for a period ofseveral hundred nanoseconds. High peak current is required to turn the device ON quickly. Then, to turn thedevice OFF, the driver is required to sink a similar amount of current to ground. This repeats at the operatingfrequency of the power device. A MOSFET is used in this discussion because it is the most common type ofswitching device used in high frequency power conversion equipment.References 1 and 2 discuss the current required to drive a power MOSFET and other capacitive-input switchingdevices. Reference 2 includes information on the previous generation of bipolar IC gate drivers.When a driver IC is tested with a discrete, capacitive load it is a fairly simple matter to calculate the power thatis required from the bias supply. The energy that must be transferred from the bias supply to charge the capacitoris given by:E+1CV2, where C is the load capacitor and V is the bias voltage feeding the driver.2There is an equal amount of energy transferred to ground when the capacitor is discharged. This leads to apower loss given by the following:P+2 1CV2f, where f is the switching frequency.2This power is dissipated in the resistive elements of the circuit. Thus, with no external resistor between the driverand gate, this power is dissipated inside the driver. Half of the total power is dissipated when the capacitor ischarged, and the other half is dissipated when the capacitor is discharged. An actual example using theconditions of the previous gate drive waveform should help clarify this.With VDD = 12 V, CLOAD = 10 nF, and f = 300 kHz, the power loss can be calculated as:P = 10 nF x (12)2 x (300 kHz) = 0.432 WWith a 12-V supply, this would equate to a current of:I+P+0.432W+0.036AV12VThe actual current measured from the supply was 0.037 A, and is very close to the predicted value. But, theIDD current that is due to the IC internal consumption should be considered. With no load the IC current drawis 0.0027 A. Under this condition the output rise and fall times are faster than with a load. This could lead to analmost insignificant, yet measurable current due to cross-conduction in the output stages of the driver. However,these small current differences are buried in the high frequency switching spikes, and are beyond themeasurement capabilities of a basic lab setup. The measured current with 10-nF load is reasonably close tothat expected.www.ti.com11UCC27423, UCC27424, UCC27425SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004APPLICATION INFORMATIONThe switching load presented by a power MOSFET can be converted to an equivalent capacitance by examiningthe gate charge required to switch the device. This gate charge includes the effects of the input capacitanceplus the added charge needed to swing the drain of the device between the ON and OFF states. Mostmanufacturers provide specifications that provide the typical and maximum gate charge, in nC, to switch thedevice under specified conditions. Using the gate charge Qg, one can determine the power that must bedissipated when charging a capacitor. This is done by using the equivalence Qg = CeffV to provide the followingequation for power:P+C V2 f+Qg fThis equation allows a power designer to calculate the bias power required to drive a specific MOSFET gateat a specific bias voltage.EnableUCC27423/4/5 provides dual Enable inputs for improved control of each driver channel operation. The inputsincorporate logic compatible thresholds with hysteresis. They are internally pulled up to VDD with 100-kΩresistor for active high operation. When ENBA and ENBB are driven high, the drivers are enabled and whenENBA and ENBB are low, the drivers are disabled. The default state of the Enable pin is to enable the driverand therefore can be left open for standard operation. The output states when the drivers are disabled is lowregardless of the input state. See the truth table of Table 1 for the operation using enable logic.Enable input are compatible with both logic signals and slow changing analog signals. They can be directlydriven or a power−up delay can be programmed with a capacitor between ENBA, ENBB and AGND. ENBA andENBB control input A and input B respectively.12www.ti.comUCC27423, UCC27424, UCC27425SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004THERMAL INFORMATIONThe useful range of a driver is greatly affected by the drive power requirements of the load and the thermalcharacteristics of the IC package. In order for a power driver to be useful over a particular temperature rangethe package must allow for the efficient removal of the heat produced while keeping the junction temperaturewithin rated limits. The UCC27423/4/5 family of drivers is available in three different packages to cover a rangeof application requirements.As shown in the power dissipation rating table, the SOIC-8 (D) and PDIP-8 (P) packages each have a powerrating of around 0.5 W with TA = 70°C. This limit is imposed in conjunction with the power derating factor alsogiven in the table. Note that the power dissipation in our earlier example is 0.432 W with a 10-nF load, 12 VDD,switched at 300 kHz. Thus, only one load of this size could be driven using the D or P package, even if the twoonboard drivers are paralleled. The difficulties with heat removal limit the drive available in the older packages.The MSOP PowerPAD-8 (DGN) package significantly relieves this concern by offering an effective means ofremoving the heat from the semiconductor junction. As illustrated in Reference 3, the PowerPAD packages offera leadframe die pad that is exposed at the base of the package. This pad is soldered to the copper on the PCboard directly underneath the IC package, reducing the Θjc down to 4.7°C/W. Data is presented in Reference 3to show that the power dissipation can be quadrupled in the PowerPAD configuration when compared to thestandard packages. The PC board must be designed with thermal lands and thermal vias to complete the heatremoval subsystem, as summarized in Reference 4. This allows a significant improvement in heatsinking overthat available in the D or P packages, and is shown to more than double the power capability of the D and Ppackages. Note that the PowerPAD is not directly connected to any leads of the package. However, it iselectrically and thermally connected to the substrate which is the ground of the device.References1.Power Supply Seminar SEM−1400 Topic 2: Design And Application Guide For High Speed MOSFETGate Drive Circuits, by Laszlo Balogh, Texas Instruments Literature No. SLUP133.2.Application Note, Practical Considerations in High Performance MOSFET, IGBT and MCT Gate DriveCircuits, by Bill Andreycak, Texas Instruments Literature No. SLUA1053.Technical Brief, PowerPad Thermally Enhanced Package, Texas Instruments Literature No. SLMA0024.Application Brief, PowerPAD Made Easy, Texas Instruments Literature No. SLMA004Related ProductsProductUCC37323/4/5UCC37321/2TPS2811/12/13TPS2814/15TPS2816/17/18/19TPS2828/29Dual 4-A Low-Side DriversSingle 9-A Low-Side Driver with EnableDual 2-A Low-Side Drivers with Internal RegulatorDual 2-A Low-Side Drivers with Two Inputs per ChannelSingle 2-A Low-Side Driver with Internal RegulatorSingle 2-A Low-Side DriverDescriptionPackagesMSOP-8 PowerPAD, SOIC-8, PDIP-8MSOP-8 PowerPAD, SOIC-8, PDIP-8TSSOP-8, SOIC-8, PDIP-8TSSOP-8, SOIC-8, PDIP-85-Pin SOT−235-Pin SOT−23www.ti.com13UCC27423, UCC27424, UCC27425SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004 TYPICAL CHARACTERISTICSSUPPLY CURRENTvsFREQUENCY (VDD = 4.5 V)100100SUPPLY CURRENTvsFREQUENCY (VDD = 8.0 V)80IDD − Supply Current − mAIDD − Supply Current − mA10 nF608010 nF604.7 nF404.7 nF 2.2 nF1 nF402.2 nF 1 nF2020470 pF00500 K1M1.5 Mf - Frequency − Hz470 pF2M00500 K1M1.5 M2Mf - Frequency − HzFigure 7SUPPLY CURRENTvsFREQUENCY (VDD = 12 V)150200Figure 8SUPPLY CURRENTvsFREQUENCY (VDD = 15 V)IDD − Supply Current − mA10010 nFIDD − Supply Current − mA15010 nF4.7 nF4.7 nF1002.2 nF2.2 nF501 nF501 nF470 pF00500 K1M1.5 M2Mf - Frequency − Hz00500 K1M470 pF1.5 M2Mf - Frequency − HzFigure 9Figure 1014www.ti.comUCC27423, UCC27424, UCC27425SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004TYPICAL CHARACTERISTICSSUPPLY CURRENTvsSUPPLY VOLTAGE (CLOAD = 2.2 nF)90802 MHz70IDD − Supply Current − mA605040302010046810121416500 kHz200 kHz100/50 kHz2004914VDD − Supply Voltage − VVDD − Supply Voltage − V1 MHzIDD − Supply Current − mA1202 MHz1008060500 kHz40200 kHz100 kHz50/20 kHz191 MHz160140SUPPLY CURRENTvsSUPPLY VOLTAGE (CLOAD = 4.7 nF)Figure 11SUPPLY CURRENTvsSUPPLY VOLTAGE (UCC27423)0.90.60Figure 12SUPPLY CURRENTvsSUPPLY VOLTAGE (UCC27424)0.8IDD − Supply Current − mAInput = VDD0.7VDD − Supply Voltage − V0.55Input = VDD0.50Input = 0 V0.450.60.50.400.4Input = 0 V0.3468101214160.350.3046VDD − Supply Voltage − V81012VDD − Supply Voltage − V1416Figure 13Figure 14www.ti.com15UCC27423, UCC27424, UCC27425SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004TYPICAL CHARACTERISTICSSUPPLY CURRENTvsSUPPLY VOLTAGE (UCC27425)0.750.70IDD − Supply Current − mA0.650.600.550.500.450.400.350.3046810121416VDD − Supply Voltage − V0−50050TJ − Temperature − °C100150Input = 0 VInput = VDDtr/tf − Rise/Fall Time − ns20tr25RISE TIME/FALL TIMEvsTEMPERATURE (UCC27423)15tf105Figure 15RISE TIMEvsSUPPLY VOLTAGE0.60.60.60.510 nF0.6tr − Rise Time − ns0.4tr − Fall Time − ns0.50.40.3Figure 16FALL TIMEvsSUPPLY VOLTAGE10 nF0.34.7 nF4.7 nF0.21 nF0.1470 pF046810121416VDD − Supply Voltage − V2.2 nF2.2 nF0.20.1470 pF046810121416VDD − Supply Voltage − V1 nFFigure 17Figure 1816www.ti.comUCC27423, UCC27424, UCC27425SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004TYPICAL CHARACTERISTICSDELAY TIME (tD1)vsSUPPLY VOLTAGE (UCC27423)302826tD1 − Delay Time − ns2422201816141246810VDD − Supply Voltage − V2.2 nF470 pF1 nF2012141646810121416VDD − Supply Voltage − V4.7 nF10 nFtD2 − Delay Time − ns383634323028262422470 pF1 nF2.2 nF4.7 nF10 nFDELAY TIME (tD2)vsSUPPLY VOLTAGE (UCC27423)Figure 19ENABLE THRESHOLD AND HYSTERESISvsTEMPERATUREFigure 20ENABLE RESISTANCEvsTEMPERATURE150140RENBL − Enable Resistance − Ω1301201101009080706050−503.0Enable threshold and hysteresis − V2.5ENBL − ON2.01.51.0ENBL − OFF0.5ENBL − HYSTERESIS0−50−250255075TJ − Temperature − °C100125−250255075100125TJ − Temperature − °CFigure 21Figure 22www.ti.com17UCC27423, UCC27424, UCC27425SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004TYPICAL CHARACTERISTICSOUTPUT BEHAVIORvsSUPPLY VOLTAGE (INVERTING)IN = GNDENBL = VDDOUTPUT BEHAVIORvsSUPPLY VOLTAGE (INVERTING)IN = GNDENBL = VDDVDD − Supply Voltage − V 1 V/divVDD − Supply Voltage − V 1 V/divVDDOUTVDD0 V0 VOUT10 nF Between Output and GND50 µs/div10 nF Between Output and GND50 µs/divFigure 23OUTPUT BEHAVIORvsVDD (INVERTING)IN = VDDENBL = VDDVDD − Supply Voltage − V 1 V/divVDD − Supply Voltage − V 1 V/divFigure 24OUTPUT BEHAVIORvsVDD (INVERTING)IN = VDDENBL = VDDVDDVDDOUTOUT0 V0 V10 nF Between Output and GND50 µs/div10 nF Between Output and GND50 µs/divFigure 25Figure 2618www.ti.comUCC27423, UCC27424, UCC27425SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004TYPICAL CHARACTERISTICSOUTPUT BEHAVIORvsVDD (NON-INVERTING)IN = VDDENBL = VDDOUTPUT BEHAVIORvsVDD (NON-INVERTING)IN = VDDENBL = VDDVDD − Supply Voltage − V 1 V/divVDD − Supply Voltage − V 1 V/divVDDOUTVDDOUT0 V0 V10 nF Between Output and GND50 µs/div10 nF Between Output and GND50 µs/divFigure 27OUTPUT BEHAVIORvsVDD (NON-INVERTING)IN = GNDENBL = VDDFigure 28OUTPUT BEHAVIORvsVDD (NON-INVERTING)IN = GNDENBL = VDDVDD − Supply Voltage − V 1 V/divVDDVDD − Supply Voltage − V 1 V/divVDDOUTOUT0 V0 V10 nF Between Output and GND50 µs/div10 nF Between Output and GND50 µs/divFigure 29Figure 30www.ti.com19UCC27423, UCC27424, UCC27425SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004TYPICAL CHARACTERISTICSINPUT THRESHOLDvsTEMPERATURE2.0VON − Input Threshold Voltage − V1.91.81.71.61.51.41.31.2−50VDD = 10 VVDD = 15 VVDD = 4.5 V−250255075100125TJ − Temperature − °CFigure 3120www.ti.comUCC27423, UCC27424, UCC27425SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004MECHANICAL DATAD (R-PDSO-G**) 8 PINS SHOWN0.050 (1,27)850.020 (0,51)0.014 (0,35)0.010 (0,25)PLASTIC SMALL-OUTLINE PACKAGE0.244 (6,20)0.228 (5,80)0.157 (4,00)0.150 (3,81)0.008 (0,20) NOMGage Plane1A40°− 8°0.044 (1,12)0.016 (0,40)0.010 (0,25)Seating Plane0.069 (1,75) MAX0.010 (0,25)0.004 (0,10)0.004 (0,10)PINS **DIMA MAXA MIN80.197(5,00)0.189(4,80)140.344(8,75)0.337(8,55)160.394(10,00)0.386(9,80)4040047/E 09/01NOTES:A.B.C.D.All linear dimensions are in inches (millimeters).This drawing is subject to change without notice.Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).Falls within JEDEC MS-012www.ti.com21UCC27423, UCC27424, UCC27425SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004MECHANICAL DATADGN (MSOP) 0,380,2585PowerPAD PLASTIC SMALL-OUTLINE PACKAGE0,650,25MThermal Pad(See Note F)0,15 NOM3,052,954,984,78Gage Plane0,2513,052,9540°−6°0,690,41Seating Plane1,07 MAX0,150,050,104073271/A 04/98NOTES:A.B.C.D.E.F.All linear dimensions are in millimeters.This drawing is subject to change without notice.Body dimensions include mold flash or protrusions.Falls within JEDEC MO-187The package thermal performance may be enhanced by attaching an external heat sink to the thermal pad.The PowerPAD is not directly connected to any leads of the package. However, it is electrically and thermally connected to thesubstrate which is the ground of the device. The exposed pad dimension is 1.3 mm x 1.7 mm. However, the tolerances can be+1.05/−0.05 mm (+ 41 / −2 mils) due to position and mold flow variation.G.For additional information on the PowerPADt package and how to take advantage of its heat dissipating abilities, refer to TechnicalBrief, PowerPad Thermally Enhanced Package, Texas Instrument s Literature No. SLMA002 and Application Brief, PowerPad MadeEasy, Texas Instruments Literature No. SLMA004. Both documents are available at www.ti.com.PowerPADt is a trademark of Texas Instruments Incorporated.22www.ti.comUCC27423, UCC27424, UCC27425SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004MECHANICAL DATAP (PDIP)0.400 (10,60)0.355 (9,02)85PLASTIC DUAL-IN-LINE0.260 (6,60)0.240 (6,10)140.070 (1,78) MAX0.325 (8,26)0.300 (7,62)0.015 (0,38)0.200 (5,08) MAXSeating Plane0.125 (3,18) MIN0.010 (0,25) NOMGage Plane0.020 (0,51) MIN0.100 (2,54)0.021 (0,53)0.015 (0,38)0.010 (0,25)M0.430 (10,92)MAX4040082/D 05/98NOTES:A.All linear dimensions are in inches (millimeters).B.This drawing is subject to change without notice.C.Falls within JEDEC MS-001For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htmwww.ti.com23PACKAGEOPTIONADDENDUM

www.ti.com

18-Sep-2008

PACKAGINGINFORMATION

OrderableDeviceUCC27423DUCC27423DG4UCC27423DGN

Status(1)ACTIVEACTIVEACTIVE

PackageTypeSOICSOICMSOP-Power PADMSOP-Power PADMSOP-Power PADMSOP-Power PADSOICSOICPDIPPDIPSOICSOICMSOP-Power PADMSOP-Power PADMSOP-Power PADMSOP-Power PADSOICSOICPDIPPDIPSOICSOIC

PackageDrawing

DDDGN

PinsPackageEcoPlan(2)

Qty888

757580

Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)

Lead/BallFinishCUNIPDAUCUNIPDAUCUNIPDAU

MSLPeakTemp(3)Level-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIM

UCC27423DGNG4ACTIVEDGN880CUNIPDAULevel-1-260C-UNLIM

UCC27423DGNRACTIVEDGN8

2500Green(RoHS&

noSb/Br)2500Green(RoHS&

noSb/Br)5050757580

Pb-Free(RoHS)Pb-Free(RoHS)Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)

CUNIPDAULevel-1-260C-UNLIM

UCC27423DGNRG4ACTIVEDGN8CUNIPDAULevel-1-260C-UNLIM

UCC27423DRUCC27423DRG4UCC27423PUCC27423PE4UCC27424DUCC27424DG4UCC27424DGN

ACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVE

DDPPDDDGN

8888888

CUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAU

Level-1-260C-UNLIMLevel-1-260C-UNLIMN/AforPkgTypeN/AforPkgTypeLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIM

UCC27424DGNG4ACTIVEDGN880CUNIPDAULevel-1-260C-UNLIM

UCC27424DGNRACTIVEDGN8

2500Green(RoHS&

noSb/Br)2500Green(RoHS&

noSb/Br)50507575

Pb-Free(RoHS)Pb-Free(RoHS)Green(RoHS&noSb/Br)Green(RoHS&

CUNIPDAULevel-1-260C-UNLIM

UCC27424DGNRG4ACTIVEDGN8CUNIPDAULevel-1-260C-UNLIM

UCC27424DRUCC27424DRG4UCC27424PUCC27424PE4UCC27425DUCC27425DG4

ACTIVEACTIVEACTIVEACTIVEACTIVEACTIVE

DDPPDD

888888

CUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAU

Level-1-260C-UNLIMLevel-1-260C-UNLIMN/AforPkgTypeN/AforPkgTypeLevel-1-260C-UNLIMLevel-1-260C-UNLIM

Addendum-Page1

PACKAGEOPTIONADDENDUM

www.ti.com

18-Sep-2008

OrderableDevice

Status(1)

PackageTypeMSOP-Power PADMSOP-Power PADMSOP-Power PADMSOP-Power PADSOICSOICPDIPPDIP

PackageDrawingDGN

PinsPackageEcoPlan(2)

Qty

noSb/Br)

Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)

Lead/BallFinish

MSLPeakTemp(3)

UCC27425DGNACTIVECUNIPDAULevel-1-260C-UNLIM

UCC27425DGNG4ACTIVEDGN880CUNIPDAULevel-1-260C-UNLIM

UCC27425DGNRACTIVEDGN8

2500Green(RoHS&

noSb/Br)2500Green(RoHS&

noSb/Br)5050

Pb-Free(RoHS)Pb-Free(RoHS)

CUNIPDAULevel-1-260C-UNLIM

UCC27425DGNRG4ACTIVEDGN8CUNIPDAULevel-1-260C-UNLIM

UCC27425DRUCC27425DRG4UCC27425PUCC27425PE4

(1)

ACTIVEACTIVEACTIVEACTIVE

DDPP

8888

CUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAU

Level-1-260C-UNLIMLevel-1-260C-UNLIMN/AforPkgTypeN/AforPkgType

Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicerecommendedfornewdesigns.

LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.

NRND:Notrecommendedfornewdesigns.Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.

PREVIEW:Devicehasbeenannouncedbutisnotinproduction.Samplesmayormaynotbeavailable.OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.

(2)

EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS),Pb-Free(RoHSExempt),orGreen(RoHS&noSb/Br)-pleasecheckhttp://www.ti.com/productcontentforthelatestavailabilityinformationandadditionalproductcontentdetails.TBD:ThePb-Free/Greenconversionplanhasnotbeendefined.

Pb-Free(RoHS):TI'sterms\"Lead-Free\"or\"Pb-Free\"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirementsforall6substances,includingtherequirementthatleadnotexceed0.1%byweightinhomogeneousmaterials.Wheredesignedtobesolderedathightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses.

Pb-Free(RoHSExempt):ThiscomponenthasaRoHSexemptionforeither1)lead-basedflip-chipsolderbumpsusedbetweenthedieandpackage,or2)lead-baseddieadhesiveusedbetweenthedieandleadframe.ThecomponentisotherwiseconsideredPb-Free(RoHScompatible)asdefinedabove.

Green(RoHS&noSb/Br):TIdefines\"Green\"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflameretardants(BrorSbdonotexceed0.1%byweightinhomogeneousmaterial)

(3)

MSL,PeakTemp.--TheMoistureSensitivityLevelratingaccordingtotheJEDECindustrystandardclassifications,andpeaksoldertemperature.

ImportantInformationandDisclaimer:TheinformationprovidedonthispagerepresentsTI'sknowledgeandbeliefasofthedatethatitisprovided.TIbasesitsknowledgeandbeliefoninformationprovidedbythirdparties,andmakesnorepresentationorwarrantyastotheaccuracyofsuchinformation.Effortsareunderwaytobetterintegrateinformationfromthirdparties.TIhastakenandcontinuestotakereasonablestepstoproviderepresentativeandaccurateinformationbutmaynothaveconducteddestructivetestingorchemicalanalysisonincomingmaterialsandchemicals.TIandTIsuppliersconsidercertaininformationtobeproprietary,andthusCASnumbersandotherlimitedinformationmaynotbeavailableforrelease.

InnoeventshallTI'sliabilityarisingoutofsuchinformationexceedthetotalpurchasepriceoftheTIpart(s)atissueinthisdocumentsoldbyTItoCustomeronanannualbasis.

OTHERQUALIFIEDVERSIONSOFUCC27424:

Addendum-Page2

PACKAGEOPTIONADDENDUM

www.ti.com

18-Sep-2008

•EnhancedProduct:UCC27424-EP

NOTE:QualifiedVersionDefinitions:

•EnhancedProduct-SupportsDefense,AerospaceandMedicalApplications

Addendum-Page3

PACKAGEMATERIALSINFORMATION

www.ti.com

29-Jul-2008

TAPEANDREELINFORMATION

*Alldimensionsarenominal

Device

PackagePackagePinsTypeDrawingMSOP-Power PADSOICMSOP-Power PADSOICMSOP-Power PADSOIC

DGN

SPQ

ReelReelDiameterWidth(mm)W1(mm)330.0

12.4

A0(mm)B0(mm)K0(mm)

P1(mm)8.0

WPin1(mm)Quadrant12.0

UCC27423DGNR25005.33.41.4

UCC27423DRUCC27424DGNR

DDGN

25002500

330.0330.0

12.412.4

6.45.3

5.23.4

2.11.4

8.08.0

12.012.0

Q1Q1

UCC27424DRUCC27425DGNR

DDGN

25002500

330.0330.0

12.412.4

6.45.3

5.23.4

2.11.4

8.08.0

12.012.0

Q1Q1

UCC27425DRD82500330.012.46.45.22.18.012.0Q1

PackMaterials-Page1

PACKAGEMATERIALSINFORMATION

www.ti.com

29-Jul-2008

*Alldimensionsarenominal

DeviceUCC27423DGNRUCC27423DRUCC27424DGNRUCC27424DRUCC27425DGNRUCC27425DR

PackageTypeMSOP-PowerPAD

SOICMSOP-PowerPAD

SOIC

PackageDrawing

DGNDDGNDDGND

Pins888888

SPQ250025002500250025002500

Length(mm)

346.0340.5346.0340.5346.0340.5

Width(mm)346.0338.1346.0338.1346.0338.1

Height(mm)

29.020.629.020.629.020.6

PackMaterials-Page2

MECHANICAL DATAMPDI001A – JANUARY 1995 – REVISED JUNE 1999P (R-PDIP-T8)0.400 (10,60)0.355 (9,02)85PLASTIC DUAL-IN-LINE0.260 (6,60)0.240 (6,10)140.070 (1,78) MAX0.325 (8,26)0.300 (7,62)0.015 (0,38)0.200 (5,08) MAXSeating Plane0.125 (3,18) MIN0.010 (0,25) NOMGage Plane0.020 (0,51) MIN0.100 (2,54)0.021 (0,53)0.015 (0,38)0.010 (0,25)M0.430 (10,92)MAX4040082/D 05/98NOTES:A.All linear dimensions are in inches (millimeters).B.This drawing is subject to change without notice.C.Falls within JEDEC MS-001For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htmPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•IMPORTANTNOTICE

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